1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
3 * Copyright (c) 2022 MediaTek Inc.
4 * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
7 #ifndef _DT_BINDINGS_POWER_MT8186_POWER_H
8 #define _DT_BINDINGS_POWER_MT8186_POWER_H
10 #define MT8186_POWER_DOMAIN_MFG0 0
11 #define MT8186_POWER_DOMAIN_MFG1 1
12 #define MT8186_POWER_DOMAIN_MFG2 2
13 #define MT8186_POWER_DOMAIN_MFG3 3
14 #define MT8186_POWER_DOMAIN_SSUSB 4
15 #define MT8186_POWER_DOMAIN_SSUSB_P1 5
16 #define MT8186_POWER_DOMAIN_DIS 6
17 #define MT8186_POWER_DOMAIN_IMG 7
18 #define MT8186_POWER_DOMAIN_IMG2 8
19 #define MT8186_POWER_DOMAIN_IPE 9
20 #define MT8186_POWER_DOMAIN_CAM 10
21 #define MT8186_POWER_DOMAIN_CAM_RAWA 11
22 #define MT8186_POWER_DOMAIN_CAM_RAWB 12
23 #define MT8186_POWER_DOMAIN_VENC 13
24 #define MT8186_POWER_DOMAIN_VDEC 14
25 #define MT8186_POWER_DOMAIN_WPE 15
26 #define MT8186_POWER_DOMAIN_CONN_ON 16
27 #define MT8186_POWER_DOMAIN_CSIRX_TOP 17
28 #define MT8186_POWER_DOMAIN_ADSP_AO 18
29 #define MT8186_POWER_DOMAIN_ADSP_INFRA 19
30 #define MT8186_POWER_DOMAIN_ADSP_TOP 20
32 #endif /* _DT_BINDINGS_POWER_MT8186_POWER_H */