1 /* SPDX-License-Identifier: GPL-2.0 */
3 * MIO pin configuration defines for Xilinx Zynq
5 * Copyright (C) 2021 Xilinx, Inc.
8 #ifndef _DT_BINDINGS_PINCTRL_ZYNQ_H
9 #define _DT_BINDINGS_PINCTRL_ZYNQ_H
11 /* Configuration options for different power supplies */
12 #define IO_STANDARD_LVCMOS18 1
13 #define IO_STANDARD_LVCMOS25 2
14 #define IO_STANDARD_LVCMOS33 3
15 #define IO_STANDARD_HSTL 4
17 #endif /* _DT_BINDINGS_PINCTRL_ZYNQ_H */