1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
3 * Qualcomm SM6350 interconnect IDs
5 * Copyright (C) 2022 Luca Weiss <luca.weiss@fairphone.com>
8 #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM6350_H
9 #define __DT_BINDINGS_INTERCONNECT_QCOM_SM6350_H
11 #define MASTER_A1NOC_CFG 0
12 #define MASTER_QUP_0 1
14 #define MASTER_UFS_MEM 3
15 #define A1NOC_SNOC_SLV 4
16 #define SLAVE_SERVICE_A1NOC 5
18 #define MASTER_A2NOC_CFG 0
19 #define MASTER_QDSS_BAM 1
20 #define MASTER_QUP_1 2
21 #define MASTER_CRYPTO_CORE_0 3
23 #define MASTER_QDSS_ETR 5
24 #define MASTER_SDCC_2 6
26 #define A2NOC_SNOC_SLV 8
27 #define SLAVE_SERVICE_A2NOC 9
29 #define MASTER_CAMNOC_HF0_UNCOMP 0
30 #define MASTER_CAMNOC_ICP_UNCOMP 1
31 #define MASTER_CAMNOC_SF_UNCOMP 2
32 #define MASTER_QUP_CORE_0 3
33 #define MASTER_QUP_CORE_1 4
35 #define SLAVE_CAMNOC_UNCOMP 6
36 #define SLAVE_QUP_CORE_0 7
37 #define SLAVE_QUP_CORE_1 8
38 #define SLAVE_EBI_CH0 9
41 #define MASTER_NPU_PROC 1
42 #define SLAVE_CDSP_GEM_NOC 2
44 #define SNOC_CNOC_MAS 0
45 #define MASTER_QDSS_DAP 1
46 #define SLAVE_A1NOC_CFG 2
47 #define SLAVE_A2NOC_CFG 3
48 #define SLAVE_AHB2PHY 4
49 #define SLAVE_AHB2PHY_2 5
51 #define SLAVE_BOOT_ROM 7
52 #define SLAVE_CAMERA_CFG 8
53 #define SLAVE_CAMERA_NRT_THROTTLE_CFG 9
54 #define SLAVE_CAMERA_RT_THROTTLE_CFG 10
55 #define SLAVE_CLK_CTL 11
56 #define SLAVE_RBCPR_CX_CFG 12
57 #define SLAVE_RBCPR_MX_CFG 13
58 #define SLAVE_CRYPTO_0_CFG 14
59 #define SLAVE_DCC_CFG 15
60 #define SLAVE_CNOC_DDRSS 16
61 #define SLAVE_DISPLAY_CFG 17
62 #define SLAVE_DISPLAY_THROTTLE_CFG 18
63 #define SLAVE_EMMC_CFG 19
65 #define SLAVE_GRAPHICS_3D_CFG 21
66 #define SLAVE_IMEM_CFG 22
67 #define SLAVE_IPA_CFG 23
68 #define SLAVE_CNOC_MNOC_CFG 24
69 #define SLAVE_CNOC_MSS 25
70 #define SLAVE_NPU_CFG 26
72 #define SLAVE_PIMEM_CFG 28
74 #define SLAVE_QDSS_CFG 30
75 #define SLAVE_QM_CFG 31
76 #define SLAVE_QM_MPU_CFG 32
77 #define SLAVE_QUP_0 33
78 #define SLAVE_QUP_1 34
79 #define SLAVE_SDCC_2 35
80 #define SLAVE_SECURITY 36
81 #define SLAVE_SNOC_CFG 37
83 #define SLAVE_UFS_MEM_CFG 39
85 #define SLAVE_VENUS_CFG 41
86 #define SLAVE_VENUS_THROTTLE_CFG 42
87 #define SLAVE_VSENSE_CTRL_CFG 43
88 #define SLAVE_SERVICE_CNOC 44
90 #define MASTER_CNOC_DC_NOC 0
91 #define SLAVE_GEM_NOC_CFG 1
92 #define SLAVE_LLCC_CFG 2
94 #define MASTER_AMPSS_M0 0
95 #define MASTER_SYS_TCU 1
96 #define MASTER_GEM_NOC_CFG 2
97 #define MASTER_COMPUTE_NOC 3
98 #define MASTER_MNOC_HF_MEM_NOC 4
99 #define MASTER_MNOC_SF_MEM_NOC 5
100 #define MASTER_SNOC_GC_MEM_NOC 6
101 #define MASTER_SNOC_SF_MEM_NOC 7
102 #define MASTER_GRAPHICS_3D 8
103 #define SLAVE_MCDMA_MS_MPU_CFG 9
104 #define SLAVE_MSS_PROC_MS_MPU_CFG 10
105 #define SLAVE_GEM_NOC_SNOC 11
106 #define SLAVE_LLCC 12
107 #define SLAVE_SERVICE_GEM_NOC 13
109 #define MASTER_CNOC_MNOC_CFG 0
110 #define MASTER_VIDEO_P0 1
111 #define MASTER_VIDEO_PROC 2
112 #define MASTER_CAMNOC_HF 3
113 #define MASTER_CAMNOC_ICP 4
114 #define MASTER_CAMNOC_SF 5
115 #define MASTER_MDP_PORT0 6
116 #define SLAVE_MNOC_HF_MEM_NOC 7
117 #define SLAVE_MNOC_SF_MEM_NOC 8
118 #define SLAVE_SERVICE_MNOC 9
120 #define MASTER_NPU_SYS 0
121 #define MASTER_NPU_NOC_CFG 1
122 #define SLAVE_NPU_CAL_DP0 2
123 #define SLAVE_NPU_CP 3
124 #define SLAVE_NPU_INT_DMA_BWMON_CFG 4
125 #define SLAVE_NPU_DPM 5
126 #define SLAVE_ISENSE_CFG 6
127 #define SLAVE_NPU_LLM_CFG 7
128 #define SLAVE_NPU_TCM 8
129 #define SLAVE_NPU_COMPUTE_NOC 9
130 #define SLAVE_SERVICE_NPU_NOC 10
132 #define MASTER_SNOC_CFG 0
133 #define A1NOC_SNOC_MAS 1
134 #define A2NOC_SNOC_MAS 2
135 #define MASTER_GEM_NOC_SNOC 3
136 #define MASTER_PIMEM 4
138 #define SLAVE_APPSS 6
139 #define SNOC_CNOC_SLV 7
140 #define SLAVE_SNOC_GEM_NOC_GC 8
141 #define SLAVE_SNOC_GEM_NOC_SF 9
142 #define SLAVE_OCIMEM 10
143 #define SLAVE_PIMEM 11
144 #define SLAVE_SERVICE_SNOC 12
145 #define SLAVE_QDSS_STM 13