GNU Linux-libre 6.9.1-gnu
[releases.git] / include / dt-bindings / clock / xlnx-zynqmp-clk.h
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Xilinx Zynq MPSoC Firmware layer
4  *
5  *  Copyright (C) 2014-2018 Xilinx, Inc.
6  *
7  */
8
9 #ifndef _DT_BINDINGS_CLK_ZYNQMP_H
10 #define _DT_BINDINGS_CLK_ZYNQMP_H
11
12 #define IOPLL                   0
13 #define RPLL                    1
14 #define APLL                    2
15 #define DPLL                    3
16 #define VPLL                    4
17 #define IOPLL_TO_FPD            5
18 #define RPLL_TO_FPD             6
19 #define APLL_TO_LPD             7
20 #define DPLL_TO_LPD             8
21 #define VPLL_TO_LPD             9
22 #define ACPU                    10
23 #define ACPU_HALF               11
24 #define DBF_FPD                 12
25 #define DBF_LPD                 13
26 #define DBG_TRACE               14
27 #define DBG_TSTMP               15
28 #define DP_VIDEO_REF            16
29 #define DP_AUDIO_REF            17
30 #define DP_STC_REF              18
31 #define GDMA_REF                19
32 #define DPDMA_REF               20
33 #define DDR_REF                 21
34 #define SATA_REF                22
35 #define PCIE_REF                23
36 #define GPU_REF                 24
37 #define GPU_PP0_REF             25
38 #define GPU_PP1_REF             26
39 #define TOPSW_MAIN              27
40 #define TOPSW_LSBUS             28
41 #define GTGREF0_REF             29
42 #define LPD_SWITCH              30
43 #define LPD_LSBUS               31
44 #define USB0_BUS_REF            32
45 #define USB1_BUS_REF            33
46 #define USB3_DUAL_REF           34
47 #define USB0                    35
48 #define USB1                    36
49 #define CPU_R5                  37
50 #define CPU_R5_CORE             38
51 #define CSU_SPB                 39
52 #define CSU_PLL                 40
53 #define PCAP                    41
54 #define IOU_SWITCH              42
55 #define GEM_TSU_REF             43
56 #define GEM_TSU                 44
57 #define GEM0_TX                 45
58 #define GEM1_TX                 46
59 #define GEM2_TX                 47
60 #define GEM3_TX                 48
61 #define GEM0_RX                 49
62 #define GEM1_RX                 50
63 #define GEM2_RX                 51
64 #define GEM3_RX                 52
65 #define QSPI_REF                53
66 #define SDIO0_REF               54
67 #define SDIO1_REF               55
68 #define UART0_REF               56
69 #define UART1_REF               57
70 #define SPI0_REF                58
71 #define SPI1_REF                59
72 #define NAND_REF                60
73 #define I2C0_REF                61
74 #define I2C1_REF                62
75 #define CAN0_REF                63
76 #define CAN1_REF                64
77 #define CAN0                    65
78 #define CAN1                    66
79 #define DLL_REF                 67
80 #define ADMA_REF                68
81 #define TIMESTAMP_REF           69
82 #define AMS_REF                 70
83 #define PL0_REF                 71
84 #define PL1_REF                 72
85 #define PL2_REF                 73
86 #define PL3_REF                 74
87 #define WDT                     75
88 #define IOPLL_INT               76
89 #define IOPLL_PRE_SRC           77
90 #define IOPLL_HALF              78
91 #define IOPLL_INT_MUX           79
92 #define IOPLL_POST_SRC          80
93 #define RPLL_INT                81
94 #define RPLL_PRE_SRC            82
95 #define RPLL_HALF               83
96 #define RPLL_INT_MUX            84
97 #define RPLL_POST_SRC           85
98 #define APLL_INT                86
99 #define APLL_PRE_SRC            87
100 #define APLL_HALF               88
101 #define APLL_INT_MUX            89
102 #define APLL_POST_SRC           90
103 #define DPLL_INT                91
104 #define DPLL_PRE_SRC            92
105 #define DPLL_HALF               93
106 #define DPLL_INT_MUX            94
107 #define DPLL_POST_SRC           95
108 #define VPLL_INT                96
109 #define VPLL_PRE_SRC            97
110 #define VPLL_HALF               98
111 #define VPLL_INT_MUX            99
112 #define VPLL_POST_SRC           100
113 #define CAN0_MIO                101
114 #define CAN1_MIO                102
115 #define ACPU_FULL               103
116 #define GEM0_REF                104
117 #define GEM1_REF                105
118 #define GEM2_REF                106
119 #define GEM3_REF                107
120 #define GEM0_REF_UNG            108
121 #define GEM1_REF_UNG            109
122 #define GEM2_REF_UNG            110
123 #define GEM3_REF_UNG            111
124 #define LPD_WDT                 112
125
126 #endif