GNU Linux-libre 6.9.1-gnu
[releases.git] / include / dt-bindings / clock / tegra194-clock.h
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */
3
4 #ifndef __ABI_MACH_T194_CLOCK_H
5 #define __ABI_MACH_T194_CLOCK_H
6
7 #define TEGRA194_CLK_ACTMON                     1
8 #define TEGRA194_CLK_ADSP                       2
9 #define TEGRA194_CLK_ADSPNEON                   3
10 #define TEGRA194_CLK_AHUB                       4
11 #define TEGRA194_CLK_APB2APE                    5
12 #define TEGRA194_CLK_APE                        6
13 #define TEGRA194_CLK_AUD_MCLK                   7
14 #define TEGRA194_CLK_AXI_CBB                    8
15 #define TEGRA194_CLK_CAN1                       9
16 #define TEGRA194_CLK_CAN1_HOST                  10
17 #define TEGRA194_CLK_CAN2                       11
18 #define TEGRA194_CLK_CAN2_HOST                  12
19 #define TEGRA194_CLK_CEC                        13
20 #define TEGRA194_CLK_CLK_M                      14
21 #define TEGRA194_CLK_DMIC1                      15
22 #define TEGRA194_CLK_DMIC2                      16
23 #define TEGRA194_CLK_DMIC3                      17
24 #define TEGRA194_CLK_DMIC4                      18
25 #define TEGRA194_CLK_DPAUX                      19
26 #define TEGRA194_CLK_DPAUX1                     20
27 #define TEGRA194_CLK_ACLK                       21
28 #define TEGRA194_CLK_MSS_ENCRYPT                22
29 #define TEGRA194_CLK_EQOS_RX_INPUT              23
30 #define TEGRA194_CLK_IQC2                       24
31 #define TEGRA194_CLK_AON_APB                    25
32 #define TEGRA194_CLK_AON_NIC                    26
33 #define TEGRA194_CLK_AON_CPU_NIC                27
34 #define TEGRA194_CLK_PLLA1                      28
35 #define TEGRA194_CLK_DSPK1                      29
36 #define TEGRA194_CLK_DSPK2                      30
37 #define TEGRA194_CLK_EMC                        31
38 #define TEGRA194_CLK_EQOS_AXI                   32
39 #define TEGRA194_CLK_EQOS_PTP_REF               33
40 #define TEGRA194_CLK_EQOS_RX                    34
41 #define TEGRA194_CLK_EQOS_TX                    35
42 #define TEGRA194_CLK_EXTPERIPH1                 36
43 #define TEGRA194_CLK_EXTPERIPH2                 37
44 #define TEGRA194_CLK_EXTPERIPH3                 38
45 #define TEGRA194_CLK_EXTPERIPH4                 39
46 #define TEGRA194_CLK_FUSE                       40
47 #define TEGRA194_CLK_GPCCLK                     41
48 #define TEGRA194_CLK_GPU_PWR                    42
49 #define TEGRA194_CLK_HDA                        43
50 #define TEGRA194_CLK_HDA2CODEC_2X               44
51 #define TEGRA194_CLK_HDA2HDMICODEC              45
52 #define TEGRA194_CLK_HOST1X                     46
53 #define TEGRA194_CLK_HSIC_TRK                   47
54 #define TEGRA194_CLK_I2C1                       48
55 #define TEGRA194_CLK_I2C2                       49
56 #define TEGRA194_CLK_I2C3                       50
57 #define TEGRA194_CLK_I2C4                       51
58 #define TEGRA194_CLK_I2C6                       52
59 #define TEGRA194_CLK_I2C7                       53
60 #define TEGRA194_CLK_I2C8                       54
61 #define TEGRA194_CLK_I2C9                       55
62 #define TEGRA194_CLK_I2S1                       56
63 #define TEGRA194_CLK_I2S1_SYNC_INPUT            57
64 #define TEGRA194_CLK_I2S2                       58
65 #define TEGRA194_CLK_I2S2_SYNC_INPUT            59
66 #define TEGRA194_CLK_I2S3                       60
67 #define TEGRA194_CLK_I2S3_SYNC_INPUT            61
68 #define TEGRA194_CLK_I2S4                       62
69 #define TEGRA194_CLK_I2S4_SYNC_INPUT            63
70 #define TEGRA194_CLK_I2S5                       64
71 #define TEGRA194_CLK_I2S5_SYNC_INPUT            65
72 #define TEGRA194_CLK_I2S6                       66
73 #define TEGRA194_CLK_I2S6_SYNC_INPUT            67
74 #define TEGRA194_CLK_IQC1                       68
75 #define TEGRA194_CLK_ISP                        69
76 #define TEGRA194_CLK_KFUSE                      70
77 #define TEGRA194_CLK_MAUD                       71
78 #define TEGRA194_CLK_MIPI_CAL                   72
79 #define TEGRA194_CLK_MPHY_CORE_PLL_FIXED        73
80 #define TEGRA194_CLK_MPHY_L0_RX_ANA             74
81 #define TEGRA194_CLK_MPHY_L0_RX_LS_BIT          75
82 #define TEGRA194_CLK_MPHY_L0_RX_SYMB            76
83 #define TEGRA194_CLK_MPHY_L0_TX_LS_3XBIT        77
84 #define TEGRA194_CLK_MPHY_L0_TX_SYMB            78
85 #define TEGRA194_CLK_MPHY_L1_RX_ANA             79
86 #define TEGRA194_CLK_MPHY_TX_1MHZ_REF           80
87 #define TEGRA194_CLK_NVCSI                      81
88 #define TEGRA194_CLK_NVCSILP                    82
89 #define TEGRA194_CLK_NVDEC                      83
90 #define TEGRA194_CLK_NVDISPLAYHUB               84
91 #define TEGRA194_CLK_NVDISPLAY_DISP             85
92 #define TEGRA194_CLK_NVDISPLAY_P0               86
93 #define TEGRA194_CLK_NVDISPLAY_P1               87
94 #define TEGRA194_CLK_NVDISPLAY_P2               88
95 #define TEGRA194_CLK_NVENC                      89
96 #define TEGRA194_CLK_NVJPG                      90
97 #define TEGRA194_CLK_OSC                        91
98 #define TEGRA194_CLK_AON_TOUCH                  92
99 #define TEGRA194_CLK_PLLA                       93
100 #define TEGRA194_CLK_PLLAON                     94
101 #define TEGRA194_CLK_PLLD                       95
102 #define TEGRA194_CLK_PLLD2                      96
103 #define TEGRA194_CLK_PLLD3                      97
104 #define TEGRA194_CLK_PLLDP                      98
105 #define TEGRA194_CLK_PLLD4                      99
106 #define TEGRA194_CLK_PLLE                       100
107 #define TEGRA194_CLK_PLLP                       101
108 #define TEGRA194_CLK_PLLP_OUT0                  102
109 #define TEGRA194_CLK_UTMIPLL                    103
110 #define TEGRA194_CLK_PLLA_OUT0                  104
111 #define TEGRA194_CLK_PWM1                       105
112 #define TEGRA194_CLK_PWM2                       106
113 #define TEGRA194_CLK_PWM3                       107
114 #define TEGRA194_CLK_PWM4                       108
115 #define TEGRA194_CLK_PWM5                       109
116 #define TEGRA194_CLK_PWM6                       110
117 #define TEGRA194_CLK_PWM7                       111
118 #define TEGRA194_CLK_PWM8                       112
119 #define TEGRA194_CLK_RCE_CPU_NIC                113
120 #define TEGRA194_CLK_RCE_NIC                    114
121 #define TEGRA194_CLK_SATA                       115
122 #define TEGRA194_CLK_SATA_OOB                   116
123 #define TEGRA194_CLK_AON_I2C_SLOW               117
124 #define TEGRA194_CLK_SCE_CPU_NIC                118
125 #define TEGRA194_CLK_SCE_NIC                    119
126 #define TEGRA194_CLK_SDMMC1                     120
127 #define TEGRA194_CLK_UPHY_PLL3                  121
128 #define TEGRA194_CLK_SDMMC3                     122
129 #define TEGRA194_CLK_SDMMC4                     123
130 #define TEGRA194_CLK_SE                         124
131 #define TEGRA194_CLK_SOR0_OUT                   125
132 #define TEGRA194_CLK_SOR0_REF                   126
133 #define TEGRA194_CLK_SOR0_PAD_CLKOUT            127
134 #define TEGRA194_CLK_SOR1_OUT                   128
135 #define TEGRA194_CLK_SOR1_REF                   129
136 #define TEGRA194_CLK_SOR1_PAD_CLKOUT            130
137 #define TEGRA194_CLK_SOR_SAFE                   131
138 #define TEGRA194_CLK_IQC1_IN                    132
139 #define TEGRA194_CLK_IQC2_IN                    133
140 #define TEGRA194_CLK_DMIC5                      134
141 #define TEGRA194_CLK_SPI1                       135
142 #define TEGRA194_CLK_SPI2                       136
143 #define TEGRA194_CLK_SPI3                       137
144 #define TEGRA194_CLK_I2C_SLOW                   138
145 #define TEGRA194_CLK_SYNC_DMIC1                 139
146 #define TEGRA194_CLK_SYNC_DMIC2                 140
147 #define TEGRA194_CLK_SYNC_DMIC3                 141
148 #define TEGRA194_CLK_SYNC_DMIC4                 142
149 #define TEGRA194_CLK_SYNC_DSPK1                 143
150 #define TEGRA194_CLK_SYNC_DSPK2                 144
151 #define TEGRA194_CLK_SYNC_I2S1                  145
152 #define TEGRA194_CLK_SYNC_I2S2                  146
153 #define TEGRA194_CLK_SYNC_I2S3                  147
154 #define TEGRA194_CLK_SYNC_I2S4                  148
155 #define TEGRA194_CLK_SYNC_I2S5                  149
156 #define TEGRA194_CLK_SYNC_I2S6                  150
157 #define TEGRA194_CLK_MPHY_FORCE_LS_MODE         151
158 #define TEGRA194_CLK_TACH                       152
159 #define TEGRA194_CLK_TSEC                       153
160 #define TEGRA194_CLK_TSECB                      154
161 #define TEGRA194_CLK_UARTA                      155
162 #define TEGRA194_CLK_UARTB                      156
163 #define TEGRA194_CLK_UARTC                      157
164 #define TEGRA194_CLK_UARTD                      158
165 #define TEGRA194_CLK_UARTE                      159
166 #define TEGRA194_CLK_UARTF                      160
167 #define TEGRA194_CLK_UARTG                      161
168 #define TEGRA194_CLK_UART_FST_MIPI_CAL          162
169 #define TEGRA194_CLK_UFSDEV_REF                 163
170 #define TEGRA194_CLK_UFSHC                      164
171 #define TEGRA194_CLK_USB2_TRK                   165
172 #define TEGRA194_CLK_VI                         166
173 #define TEGRA194_CLK_VIC                        167
174 #define TEGRA194_CLK_PVA0_AXI                   168
175 #define TEGRA194_CLK_PVA0_VPS0                  169
176 #define TEGRA194_CLK_PVA0_VPS1                  170
177 #define TEGRA194_CLK_PVA1_AXI                   171
178 #define TEGRA194_CLK_PVA1_VPS0                  172
179 #define TEGRA194_CLK_PVA1_VPS1                  173
180 #define TEGRA194_CLK_DLA0_FALCON                174
181 #define TEGRA194_CLK_DLA0_CORE                  175
182 #define TEGRA194_CLK_DLA1_FALCON                176
183 #define TEGRA194_CLK_DLA1_CORE                  177
184 #define TEGRA194_CLK_SOR2_OUT                   178
185 #define TEGRA194_CLK_SOR2_REF                   179
186 #define TEGRA194_CLK_SOR2_PAD_CLKOUT            180
187 #define TEGRA194_CLK_SOR3_OUT                   181
188 #define TEGRA194_CLK_SOR3_REF                   182
189 #define TEGRA194_CLK_SOR3_PAD_CLKOUT            183
190 #define TEGRA194_CLK_NVDISPLAY_P3               184
191 #define TEGRA194_CLK_DPAUX2                     185
192 #define TEGRA194_CLK_DPAUX3                     186
193 #define TEGRA194_CLK_NVDEC1                     187
194 #define TEGRA194_CLK_NVENC1                     188
195 #define TEGRA194_CLK_SE_FREE                    189
196 #define TEGRA194_CLK_UARTH                      190
197 #define TEGRA194_CLK_FUSE_SERIAL                191
198 #define TEGRA194_CLK_QSPI0                      192
199 #define TEGRA194_CLK_QSPI1                      193
200 #define TEGRA194_CLK_QSPI0_PM                   194
201 #define TEGRA194_CLK_QSPI1_PM                   195
202 #define TEGRA194_CLK_VI_CONST                   196
203 #define TEGRA194_CLK_NAFLL_BPMP                 197
204 #define TEGRA194_CLK_NAFLL_SCE                  198
205 #define TEGRA194_CLK_NAFLL_NVDEC                199
206 #define TEGRA194_CLK_NAFLL_NVJPG                200
207 #define TEGRA194_CLK_NAFLL_TSEC                 201
208 #define TEGRA194_CLK_NAFLL_TSECB                202
209 #define TEGRA194_CLK_NAFLL_VI                   203
210 #define TEGRA194_CLK_NAFLL_SE                   204
211 #define TEGRA194_CLK_NAFLL_NVENC                205
212 #define TEGRA194_CLK_NAFLL_ISP                  206
213 #define TEGRA194_CLK_NAFLL_VIC                  207
214 #define TEGRA194_CLK_NAFLL_NVDISPLAYHUB         208
215 #define TEGRA194_CLK_NAFLL_AXICBB               209
216 #define TEGRA194_CLK_NAFLL_DLA                  210
217 #define TEGRA194_CLK_NAFLL_PVA_CORE             211
218 #define TEGRA194_CLK_NAFLL_PVA_VPS              212
219 #define TEGRA194_CLK_NAFLL_CVNAS                213
220 #define TEGRA194_CLK_NAFLL_RCE                  214
221 #define TEGRA194_CLK_NAFLL_NVENC1               215
222 #define TEGRA194_CLK_NAFLL_DLA_FALCON           216
223 #define TEGRA194_CLK_NAFLL_NVDEC1               217
224 #define TEGRA194_CLK_NAFLL_GPU                  218
225 #define TEGRA194_CLK_SDMMC_LEGACY_TM            219
226 #define TEGRA194_CLK_PEX0_CORE_0                220
227 #define TEGRA194_CLK_PEX0_CORE_1                221
228 #define TEGRA194_CLK_PEX0_CORE_2                222
229 #define TEGRA194_CLK_PEX0_CORE_3                223
230 #define TEGRA194_CLK_PEX0_CORE_4                224
231 #define TEGRA194_CLK_PEX1_CORE_5                225
232 #define TEGRA194_CLK_PEX_REF1                   226
233 #define TEGRA194_CLK_PEX_REF2                   227
234 #define TEGRA194_CLK_CSI_A                      229
235 #define TEGRA194_CLK_CSI_B                      230
236 #define TEGRA194_CLK_CSI_C                      231
237 #define TEGRA194_CLK_CSI_D                      232
238 #define TEGRA194_CLK_CSI_E                      233
239 #define TEGRA194_CLK_CSI_F                      234
240 #define TEGRA194_CLK_CSI_G                      235
241 #define TEGRA194_CLK_CSI_H                      236
242 #define TEGRA194_CLK_PLLC4                      237
243 #define TEGRA194_CLK_PLLC4_OUT                  238
244 #define TEGRA194_CLK_PLLC4_OUT1                 239
245 #define TEGRA194_CLK_PLLC4_OUT2                 240
246 #define TEGRA194_CLK_PLLC4_MUXED                241
247 #define TEGRA194_CLK_PLLC4_VCO_DIV2             242
248 #define TEGRA194_CLK_CSI_A_PAD                  244
249 #define TEGRA194_CLK_CSI_B_PAD                  245
250 #define TEGRA194_CLK_CSI_C_PAD                  246
251 #define TEGRA194_CLK_CSI_D_PAD                  247
252 #define TEGRA194_CLK_CSI_E_PAD                  248
253 #define TEGRA194_CLK_CSI_F_PAD                  249
254 #define TEGRA194_CLK_CSI_G_PAD                  250
255 #define TEGRA194_CLK_CSI_H_PAD                  251
256 #define TEGRA194_CLK_PEX_SATA_USB_RX_BYP        254
257 #define TEGRA194_CLK_PEX_USB_PAD_PLL0_MGMT      255
258 #define TEGRA194_CLK_PEX_USB_PAD_PLL1_MGMT      256
259 #define TEGRA194_CLK_PEX_USB_PAD_PLL2_MGMT      257
260 #define TEGRA194_CLK_PEX_USB_PAD_PLL3_MGMT      258
261 #define TEGRA194_CLK_XUSB_CORE_DEV              265
262 #define TEGRA194_CLK_XUSB_CORE_MUX              266
263 #define TEGRA194_CLK_XUSB_CORE_HOST             267
264 #define TEGRA194_CLK_XUSB_CORE_SS               268
265 #define TEGRA194_CLK_XUSB_FALCON                269
266 #define TEGRA194_CLK_XUSB_FALCON_HOST           270
267 #define TEGRA194_CLK_XUSB_FALCON_SS             271
268 #define TEGRA194_CLK_XUSB_FS                    272
269 #define TEGRA194_CLK_XUSB_FS_HOST               273
270 #define TEGRA194_CLK_XUSB_FS_DEV                274
271 #define TEGRA194_CLK_XUSB_SS                    275
272 #define TEGRA194_CLK_XUSB_SS_DEV                276
273 #define TEGRA194_CLK_XUSB_SS_SUPERSPEED         277
274 #define TEGRA194_CLK_PLLDISPHUB                 278
275 #define TEGRA194_CLK_PLLDISPHUB_DIV             279
276 #define TEGRA194_CLK_NAFLL_CLUSTER0             280
277 #define TEGRA194_CLK_NAFLL_CLUSTER1             281
278 #define TEGRA194_CLK_NAFLL_CLUSTER2             282
279 #define TEGRA194_CLK_NAFLL_CLUSTER3             283
280 #define TEGRA194_CLK_CAN1_CORE                  284
281 #define TEGRA194_CLK_CAN2_CORE                  285
282 #define TEGRA194_CLK_PLLA1_OUT1                 286
283 #define TEGRA194_CLK_PLLREFE_VCOOUT             288
284 #define TEGRA194_CLK_CLK_32K                    289
285 #define TEGRA194_CLK_SPDIFIN_SYNC_INPUT         290
286 #define TEGRA194_CLK_UTMIPLL_CLKOUT48           291
287 #define TEGRA194_CLK_UTMIPLL_CLKOUT480          292
288 #define TEGRA194_CLK_CVNAS                      293
289 #define TEGRA194_CLK_PLLNVCSI                   294
290 #define TEGRA194_CLK_PVA0_CPU_AXI               295
291 #define TEGRA194_CLK_PVA1_CPU_AXI               296
292 #define TEGRA194_CLK_PVA0_VPS                   297
293 #define TEGRA194_CLK_PVA1_VPS                   298
294 #define TEGRA194_CLK_DLA0_FALCON_MUX            299
295 #define TEGRA194_CLK_DLA1_FALCON_MUX            300
296 #define TEGRA194_CLK_DLA0_CORE_MUX              301
297 #define TEGRA194_CLK_DLA1_CORE_MUX              302
298 #define TEGRA194_CLK_UTMIPLL_HPS                304
299 #define TEGRA194_CLK_I2C5                       305
300 #define TEGRA194_CLK_I2C10                      306
301 #define TEGRA194_CLK_BPMP_CPU_NIC               307
302 #define TEGRA194_CLK_BPMP_APB                   308
303 #define TEGRA194_CLK_TSC                        309
304 #define TEGRA194_CLK_EMCSA                      310
305 #define TEGRA194_CLK_EMCSB                      311
306 #define TEGRA194_CLK_EMCSC                      312
307 #define TEGRA194_CLK_EMCSD                      313
308 #define TEGRA194_CLK_PLLC                       314
309 #define TEGRA194_CLK_PLLC2                      315
310 #define TEGRA194_CLK_PLLC3                      316
311 #define TEGRA194_CLK_TSC_REF                    317
312 #define TEGRA194_CLK_FUSE_BURN                  318
313 #define TEGRA194_CLK_PEX0_CORE_0M               319
314 #define TEGRA194_CLK_PEX0_CORE_1M               320
315 #define TEGRA194_CLK_PEX0_CORE_2M               321
316 #define TEGRA194_CLK_PEX0_CORE_3M               322
317 #define TEGRA194_CLK_PEX0_CORE_4M               323
318 #define TEGRA194_CLK_PEX1_CORE_5M               324
319 #define TEGRA194_CLK_PLLE_HPS                   326
320
321 #endif