include/dt-bindings/clock/r8a77990-cpg-mssr.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2018 Renesas Electronics Corp.
   4  */
   5 #ifndef __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
   6 #define __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__
   7
   8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
   9
  10 /* r8a77990 CPG Core Clocks */
  11 #define R8A77990_CLK_Z2                 0
  12 #define R8A77990_CLK_ZR                 1
  13 #define R8A77990_CLK_ZG                 2
  14 #define R8A77990_CLK_ZTR                3
  15 #define R8A77990_CLK_ZT                 4
  16 #define R8A77990_CLK_ZX                 5
  17 #define R8A77990_CLK_S0D1               6
  18 #define R8A77990_CLK_S0D3               7
  19 #define R8A77990_CLK_S0D6               8
  20 #define R8A77990_CLK_S0D12              9
  21 #define R8A77990_CLK_S0D24              10
  22 #define R8A77990_CLK_S1D1               11
  23 #define R8A77990_CLK_S1D2               12
  24 #define R8A77990_CLK_S1D4               13
  25 #define R8A77990_CLK_S2D1               14
  26 #define R8A77990_CLK_S2D2               15
  27 #define R8A77990_CLK_S2D4               16
  28 #define R8A77990_CLK_S3D1               17
  29 #define R8A77990_CLK_S3D2               18
  30 #define R8A77990_CLK_S3D4               19
  31 #define R8A77990_CLK_S0D6C              20
  32 #define R8A77990_CLK_S3D1C              21
  33 #define R8A77990_CLK_S3D2C              22
  34 #define R8A77990_CLK_S3D4C              23
  35 #define R8A77990_CLK_LB                 24
  36 #define R8A77990_CLK_CL                 25
  37 #define R8A77990_CLK_ZB3                26
  38 #define R8A77990_CLK_ZB3D2              27
  39 #define R8A77990_CLK_CR                 28
  40 #define R8A77990_CLK_CRD2               29
  41 #define R8A77990_CLK_SD0H               30
  42 #define R8A77990_CLK_SD0                31
  43 #define R8A77990_CLK_SD1H               32
  44 #define R8A77990_CLK_SD1                33
  45 #define R8A77990_CLK_SD3H               34
  46 #define R8A77990_CLK_SD3                35
  47 #define R8A77990_CLK_RPC                36
  48 #define R8A77990_CLK_RPCD2              37
  49 #define R8A77990_CLK_ZA2                38
  50 #define R8A77990_CLK_ZA8                39
  51 #define R8A77990_CLK_Z2D                40
  52 #define R8A77990_CLK_CANFD              41
  53 #define R8A77990_CLK_MSO                42
  54 #define R8A77990_CLK_R                  43
  55 #define R8A77990_CLK_OSC                44
  56 #define R8A77990_CLK_LV0                45
  57 #define R8A77990_CLK_LV1                46
  58 #define R8A77990_CLK_CSI0               47
  59 #define R8A77990_CLK_CP                 48
  60 #define R8A77990_CLK_CPEX               49
  61
  62 #endif /* __DT_BINDINGS_CLOCK_R8A77990_CPG_MSSR_H__ */