GNU Linux-libre 6.9.1-gnu
[releases.git] / include / dt-bindings / clock / r8a7792-clock.h
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright (C) 2016 Cogent Embedded, Inc.
4  */
5
6 #ifndef __DT_BINDINGS_CLOCK_R8A7792_H__
7 #define __DT_BINDINGS_CLOCK_R8A7792_H__
8
9 /* CPG */
10 #define R8A7792_CLK_MAIN                0
11 #define R8A7792_CLK_PLL0                1
12 #define R8A7792_CLK_PLL1                2
13 #define R8A7792_CLK_PLL3                3
14 #define R8A7792_CLK_LB                  4
15 #define R8A7792_CLK_QSPI                5
16
17 /* MSTP0 */
18 #define R8A7792_CLK_MSIOF0              0
19
20 /* MSTP1 */
21 #define R8A7792_CLK_JPU                 6
22 #define R8A7792_CLK_TMU1                11
23 #define R8A7792_CLK_TMU3                21
24 #define R8A7792_CLK_TMU2                22
25 #define R8A7792_CLK_CMT0                24
26 #define R8A7792_CLK_TMU0                25
27 #define R8A7792_CLK_VSP1DU1             27
28 #define R8A7792_CLK_VSP1DU0             28
29 #define R8A7792_CLK_VSP1_SY             31
30
31 /* MSTP2 */
32 #define R8A7792_CLK_MSIOF1              8
33 #define R8A7792_CLK_SYS_DMAC1           18
34 #define R8A7792_CLK_SYS_DMAC0           19
35
36 /* MSTP3 */
37 #define R8A7792_CLK_TPU0                4
38 #define R8A7792_CLK_SDHI0               14
39 #define R8A7792_CLK_CMT1                29
40
41 /* MSTP4 */
42 #define R8A7792_CLK_IRQC                7
43 #define R8A7792_CLK_INTC_SYS            8
44
45 /* MSTP5 */
46 #define R8A7792_CLK_AUDIO_DMAC0         2
47 #define R8A7792_CLK_THERMAL             22
48 #define R8A7792_CLK_PWM                 23
49
50 /* MSTP7 */
51 #define R8A7792_CLK_HSCIF1              16
52 #define R8A7792_CLK_HSCIF0              17
53 #define R8A7792_CLK_SCIF3               18
54 #define R8A7792_CLK_SCIF2               19
55 #define R8A7792_CLK_SCIF1               20
56 #define R8A7792_CLK_SCIF0               21
57 #define R8A7792_CLK_DU1                 23
58 #define R8A7792_CLK_DU0                 24
59
60 /* MSTP8 */
61 #define R8A7792_CLK_VIN5                4
62 #define R8A7792_CLK_VIN4                5
63 #define R8A7792_CLK_VIN3                8
64 #define R8A7792_CLK_VIN2                9
65 #define R8A7792_CLK_VIN1                10
66 #define R8A7792_CLK_VIN0                11
67 #define R8A7792_CLK_ETHERAVB            12
68
69 /* MSTP9 */
70 #define R8A7792_CLK_GPIO7               4
71 #define R8A7792_CLK_GPIO6               5
72 #define R8A7792_CLK_GPIO5               7
73 #define R8A7792_CLK_GPIO4               8
74 #define R8A7792_CLK_GPIO3               9
75 #define R8A7792_CLK_GPIO2               10
76 #define R8A7792_CLK_GPIO1               11
77 #define R8A7792_CLK_GPIO0               12
78 #define R8A7792_CLK_GPIO11              13
79 #define R8A7792_CLK_GPIO10              14
80 #define R8A7792_CLK_CAN1                15
81 #define R8A7792_CLK_CAN0                16
82 #define R8A7792_CLK_QSPI_MOD            17
83 #define R8A7792_CLK_GPIO9               19
84 #define R8A7792_CLK_GPIO8               21
85 #define R8A7792_CLK_I2C5                25
86 #define R8A7792_CLK_IICDVFS             26
87 #define R8A7792_CLK_I2C4                27
88 #define R8A7792_CLK_I2C3                28
89 #define R8A7792_CLK_I2C2                29
90 #define R8A7792_CLK_I2C1                30
91 #define R8A7792_CLK_I2C0                31
92
93 /* MSTP10 */
94 #define R8A7792_CLK_SSI_ALL             5
95 #define R8A7792_CLK_SSI4                11
96 #define R8A7792_CLK_SSI3                12
97
98 #endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */