include/dt-bindings/clock/qcom,sm8550-gcc.h

   1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
   2 /*
   3  * Copyright (c) 2022, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2022, Linaro Limited
   5  */
   6
   7 #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8550_H
   8 #define _DT_BINDINGS_CLK_QCOM_GCC_SM8550_H
   9
  10 /* GCC clocks */
  11 #define GCC_AGGRE_NOC_PCIE_AXI_CLK                              0
  12 #define GCC_AGGRE_UFS_PHY_AXI_CLK                               1
  13 #define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK                        2
  14 #define GCC_AGGRE_USB3_PRIM_AXI_CLK                             3
  15 #define GCC_AHB2PHY_0_CLK                                       4
  16 #define GCC_BOOT_ROM_AHB_CLK                                    5
  17 #define GCC_CAMERA_AHB_CLK                                      6
  18 #define GCC_CAMERA_HF_AXI_CLK                                   7
  19 #define GCC_CAMERA_SF_AXI_CLK                                   8
  20 #define GCC_CAMERA_XO_CLK                                       9
  21 #define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK                           10
  22 #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK                           11
  23 #define GCC_CNOC_PCIE_SF_AXI_CLK                                12
  24 #define GCC_DDRSS_GPU_AXI_CLK                                   13
  25 #define GCC_DDRSS_PCIE_SF_QTB_CLK                               14
  26 #define GCC_DISP_AHB_CLK                                        15
  27 #define GCC_DISP_HF_AXI_CLK                                     16
  28 #define GCC_DISP_XO_CLK                                         17
  29 #define GCC_GP1_CLK                                             18
  30 #define GCC_GP1_CLK_SRC                                         19
  31 #define GCC_GP2_CLK                                             20
  32 #define GCC_GP2_CLK_SRC                                         21
  33 #define GCC_GP3_CLK                                             22
  34 #define GCC_GP3_CLK_SRC                                         23
  35 #define GCC_GPLL0                                               24
  36 #define GCC_GPLL0_OUT_EVEN                                      25
  37 #define GCC_GPLL4                                               26
  38 #define GCC_GPLL7                                               27
  39 #define GCC_GPLL9                                               28
  40 #define GCC_GPU_CFG_AHB_CLK                                     29
  41 #define GCC_GPU_GPLL0_CLK_SRC                                   30
  42 #define GCC_GPU_GPLL0_DIV_CLK_SRC                               31
  43 #define GCC_GPU_MEMNOC_GFX_CLK                                  32
  44 #define GCC_GPU_SNOC_DVM_GFX_CLK                                33
  45 #define GCC_PCIE_0_AUX_CLK                                      34
  46 #define GCC_PCIE_0_AUX_CLK_SRC                                  35
  47 #define GCC_PCIE_0_CFG_AHB_CLK                                  36
  48 #define GCC_PCIE_0_MSTR_AXI_CLK                                 37
  49 #define GCC_PCIE_0_PHY_RCHNG_CLK                                38
  50 #define GCC_PCIE_0_PHY_RCHNG_CLK_SRC                            39
  51 #define GCC_PCIE_0_PIPE_CLK                                     40
  52 #define GCC_PCIE_0_PIPE_CLK_SRC                                 41
  53 #define GCC_PCIE_0_SLV_AXI_CLK                                  42
  54 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK                              43
  55 #define GCC_PCIE_1_AUX_CLK                                      44
  56 #define GCC_PCIE_1_AUX_CLK_SRC                                  45
  57 #define GCC_PCIE_1_CFG_AHB_CLK                                  46
  58 #define GCC_PCIE_1_MSTR_AXI_CLK                                 47
  59 #define GCC_PCIE_1_PHY_AUX_CLK                                  48
  60 #define GCC_PCIE_1_PHY_AUX_CLK_SRC                              49
  61 #define GCC_PCIE_1_PHY_RCHNG_CLK                                50
  62 #define GCC_PCIE_1_PHY_RCHNG_CLK_SRC                            51
  63 #define GCC_PCIE_1_PIPE_CLK                                     52
  64 #define GCC_PCIE_1_PIPE_CLK_SRC                                 53
  65 #define GCC_PCIE_1_SLV_AXI_CLK                                  54
  66 #define GCC_PCIE_1_SLV_Q2A_AXI_CLK                              55
  67 #define GCC_PDM2_CLK                                            56
  68 #define GCC_PDM2_CLK_SRC                                        57
  69 #define GCC_PDM_AHB_CLK                                         58
  70 #define GCC_PDM_XO4_CLK                                         59
  71 #define GCC_QMIP_CAMERA_NRT_AHB_CLK                             60
  72 #define GCC_QMIP_CAMERA_RT_AHB_CLK                              61
  73 #define GCC_QMIP_DISP_AHB_CLK                                   62
  74 #define GCC_QMIP_GPU_AHB_CLK                                    63
  75 #define GCC_QMIP_PCIE_AHB_CLK                                   64
  76 #define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK                           65
  77 #define GCC_QMIP_VIDEO_CVP_AHB_CLK                              66
  78 #define GCC_QMIP_VIDEO_V_CPU_AHB_CLK                            67
  79 #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK                           68
  80 #define GCC_QUPV3_I2C_CORE_CLK                                  69
  81 #define GCC_QUPV3_I2C_S0_CLK                                    70
  82 #define GCC_QUPV3_I2C_S0_CLK_SRC                                71
  83 #define GCC_QUPV3_I2C_S1_CLK                                    72
  84 #define GCC_QUPV3_I2C_S1_CLK_SRC                                73
  85 #define GCC_QUPV3_I2C_S2_CLK                                    74
  86 #define GCC_QUPV3_I2C_S2_CLK_SRC                                75
  87 #define GCC_QUPV3_I2C_S3_CLK                                    76
  88 #define GCC_QUPV3_I2C_S3_CLK_SRC                                77
  89 #define GCC_QUPV3_I2C_S4_CLK                                    78
  90 #define GCC_QUPV3_I2C_S4_CLK_SRC                                79
  91 #define GCC_QUPV3_I2C_S5_CLK                                    80
  92 #define GCC_QUPV3_I2C_S5_CLK_SRC                                81
  93 #define GCC_QUPV3_I2C_S6_CLK                                    82
  94 #define GCC_QUPV3_I2C_S6_CLK_SRC                                83
  95 #define GCC_QUPV3_I2C_S7_CLK                                    84
  96 #define GCC_QUPV3_I2C_S7_CLK_SRC                                85
  97 #define GCC_QUPV3_I2C_S8_CLK                                    86
  98 #define GCC_QUPV3_I2C_S8_CLK_SRC                                87
  99 #define GCC_QUPV3_I2C_S9_CLK                                    88
 100 #define GCC_QUPV3_I2C_S9_CLK_SRC                                89
 101 #define GCC_QUPV3_I2C_S_AHB_CLK                                 90
 102 #define GCC_QUPV3_WRAP1_CORE_2X_CLK                             91
 103 #define GCC_QUPV3_WRAP1_CORE_CLK                                92
 104 #define GCC_QUPV3_WRAP1_S0_CLK                                  93
 105 #define GCC_QUPV3_WRAP1_S0_CLK_SRC                              94
 106 #define GCC_QUPV3_WRAP1_S1_CLK                                  95
 107 #define GCC_QUPV3_WRAP1_S1_CLK_SRC                              96
 108 #define GCC_QUPV3_WRAP1_S2_CLK                                  97
 109 #define GCC_QUPV3_WRAP1_S2_CLK_SRC                              98
 110 #define GCC_QUPV3_WRAP1_S3_CLK                                  99
 111 #define GCC_QUPV3_WRAP1_S3_CLK_SRC                              100
 112 #define GCC_QUPV3_WRAP1_S4_CLK                                  101
 113 #define GCC_QUPV3_WRAP1_S4_CLK_SRC                              102
 114 #define GCC_QUPV3_WRAP1_S5_CLK                                  103
 115 #define GCC_QUPV3_WRAP1_S5_CLK_SRC                              104
 116 #define GCC_QUPV3_WRAP1_S6_CLK                                  105
 117 #define GCC_QUPV3_WRAP1_S6_CLK_SRC                              106
 118 #define GCC_QUPV3_WRAP1_S7_CLK                                  107
 119 #define GCC_QUPV3_WRAP1_S7_CLK_SRC                              108
 120 #define GCC_QUPV3_WRAP2_CORE_2X_CLK                             109
 121 #define GCC_QUPV3_WRAP2_CORE_CLK                                110
 122 #define GCC_QUPV3_WRAP2_S0_CLK                                  111
 123 #define GCC_QUPV3_WRAP2_S0_CLK_SRC                              112
 124 #define GCC_QUPV3_WRAP2_S1_CLK                                  113
 125 #define GCC_QUPV3_WRAP2_S1_CLK_SRC                              114
 126 #define GCC_QUPV3_WRAP2_S2_CLK                                  115
 127 #define GCC_QUPV3_WRAP2_S2_CLK_SRC                              116
 128 #define GCC_QUPV3_WRAP2_S3_CLK                                  117
 129 #define GCC_QUPV3_WRAP2_S3_CLK_SRC                              118
 130 #define GCC_QUPV3_WRAP2_S4_CLK                                  119
 131 #define GCC_QUPV3_WRAP2_S4_CLK_SRC                              120
 132 #define GCC_QUPV3_WRAP2_S5_CLK                                  121
 133 #define GCC_QUPV3_WRAP2_S5_CLK_SRC                              122
 134 #define GCC_QUPV3_WRAP2_S6_CLK                                  123
 135 #define GCC_QUPV3_WRAP2_S6_CLK_SRC                              124
 136 #define GCC_QUPV3_WRAP2_S7_CLK                                  125
 137 #define GCC_QUPV3_WRAP2_S7_CLK_SRC                              126
 138 #define GCC_QUPV3_WRAP_1_M_AHB_CLK                              127
 139 #define GCC_QUPV3_WRAP_1_S_AHB_CLK                              128
 140 #define GCC_QUPV3_WRAP_2_M_AHB_CLK                              129
 141 #define GCC_QUPV3_WRAP_2_S_AHB_CLK                              130
 142 #define GCC_SDCC2_AHB_CLK                                       131
 143 #define GCC_SDCC2_APPS_CLK                                      132
 144 #define GCC_SDCC2_APPS_CLK_SRC                                  133
 145 #define GCC_SDCC4_AHB_CLK                                       134
 146 #define GCC_SDCC4_APPS_CLK                                      135
 147 #define GCC_SDCC4_APPS_CLK_SRC                                  136
 148 #define GCC_UFS_PHY_AHB_CLK                                     137
 149 #define GCC_UFS_PHY_AXI_CLK                                     138
 150 #define GCC_UFS_PHY_AXI_CLK_SRC                                 139
 151 #define GCC_UFS_PHY_AXI_HW_CTL_CLK                              140
 152 #define GCC_UFS_PHY_ICE_CORE_CLK                                141
 153 #define GCC_UFS_PHY_ICE_CORE_CLK_SRC                            142
 154 #define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK                         143
 155 #define GCC_UFS_PHY_PHY_AUX_CLK                                 144
 156 #define GCC_UFS_PHY_PHY_AUX_CLK_SRC                             145
 157 #define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK                          146
 158 #define GCC_UFS_PHY_RX_SYMBOL_0_CLK                             147
 159 #define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC                         148
 160 #define GCC_UFS_PHY_RX_SYMBOL_1_CLK                             149
 161 #define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC                         150
 162 #define GCC_UFS_PHY_TX_SYMBOL_0_CLK                             151
 163 #define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC                         152
 164 #define GCC_UFS_PHY_UNIPRO_CORE_CLK                             153
 165 #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC                         154
 166 #define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK                      155
 167 #define GCC_USB30_PRIM_MASTER_CLK                               156
 168 #define GCC_USB30_PRIM_MASTER_CLK_SRC                           157
 169 #define GCC_USB30_PRIM_MOCK_UTMI_CLK                            158
 170 #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC                        159
 171 #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC                160
 172 #define GCC_USB30_PRIM_SLEEP_CLK                                161
 173 #define GCC_USB3_PRIM_PHY_AUX_CLK                               162
 174 #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC                           163
 175 #define GCC_USB3_PRIM_PHY_COM_AUX_CLK                           164
 176 #define GCC_USB3_PRIM_PHY_PIPE_CLK                              165
 177 #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC                          166
 178 #define GCC_VIDEO_AHB_CLK                                       167
 179 #define GCC_VIDEO_AXI0_CLK                                      168
 180 #define GCC_VIDEO_AXI1_CLK                                      169
 181 #define GCC_VIDEO_XO_CLK                                        170
 182
 183 /* GCC resets */
 184 #define GCC_CAMERA_BCR                                          0
 185 #define GCC_DISPLAY_BCR                                         1
 186 #define GCC_GPU_BCR                                             2
 187 #define GCC_PCIE_0_BCR                                          3
 188 #define GCC_PCIE_0_LINK_DOWN_BCR                                4
 189 #define GCC_PCIE_0_NOCSR_COM_PHY_BCR                            5
 190 #define GCC_PCIE_0_PHY_BCR                                      6
 191 #define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR                        7
 192 #define GCC_PCIE_1_BCR                                          8
 193 #define GCC_PCIE_1_LINK_DOWN_BCR                                9
 194 #define GCC_PCIE_1_NOCSR_COM_PHY_BCR                            10
 195 #define GCC_PCIE_1_PHY_BCR                                      11
 196 #define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR                        12
 197 #define GCC_PCIE_PHY_BCR                                        13
 198 #define GCC_PCIE_PHY_CFG_AHB_BCR                                14
 199 #define GCC_PCIE_PHY_COM_BCR                                    15
 200 #define GCC_PDM_BCR                                             16
 201 #define GCC_QUPV3_WRAPPER_1_BCR                                 17
 202 #define GCC_QUPV3_WRAPPER_2_BCR                                 18
 203 #define GCC_QUPV3_WRAPPER_I2C_BCR                               19
 204 #define GCC_QUSB2PHY_PRIM_BCR                                   20
 205 #define GCC_QUSB2PHY_SEC_BCR                                    21
 206 #define GCC_SDCC2_BCR                                           22
 207 #define GCC_SDCC4_BCR                                           23
 208 #define GCC_UFS_PHY_BCR                                         24
 209 #define GCC_USB30_PRIM_BCR                                      25
 210 #define GCC_USB3_DP_PHY_PRIM_BCR                                26
 211 #define GCC_USB3_DP_PHY_SEC_BCR                                 27
 212 #define GCC_USB3_PHY_PRIM_BCR                                   28
 213 #define GCC_USB3_PHY_SEC_BCR                                    29
 214 #define GCC_USB3PHY_PHY_PRIM_BCR                                30
 215 #define GCC_USB3PHY_PHY_SEC_BCR                                 31
 216 #define GCC_USB_PHY_CFG_AHB2PHY_BCR                             32
 217 #define GCC_VIDEO_AXI0_CLK_ARES                                 33
 218 #define GCC_VIDEO_AXI1_CLK_ARES                                 34
 219 #define GCC_VIDEO_BCR                                           35
 220
 221 /* GCC power domains */
 222 #define PCIE_0_GDSC                                             0
 223 #define PCIE_0_PHY_GDSC                                         1
 224 #define PCIE_1_GDSC                                             2
 225 #define PCIE_1_PHY_GDSC                                         3
 226 #define UFS_PHY_GDSC                                            4
 227 #define UFS_MEM_PHY_GDSC                                        5
 228 #define USB30_PRIM_GDSC                                         6
 229 #define USB3_PHY_GDSC                                           7
 230
 231 #endif