include/dt-bindings/clock/qcom,sdx75-gcc.h

   1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
   2 /*
   3  * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
   4  */
   5
   6 #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SDX75_H
   7 #define _DT_BINDINGS_CLK_QCOM_GCC_SDX75_H
   8
   9 /* GCC clocks */
  10 #define GPLL0                                                   0
  11 #define GPLL0_OUT_EVEN                                          1
  12 #define GPLL4                                                   2
  13 #define GPLL5                                                   3
  14 #define GPLL6                                                   4
  15 #define GPLL8                                                   5
  16 #define GCC_AHB_PCIE_LINK_CLK                                   6
  17 #define GCC_BOOT_ROM_AHB_CLK                                    7
  18 #define GCC_EEE_EMAC0_CLK                                       8
  19 #define GCC_EEE_EMAC0_CLK_SRC                                   9
  20 #define GCC_EEE_EMAC1_CLK                                       10
  21 #define GCC_EEE_EMAC1_CLK_SRC                                   11
  22 #define GCC_EMAC0_AXI_CLK                                       12
  23 #define GCC_EMAC0_CC_SGMIIPHY_RX_CLK                            13
  24 #define GCC_EMAC0_CC_SGMIIPHY_RX_CLK_SRC                        14
  25 #define GCC_EMAC0_CC_SGMIIPHY_TX_CLK                            15
  26 #define GCC_EMAC0_CC_SGMIIPHY_TX_CLK_SRC                        16
  27 #define GCC_EMAC0_PHY_AUX_CLK                                   17
  28 #define GCC_EMAC0_PHY_AUX_CLK_SRC                               18
  29 #define GCC_EMAC0_PTP_CLK                                       19
  30 #define GCC_EMAC0_PTP_CLK_SRC                                   20
  31 #define GCC_EMAC0_RGMII_CLK                                     21
  32 #define GCC_EMAC0_RGMII_CLK_SRC                                 22
  33 #define GCC_EMAC0_RPCS_RX_CLK                                   23
  34 #define GCC_EMAC0_RPCS_TX_CLK                                   24
  35 #define GCC_EMAC0_SGMIIPHY_MAC_RCLK_SRC                         25
  36 #define GCC_EMAC0_SGMIIPHY_MAC_TCLK_SRC                         26
  37 #define GCC_EMAC0_SLV_AHB_CLK                                   27
  38 #define GCC_EMAC0_XGXS_RX_CLK                                   28
  39 #define GCC_EMAC0_XGXS_TX_CLK                                   29
  40 #define GCC_EMAC1_AXI_CLK                                       30
  41 #define GCC_EMAC1_CC_SGMIIPHY_RX_CLK                            31
  42 #define GCC_EMAC1_CC_SGMIIPHY_RX_CLK_SRC                        32
  43 #define GCC_EMAC1_CC_SGMIIPHY_TX_CLK                            33
  44 #define GCC_EMAC1_CC_SGMIIPHY_TX_CLK_SRC                        34
  45 #define GCC_EMAC1_PHY_AUX_CLK                                   35
  46 #define GCC_EMAC1_PHY_AUX_CLK_SRC                               36
  47 #define GCC_EMAC1_PTP_CLK                                       37
  48 #define GCC_EMAC1_PTP_CLK_SRC                                   38
  49 #define GCC_EMAC1_RGMII_CLK                                     39
  50 #define GCC_EMAC1_RGMII_CLK_SRC                                 40
  51 #define GCC_EMAC1_RPCS_RX_CLK                                   41
  52 #define GCC_EMAC1_RPCS_TX_CLK                                   42
  53 #define GCC_EMAC1_SGMIIPHY_MAC_RCLK_SRC                         43
  54 #define GCC_EMAC1_SGMIIPHY_MAC_TCLK_SRC                         44
  55 #define GCC_EMAC1_SLV_AHB_CLK                                   45
  56 #define GCC_EMAC1_XGXS_RX_CLK                                   46
  57 #define GCC_EMAC1_XGXS_TX_CLK                                   47
  58 #define GCC_EMAC_0_CLKREF_EN                                    48
  59 #define GCC_EMAC_1_CLKREF_EN                                    49
  60 #define GCC_GP1_CLK                                             50
  61 #define GCC_GP1_CLK_SRC                                         51
  62 #define GCC_GP2_CLK                                             52
  63 #define GCC_GP2_CLK_SRC                                         53
  64 #define GCC_GP3_CLK                                             54
  65 #define GCC_GP3_CLK_SRC                                         55
  66 #define GCC_PCIE_0_CLKREF_EN                                    56
  67 #define GCC_PCIE_1_AUX_CLK                                      57
  68 #define GCC_PCIE_1_AUX_PHY_CLK_SRC                              58
  69 #define GCC_PCIE_1_CFG_AHB_CLK                                  59
  70 #define GCC_PCIE_1_CLKREF_EN                                    60
  71 #define GCC_PCIE_1_MSTR_AXI_CLK                                 61
  72 #define GCC_PCIE_1_PHY_RCHNG_CLK                                62
  73 #define GCC_PCIE_1_PHY_RCHNG_CLK_SRC                            63
  74 #define GCC_PCIE_1_PIPE_CLK                                     64
  75 #define GCC_PCIE_1_PIPE_CLK_SRC                                 65
  76 #define GCC_PCIE_1_PIPE_DIV2_CLK                                66
  77 #define GCC_PCIE_1_PIPE_DIV2_CLK_SRC                            67
  78 #define GCC_PCIE_1_SLV_AXI_CLK                                  68
  79 #define GCC_PCIE_1_SLV_Q2A_AXI_CLK                              69
  80 #define GCC_PCIE_2_AUX_CLK                                      70
  81 #define GCC_PCIE_2_AUX_PHY_CLK_SRC                              71
  82 #define GCC_PCIE_2_CFG_AHB_CLK                                  72
  83 #define GCC_PCIE_2_CLKREF_EN                                    73
  84 #define GCC_PCIE_2_MSTR_AXI_CLK                                 74
  85 #define GCC_PCIE_2_PHY_RCHNG_CLK                                75
  86 #define GCC_PCIE_2_PHY_RCHNG_CLK_SRC                            76
  87 #define GCC_PCIE_2_PIPE_CLK                                     77
  88 #define GCC_PCIE_2_PIPE_CLK_SRC                                 78
  89 #define GCC_PCIE_2_PIPE_DIV2_CLK                                79
  90 #define GCC_PCIE_2_PIPE_DIV2_CLK_SRC                            80
  91 #define GCC_PCIE_2_SLV_AXI_CLK                                  81
  92 #define GCC_PCIE_2_SLV_Q2A_AXI_CLK                              82
  93 #define GCC_PCIE_AUX_CLK                                        83
  94 #define GCC_PCIE_AUX_CLK_SRC                                    84
  95 #define GCC_PCIE_AUX_PHY_CLK_SRC                                85
  96 #define GCC_PCIE_CFG_AHB_CLK                                    86
  97 #define GCC_PCIE_MSTR_AXI_CLK                                   87
  98 #define GCC_PCIE_PIPE_CLK                                       88
  99 #define GCC_PCIE_PIPE_CLK_SRC                                   89
 100 #define GCC_PCIE_RCHNG_PHY_CLK                                  90
 101 #define GCC_PCIE_RCHNG_PHY_CLK_SRC                              91
 102 #define GCC_PCIE_SLEEP_CLK                                      92
 103 #define GCC_PCIE_SLV_AXI_CLK                                    93
 104 #define GCC_PCIE_SLV_Q2A_AXI_CLK                                94
 105 #define GCC_PDM2_CLK                                            95
 106 #define GCC_PDM2_CLK_SRC                                        96
 107 #define GCC_PDM_AHB_CLK                                         97
 108 #define GCC_PDM_XO4_CLK                                         98
 109 #define GCC_QUPV3_WRAP0_CORE_2X_CLK                             99
 110 #define GCC_QUPV3_WRAP0_CORE_CLK                                100
 111 #define GCC_QUPV3_WRAP0_S0_CLK                                  101
 112 #define GCC_QUPV3_WRAP0_S0_CLK_SRC                              102
 113 #define GCC_QUPV3_WRAP0_S1_CLK                                  103
 114 #define GCC_QUPV3_WRAP0_S1_CLK_SRC                              104
 115 #define GCC_QUPV3_WRAP0_S2_CLK                                  105
 116 #define GCC_QUPV3_WRAP0_S2_CLK_SRC                              106
 117 #define GCC_QUPV3_WRAP0_S3_CLK                                  107
 118 #define GCC_QUPV3_WRAP0_S3_CLK_SRC                              108
 119 #define GCC_QUPV3_WRAP0_S4_CLK                                  109
 120 #define GCC_QUPV3_WRAP0_S4_CLK_SRC                              110
 121 #define GCC_QUPV3_WRAP0_S5_CLK                                  111
 122 #define GCC_QUPV3_WRAP0_S5_CLK_SRC                              112
 123 #define GCC_QUPV3_WRAP0_S6_CLK                                  113
 124 #define GCC_QUPV3_WRAP0_S6_CLK_SRC                              114
 125 #define GCC_QUPV3_WRAP0_S7_CLK                                  115
 126 #define GCC_QUPV3_WRAP0_S7_CLK_SRC                              116
 127 #define GCC_QUPV3_WRAP0_S8_CLK                                  117
 128 #define GCC_QUPV3_WRAP0_S8_CLK_SRC                              118
 129 #define GCC_QUPV3_WRAP_0_M_AHB_CLK                              119
 130 #define GCC_QUPV3_WRAP_0_S_AHB_CLK                              120
 131 #define GCC_SDCC1_AHB_CLK                                       121
 132 #define GCC_SDCC1_APPS_CLK                                      122
 133 #define GCC_SDCC1_APPS_CLK_SRC                                  123
 134 #define GCC_SDCC2_AHB_CLK                                       124
 135 #define GCC_SDCC2_APPS_CLK                                      125
 136 #define GCC_SDCC2_APPS_CLK_SRC                                  126
 137 #define GCC_USB2_CLKREF_EN                                      127
 138 #define GCC_USB30_MASTER_CLK                                    128
 139 #define GCC_USB30_MASTER_CLK_SRC                                129
 140 #define GCC_USB30_MOCK_UTMI_CLK                                 130
 141 #define GCC_USB30_MOCK_UTMI_CLK_SRC                             131
 142 #define GCC_USB30_MOCK_UTMI_POSTDIV_CLK_SRC                     132
 143 #define GCC_USB30_MSTR_AXI_CLK                                  133
 144 #define GCC_USB30_SLEEP_CLK                                     134
 145 #define GCC_USB30_SLV_AHB_CLK                                   135
 146 #define GCC_USB3_PHY_AUX_CLK                                    136
 147 #define GCC_USB3_PHY_AUX_CLK_SRC                                137
 148 #define GCC_USB3_PHY_PIPE_CLK                                   138
 149 #define GCC_USB3_PHY_PIPE_CLK_SRC                               139
 150 #define GCC_USB3_PRIM_CLKREF_EN                                 140
 151 #define GCC_USB_PHY_CFG_AHB2PHY_CLK                             141
 152 #define GCC_XO_PCIE_LINK_CLK                                    142
 153
 154 /* GCC power domains */
 155 #define GCC_EMAC0_GDSC                                          0
 156 #define GCC_EMAC1_GDSC                                          1
 157 #define GCC_PCIE_1_GDSC                                         2
 158 #define GCC_PCIE_1_PHY_GDSC                                     3
 159 #define GCC_PCIE_2_GDSC                                         4
 160 #define GCC_PCIE_2_PHY_GDSC                                     5
 161 #define GCC_PCIE_GDSC                                           6
 162 #define GCC_PCIE_PHY_GDSC                                       7
 163 #define GCC_USB30_GDSC                                          8
 164 #define GCC_USB3_PHY_GDSC                                       9
 165
 166 /* GCC resets */
 167 #define GCC_EMAC0_BCR                                           0
 168 #define GCC_EMAC1_BCR                                           1
 169 #define GCC_EMMC_BCR                                            2
 170 #define GCC_PCIE_1_BCR                                          3
 171 #define GCC_PCIE_1_LINK_DOWN_BCR                                4
 172 #define GCC_PCIE_1_NOCSR_COM_PHY_BCR                            5
 173 #define GCC_PCIE_1_PHY_BCR                                      6
 174 #define GCC_PCIE_2_BCR                                          7
 175 #define GCC_PCIE_2_LINK_DOWN_BCR                                8
 176 #define GCC_PCIE_2_NOCSR_COM_PHY_BCR                            9
 177 #define GCC_PCIE_2_PHY_BCR                                      10
 178 #define GCC_PCIE_BCR                                            11
 179 #define GCC_PCIE_LINK_DOWN_BCR                                  12
 180 #define GCC_PCIE_NOCSR_COM_PHY_BCR                              13
 181 #define GCC_PCIE_PHY_BCR                                        14
 182 #define GCC_PCIE_PHY_CFG_AHB_BCR                                15
 183 #define GCC_PCIE_PHY_COM_BCR                                    16
 184 #define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR                          17
 185 #define GCC_QUSB2PHY_BCR                                        18
 186 #define GCC_TCSR_PCIE_BCR                                       19
 187 #define GCC_USB30_BCR                                           20
 188 #define GCC_USB3_PHY_BCR                                        21
 189 #define GCC_USB3PHY_PHY_BCR                                     22
 190 #define GCC_USB_PHY_CFG_AHB2PHY_BCR                             23
 191 #define GCC_EMAC0_RGMII_CLK_ARES                                24
 192
 193 #endif