GNU Linux-libre 6.9.1-gnu
[releases.git] / include / dt-bindings / clock / qcom,gcc-sdm845.h
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4  */
5
6 #ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
7 #define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
8
9 /* GCC clock registers */
10 #define GCC_AGGRE_NOC_PCIE_TBU_CLK                              0
11 #define GCC_AGGRE_UFS_CARD_AXI_CLK                              1
12 #define GCC_AGGRE_UFS_PHY_AXI_CLK                               2
13 #define GCC_AGGRE_USB3_PRIM_AXI_CLK                             3
14 #define GCC_AGGRE_USB3_SEC_AXI_CLK                              4
15 #define GCC_BOOT_ROM_AHB_CLK                                    5
16 #define GCC_CAMERA_AHB_CLK                                      6
17 #define GCC_CAMERA_AXI_CLK                                      7
18 #define GCC_CAMERA_XO_CLK                                       8
19 #define GCC_CE1_AHB_CLK                                         9
20 #define GCC_CE1_AXI_CLK                                         10
21 #define GCC_CE1_CLK                                             11
22 #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK                           12
23 #define GCC_CFG_NOC_USB3_SEC_AXI_CLK                            13
24 #define GCC_CPUSS_AHB_CLK                                       14
25 #define GCC_CPUSS_AHB_CLK_SRC                                   15
26 #define GCC_CPUSS_RBCPR_CLK                                     16
27 #define GCC_CPUSS_RBCPR_CLK_SRC                                 17
28 #define GCC_DDRSS_GPU_AXI_CLK                                   18
29 #define GCC_DISP_AHB_CLK                                        19
30 #define GCC_DISP_AXI_CLK                                        20
31 #define GCC_DISP_GPLL0_CLK_SRC                                  21
32 #define GCC_DISP_GPLL0_DIV_CLK_SRC                              22
33 #define GCC_DISP_XO_CLK                                         23
34 #define GCC_GP1_CLK                                             24
35 #define GCC_GP1_CLK_SRC                                         25
36 #define GCC_GP2_CLK                                             26
37 #define GCC_GP2_CLK_SRC                                         27
38 #define GCC_GP3_CLK                                             28
39 #define GCC_GP3_CLK_SRC                                         29
40 #define GCC_GPU_CFG_AHB_CLK                                     30
41 #define GCC_GPU_GPLL0_CLK_SRC                                   31
42 #define GCC_GPU_GPLL0_DIV_CLK_SRC                               32
43 #define GCC_GPU_MEMNOC_GFX_CLK                                  33
44 #define GCC_GPU_SNOC_DVM_GFX_CLK                                34
45 #define GCC_MSS_AXIS2_CLK                                       35
46 #define GCC_MSS_CFG_AHB_CLK                                     36
47 #define GCC_MSS_GPLL0_DIV_CLK_SRC                               37
48 #define GCC_MSS_MFAB_AXIS_CLK                                   38
49 #define GCC_MSS_Q6_MEMNOC_AXI_CLK                               39
50 #define GCC_MSS_SNOC_AXI_CLK                                    40
51 #define GCC_PCIE_0_AUX_CLK                                      41
52 #define GCC_PCIE_0_AUX_CLK_SRC                                  42
53 #define GCC_PCIE_0_CFG_AHB_CLK                                  43
54 #define GCC_PCIE_0_CLKREF_CLK                                   44
55 #define GCC_PCIE_0_MSTR_AXI_CLK                                 45
56 #define GCC_PCIE_0_PIPE_CLK                                     46
57 #define GCC_PCIE_0_SLV_AXI_CLK                                  47
58 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK                              48
59 #define GCC_PCIE_1_AUX_CLK                                      49
60 #define GCC_PCIE_1_AUX_CLK_SRC                                  50
61 #define GCC_PCIE_1_CFG_AHB_CLK                                  51
62 #define GCC_PCIE_1_CLKREF_CLK                                   52
63 #define GCC_PCIE_1_MSTR_AXI_CLK                                 53
64 #define GCC_PCIE_1_PIPE_CLK                                     54
65 #define GCC_PCIE_1_SLV_AXI_CLK                                  55
66 #define GCC_PCIE_1_SLV_Q2A_AXI_CLK                              56
67 #define GCC_PCIE_PHY_AUX_CLK                                    57
68 #define GCC_PCIE_PHY_REFGEN_CLK                                 58
69 #define GCC_PCIE_PHY_REFGEN_CLK_SRC                             59
70 #define GCC_PDM2_CLK                                            60
71 #define GCC_PDM2_CLK_SRC                                        61
72 #define GCC_PDM_AHB_CLK                                         62
73 #define GCC_PDM_XO4_CLK                                         63
74 #define GCC_PRNG_AHB_CLK                                        64
75 #define GCC_QMIP_CAMERA_AHB_CLK                                 65
76 #define GCC_QMIP_DISP_AHB_CLK                                   66
77 #define GCC_QMIP_VIDEO_AHB_CLK                                  67
78 #define GCC_QUPV3_WRAP0_S0_CLK                                  68
79 #define GCC_QUPV3_WRAP0_S0_CLK_SRC                              69
80 #define GCC_QUPV3_WRAP0_S1_CLK                                  70
81 #define GCC_QUPV3_WRAP0_S1_CLK_SRC                              71
82 #define GCC_QUPV3_WRAP0_S2_CLK                                  72
83 #define GCC_QUPV3_WRAP0_S2_CLK_SRC                              73
84 #define GCC_QUPV3_WRAP0_S3_CLK                                  74
85 #define GCC_QUPV3_WRAP0_S3_CLK_SRC                              75
86 #define GCC_QUPV3_WRAP0_S4_CLK                                  76
87 #define GCC_QUPV3_WRAP0_S4_CLK_SRC                              77
88 #define GCC_QUPV3_WRAP0_S5_CLK                                  78
89 #define GCC_QUPV3_WRAP0_S5_CLK_SRC                              79
90 #define GCC_QUPV3_WRAP0_S6_CLK                                  80
91 #define GCC_QUPV3_WRAP0_S6_CLK_SRC                              81
92 #define GCC_QUPV3_WRAP0_S7_CLK                                  82
93 #define GCC_QUPV3_WRAP0_S7_CLK_SRC                              83
94 #define GCC_QUPV3_WRAP1_S0_CLK                                  84
95 #define GCC_QUPV3_WRAP1_S0_CLK_SRC                              85
96 #define GCC_QUPV3_WRAP1_S1_CLK                                  86
97 #define GCC_QUPV3_WRAP1_S1_CLK_SRC                              87
98 #define GCC_QUPV3_WRAP1_S2_CLK                                  88
99 #define GCC_QUPV3_WRAP1_S2_CLK_SRC                              89
100 #define GCC_QUPV3_WRAP1_S3_CLK                                  90
101 #define GCC_QUPV3_WRAP1_S3_CLK_SRC                              91
102 #define GCC_QUPV3_WRAP1_S4_CLK                                  92
103 #define GCC_QUPV3_WRAP1_S4_CLK_SRC                              93
104 #define GCC_QUPV3_WRAP1_S5_CLK                                  94
105 #define GCC_QUPV3_WRAP1_S5_CLK_SRC                              95
106 #define GCC_QUPV3_WRAP1_S6_CLK                                  96
107 #define GCC_QUPV3_WRAP1_S6_CLK_SRC                              97
108 #define GCC_QUPV3_WRAP1_S7_CLK                                  98
109 #define GCC_QUPV3_WRAP1_S7_CLK_SRC                              99
110 #define GCC_QUPV3_WRAP_0_M_AHB_CLK                              100
111 #define GCC_QUPV3_WRAP_0_S_AHB_CLK                              101
112 #define GCC_QUPV3_WRAP_1_M_AHB_CLK                              102
113 #define GCC_QUPV3_WRAP_1_S_AHB_CLK                              103
114 #define GCC_SDCC2_AHB_CLK                                       104
115 #define GCC_SDCC2_APPS_CLK                                      105
116 #define GCC_SDCC2_APPS_CLK_SRC                                  106
117 #define GCC_SDCC4_AHB_CLK                                       107
118 #define GCC_SDCC4_APPS_CLK                                      108
119 #define GCC_SDCC4_APPS_CLK_SRC                                  109
120 #define GCC_SYS_NOC_CPUSS_AHB_CLK                               110
121 #define GCC_TSIF_AHB_CLK                                        111
122 #define GCC_TSIF_INACTIVITY_TIMERS_CLK                          112
123 #define GCC_TSIF_REF_CLK                                        113
124 #define GCC_TSIF_REF_CLK_SRC                                    114
125 #define GCC_UFS_CARD_AHB_CLK                                    115
126 #define GCC_UFS_CARD_AXI_CLK                                    116
127 #define GCC_UFS_CARD_AXI_CLK_SRC                                117
128 #define GCC_UFS_CARD_CLKREF_CLK                                 118
129 #define GCC_UFS_CARD_ICE_CORE_CLK                               119
130 #define GCC_UFS_CARD_ICE_CORE_CLK_SRC                           120
131 #define GCC_UFS_CARD_PHY_AUX_CLK                                121
132 #define GCC_UFS_CARD_PHY_AUX_CLK_SRC                            122
133 #define GCC_UFS_CARD_RX_SYMBOL_0_CLK                            123
134 #define GCC_UFS_CARD_RX_SYMBOL_1_CLK                            124
135 #define GCC_UFS_CARD_TX_SYMBOL_0_CLK                            125
136 #define GCC_UFS_CARD_UNIPRO_CORE_CLK                            126
137 #define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC                        127
138 #define GCC_UFS_MEM_CLKREF_CLK                                  128
139 #define GCC_UFS_PHY_AHB_CLK                                     129
140 #define GCC_UFS_PHY_AXI_CLK                                     130
141 #define GCC_UFS_PHY_AXI_CLK_SRC                                 131
142 #define GCC_UFS_PHY_ICE_CORE_CLK                                132
143 #define GCC_UFS_PHY_ICE_CORE_CLK_SRC                            133
144 #define GCC_UFS_PHY_PHY_AUX_CLK                                 134
145 #define GCC_UFS_PHY_PHY_AUX_CLK_SRC                             135
146 #define GCC_UFS_PHY_RX_SYMBOL_0_CLK                             136
147 #define GCC_UFS_PHY_RX_SYMBOL_1_CLK                             137
148 #define GCC_UFS_PHY_TX_SYMBOL_0_CLK                             138
149 #define GCC_UFS_PHY_UNIPRO_CORE_CLK                             139
150 #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC                         140
151 #define GCC_USB30_PRIM_MASTER_CLK                               141
152 #define GCC_USB30_PRIM_MASTER_CLK_SRC                           142
153 #define GCC_USB30_PRIM_MOCK_UTMI_CLK                            143
154 #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC                        144
155 #define GCC_USB30_PRIM_SLEEP_CLK                                145
156 #define GCC_USB30_SEC_MASTER_CLK                                146
157 #define GCC_USB30_SEC_MASTER_CLK_SRC                            147
158 #define GCC_USB30_SEC_MOCK_UTMI_CLK                             148
159 #define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC                         149
160 #define GCC_USB30_SEC_SLEEP_CLK                                 150
161 #define GCC_USB3_PRIM_CLKREF_CLK                                151
162 #define GCC_USB3_PRIM_PHY_AUX_CLK                               152
163 #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC                           153
164 #define GCC_USB3_PRIM_PHY_COM_AUX_CLK                           154
165 #define GCC_USB3_PRIM_PHY_PIPE_CLK                              155
166 #define GCC_USB3_SEC_CLKREF_CLK                                 156
167 #define GCC_USB3_SEC_PHY_AUX_CLK                                157
168 #define GCC_USB3_SEC_PHY_AUX_CLK_SRC                            158
169 #define GCC_USB3_SEC_PHY_PIPE_CLK                               159
170 #define GCC_USB3_SEC_PHY_COM_AUX_CLK                            160
171 #define GCC_USB_PHY_CFG_AHB2PHY_CLK                             161
172 #define GCC_VIDEO_AHB_CLK                                       162
173 #define GCC_VIDEO_AXI_CLK                                       163
174 #define GCC_VIDEO_XO_CLK                                        164
175 #define GPLL0                                                   165
176 #define GPLL0_OUT_EVEN                                          166
177 #define GPLL0_OUT_MAIN                                          167
178 #define GCC_GPU_IREF_CLK                                        168
179 #define GCC_SDCC1_AHB_CLK                                       169
180 #define GCC_SDCC1_APPS_CLK                                      170
181 #define GCC_SDCC1_ICE_CORE_CLK                                  171
182 #define GCC_SDCC1_APPS_CLK_SRC                                  172
183 #define GCC_SDCC1_ICE_CORE_CLK_SRC                              173
184 #define GCC_APC_VS_CLK                                          174
185 #define GCC_GPU_VS_CLK                                          175
186 #define GCC_MSS_VS_CLK                                          176
187 #define GCC_VDDA_VS_CLK                                         177
188 #define GCC_VDDCX_VS_CLK                                        178
189 #define GCC_VDDMX_VS_CLK                                        179
190 #define GCC_VS_CTRL_AHB_CLK                                     180
191 #define GCC_VS_CTRL_CLK                                         181
192 #define GCC_VS_CTRL_CLK_SRC                                     182
193 #define GCC_VSENSOR_CLK_SRC                                     183
194 #define GPLL4                                                   184
195 #define GCC_CPUSS_DVM_BUS_CLK                                   185
196 #define GCC_CPUSS_GNOC_CLK                                      186
197 #define GCC_QSPI_CORE_CLK_SRC                                   187
198 #define GCC_QSPI_CORE_CLK                                       188
199 #define GCC_QSPI_CNOC_PERIPH_AHB_CLK                            189
200 #define GCC_LPASS_Q6_AXI_CLK                                    190
201 #define GCC_LPASS_SWAY_CLK                                      191
202 #define GPLL6                                                   192
203
204 /* GCC Resets */
205 #define GCC_MMSS_BCR                                            0
206 #define GCC_PCIE_0_BCR                                          1
207 #define GCC_PCIE_1_BCR                                          2
208 #define GCC_PCIE_PHY_BCR                                        3
209 #define GCC_PDM_BCR                                             4
210 #define GCC_PRNG_BCR                                            5
211 #define GCC_QUPV3_WRAPPER_0_BCR                                 6
212 #define GCC_QUPV3_WRAPPER_1_BCR                                 7
213 #define GCC_QUSB2PHY_PRIM_BCR                                   8
214 #define GCC_QUSB2PHY_SEC_BCR                                    9
215 #define GCC_SDCC2_BCR                                           10
216 #define GCC_SDCC4_BCR                                           11
217 #define GCC_TSIF_BCR                                            12
218 #define GCC_UFS_CARD_BCR                                        13
219 #define GCC_UFS_PHY_BCR                                         14
220 #define GCC_USB30_PRIM_BCR                                      15
221 #define GCC_USB30_SEC_BCR                                       16
222 #define GCC_USB3_PHY_PRIM_BCR                                   17
223 #define GCC_USB3PHY_PHY_PRIM_BCR                                18
224 #define GCC_USB3_DP_PHY_PRIM_BCR                                19
225 #define GCC_USB3_PHY_SEC_BCR                                    20
226 #define GCC_USB3PHY_PHY_SEC_BCR                                 21
227 #define GCC_USB3_DP_PHY_SEC_BCR                                 22
228 #define GCC_USB_PHY_CFG_AHB2PHY_BCR                             23
229 #define GCC_PCIE_0_PHY_BCR                                      24
230 #define GCC_PCIE_1_PHY_BCR                                      25
231
232 /* GCC GDSCRs */
233 #define PCIE_0_GDSC                                             0
234 #define PCIE_1_GDSC                                             1
235 #define UFS_CARD_GDSC                                           2
236 #define UFS_PHY_GDSC                                            3
237 #define USB30_PRIM_GDSC                                         4
238 #define USB30_SEC_GDSC                                          5
239 #define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC                 6
240 #define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC                  7
241 #define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC                      8
242 #define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC                      9
243 #define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC                       10
244 #define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC                       11
245 #define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC                        12
246
247 #endif