include/dt-bindings/clock/qcom,gcc-msm8998.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2016, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #ifndef _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
   7 #define _DT_BINDINGS_CLK_MSM_GCC_COBALT_H
   8
   9 #define BLSP1_QUP1_I2C_APPS_CLK_SRC                             0
  10 #define BLSP1_QUP1_SPI_APPS_CLK_SRC                             1
  11 #define BLSP1_QUP2_I2C_APPS_CLK_SRC                             2
  12 #define BLSP1_QUP2_SPI_APPS_CLK_SRC                             3
  13 #define BLSP1_QUP3_I2C_APPS_CLK_SRC                             4
  14 #define BLSP1_QUP3_SPI_APPS_CLK_SRC                             5
  15 #define BLSP1_QUP4_I2C_APPS_CLK_SRC                             6
  16 #define BLSP1_QUP4_SPI_APPS_CLK_SRC                             7
  17 #define BLSP1_QUP5_I2C_APPS_CLK_SRC                             8
  18 #define BLSP1_QUP5_SPI_APPS_CLK_SRC                             9
  19 #define BLSP1_QUP6_I2C_APPS_CLK_SRC                             10
  20 #define BLSP1_QUP6_SPI_APPS_CLK_SRC                             11
  21 #define BLSP1_UART1_APPS_CLK_SRC                                12
  22 #define BLSP1_UART2_APPS_CLK_SRC                                13
  23 #define BLSP1_UART3_APPS_CLK_SRC                                14
  24 #define BLSP2_QUP1_I2C_APPS_CLK_SRC                             15
  25 #define BLSP2_QUP1_SPI_APPS_CLK_SRC                             16
  26 #define BLSP2_QUP2_I2C_APPS_CLK_SRC                             17
  27 #define BLSP2_QUP2_SPI_APPS_CLK_SRC                             18
  28 #define BLSP2_QUP3_I2C_APPS_CLK_SRC                             19
  29 #define BLSP2_QUP3_SPI_APPS_CLK_SRC                             20
  30 #define BLSP2_QUP4_I2C_APPS_CLK_SRC                             21
  31 #define BLSP2_QUP4_SPI_APPS_CLK_SRC                             22
  32 #define BLSP2_QUP5_I2C_APPS_CLK_SRC                             23
  33 #define BLSP2_QUP5_SPI_APPS_CLK_SRC                             24
  34 #define BLSP2_QUP6_I2C_APPS_CLK_SRC                             25
  35 #define BLSP2_QUP6_SPI_APPS_CLK_SRC                             26
  36 #define BLSP2_UART1_APPS_CLK_SRC                                27
  37 #define BLSP2_UART2_APPS_CLK_SRC                                28
  38 #define BLSP2_UART3_APPS_CLK_SRC                                29
  39 #define GCC_AGGRE1_NOC_XO_CLK                                   30
  40 #define GCC_AGGRE1_UFS_AXI_CLK                                  31
  41 #define GCC_AGGRE1_USB3_AXI_CLK                                 32
  42 #define GCC_APSS_QDSS_TSCTR_DIV2_CLK                            33
  43 #define GCC_APSS_QDSS_TSCTR_DIV8_CLK                            34
  44 #define GCC_BIMC_HMSS_AXI_CLK                                   35
  45 #define GCC_BIMC_MSS_Q6_AXI_CLK                                 36
  46 #define GCC_BLSP1_AHB_CLK                                       37
  47 #define GCC_BLSP1_QUP1_I2C_APPS_CLK                             38
  48 #define GCC_BLSP1_QUP1_SPI_APPS_CLK                             39
  49 #define GCC_BLSP1_QUP2_I2C_APPS_CLK                             40
  50 #define GCC_BLSP1_QUP2_SPI_APPS_CLK                             41
  51 #define GCC_BLSP1_QUP3_I2C_APPS_CLK                             42
  52 #define GCC_BLSP1_QUP3_SPI_APPS_CLK                             43
  53 #define GCC_BLSP1_QUP4_I2C_APPS_CLK                             44
  54 #define GCC_BLSP1_QUP4_SPI_APPS_CLK                             45
  55 #define GCC_BLSP1_QUP5_I2C_APPS_CLK                             46
  56 #define GCC_BLSP1_QUP5_SPI_APPS_CLK                             47
  57 #define GCC_BLSP1_QUP6_I2C_APPS_CLK                             48
  58 #define GCC_BLSP1_QUP6_SPI_APPS_CLK                             49
  59 #define GCC_BLSP1_SLEEP_CLK                                     50
  60 #define GCC_BLSP1_UART1_APPS_CLK                                51
  61 #define GCC_BLSP1_UART2_APPS_CLK                                52
  62 #define GCC_BLSP1_UART3_APPS_CLK                                53
  63 #define GCC_BLSP2_AHB_CLK                                       54
  64 #define GCC_BLSP2_QUP1_I2C_APPS_CLK                             55
  65 #define GCC_BLSP2_QUP1_SPI_APPS_CLK                             56
  66 #define GCC_BLSP2_QUP2_I2C_APPS_CLK                             57
  67 #define GCC_BLSP2_QUP2_SPI_APPS_CLK                             58
  68 #define GCC_BLSP2_QUP3_I2C_APPS_CLK                             59
  69 #define GCC_BLSP2_QUP3_SPI_APPS_CLK                             60
  70 #define GCC_BLSP2_QUP4_I2C_APPS_CLK                             61
  71 #define GCC_BLSP2_QUP4_SPI_APPS_CLK                             62
  72 #define GCC_BLSP2_QUP5_I2C_APPS_CLK                             63
  73 #define GCC_BLSP2_QUP5_SPI_APPS_CLK                             64
  74 #define GCC_BLSP2_QUP6_I2C_APPS_CLK                             65
  75 #define GCC_BLSP2_QUP6_SPI_APPS_CLK                             66
  76 #define GCC_BLSP2_SLEEP_CLK                                     67
  77 #define GCC_BLSP2_UART1_APPS_CLK                                68
  78 #define GCC_BLSP2_UART2_APPS_CLK                                69
  79 #define GCC_BLSP2_UART3_APPS_CLK                                70
  80 #define GCC_CFG_NOC_USB3_AXI_CLK                                71
  81 #define GCC_GP1_CLK                                             72
  82 #define GCC_GP2_CLK                                             73
  83 #define GCC_GP3_CLK                                             74
  84 #define GCC_GPU_BIMC_GFX_CLK                                    75
  85 #define GCC_GPU_BIMC_GFX_SRC_CLK                                76
  86 #define GCC_GPU_CFG_AHB_CLK                                     77
  87 #define GCC_GPU_SNOC_DVM_GFX_CLK                                78
  88 #define GCC_HMSS_AHB_CLK                                        79
  89 #define GCC_HMSS_AT_CLK                                         80
  90 #define GCC_HMSS_DVM_BUS_CLK                                    81
  91 #define GCC_HMSS_RBCPR_CLK                                      82
  92 #define GCC_HMSS_TRIG_CLK                                       83
  93 #define GCC_LPASS_AT_CLK                                        84
  94 #define GCC_LPASS_TRIG_CLK                                      85
  95 #define GCC_MMSS_NOC_CFG_AHB_CLK                                86
  96 #define GCC_MMSS_QM_AHB_CLK                                     87
  97 #define GCC_MMSS_QM_CORE_CLK                                    88
  98 #define GCC_MMSS_SYS_NOC_AXI_CLK                                89
  99 #define GCC_MSS_AT_CLK                                          90
 100 #define GCC_PCIE_0_AUX_CLK                                      91
 101 #define GCC_PCIE_0_CFG_AHB_CLK                                  92
 102 #define GCC_PCIE_0_MSTR_AXI_CLK                                 93
 103 #define GCC_PCIE_0_PIPE_CLK                                     94
 104 #define GCC_PCIE_0_SLV_AXI_CLK                                  95
 105 #define GCC_PCIE_PHY_AUX_CLK                                    96
 106 #define GCC_PDM2_CLK                                            97
 107 #define GCC_PDM_AHB_CLK                                         98
 108 #define GCC_PDM_XO4_CLK                                         99
 109 #define GCC_PRNG_AHB_CLK                                        100
 110 #define GCC_SDCC2_AHB_CLK                                       101
 111 #define GCC_SDCC2_APPS_CLK                                      102
 112 #define GCC_SDCC4_AHB_CLK                                       103
 113 #define GCC_SDCC4_APPS_CLK                                      104
 114 #define GCC_TSIF_AHB_CLK                                        105
 115 #define GCC_TSIF_INACTIVITY_TIMERS_CLK                          106
 116 #define GCC_TSIF_REF_CLK                                        107
 117 #define GCC_UFS_AHB_CLK                                         108
 118 #define GCC_UFS_AXI_CLK                                         109
 119 #define GCC_UFS_ICE_CORE_CLK                                    110
 120 #define GCC_UFS_PHY_AUX_CLK                                     111
 121 #define GCC_UFS_RX_SYMBOL_0_CLK                                 112
 122 #define GCC_UFS_RX_SYMBOL_1_CLK                                 113
 123 #define GCC_UFS_TX_SYMBOL_0_CLK                                 114
 124 #define GCC_UFS_UNIPRO_CORE_CLK                                 115
 125 #define GCC_USB30_MASTER_CLK                                    116
 126 #define GCC_USB30_MOCK_UTMI_CLK                                 117
 127 #define GCC_USB30_SLEEP_CLK                                     118
 128 #define GCC_USB3_PHY_AUX_CLK                                    119
 129 #define GCC_USB3_PHY_PIPE_CLK                                   120
 130 #define GCC_USB_PHY_CFG_AHB2PHY_CLK                             121
 131 #define GP1_CLK_SRC                                             122
 132 #define GP2_CLK_SRC                                             123
 133 #define GP3_CLK_SRC                                             124
 134 #define GPLL0                                                   125
 135 #define GPLL0_OUT_EVEN                                          126
 136 #define GPLL0_OUT_MAIN                                          127
 137 #define GPLL0_OUT_ODD                                           128
 138 #define GPLL0_OUT_TEST                                          129
 139 #define GPLL1                                                   130
 140 #define GPLL1_OUT_EVEN                                          131
 141 #define GPLL1_OUT_MAIN                                          132
 142 #define GPLL1_OUT_ODD                                           133
 143 #define GPLL1_OUT_TEST                                          134
 144 #define GPLL2                                                   135
 145 #define GPLL2_OUT_EVEN                                          136
 146 #define GPLL2_OUT_MAIN                                          137
 147 #define GPLL2_OUT_ODD                                           138
 148 #define GPLL2_OUT_TEST                                          139
 149 #define GPLL3                                                   140
 150 #define GPLL3_OUT_EVEN                                          141
 151 #define GPLL3_OUT_MAIN                                          142
 152 #define GPLL3_OUT_ODD                                           143
 153 #define GPLL3_OUT_TEST                                          144
 154 #define GPLL4                                                   145
 155 #define GPLL4_OUT_EVEN                                          146
 156 #define GPLL4_OUT_MAIN                                          147
 157 #define GPLL4_OUT_ODD                                           148
 158 #define GPLL4_OUT_TEST                                          149
 159 #define GPLL6                                                   150
 160 #define GPLL6_OUT_EVEN                                          151
 161 #define GPLL6_OUT_MAIN                                          152
 162 #define GPLL6_OUT_ODD                                           153
 163 #define GPLL6_OUT_TEST                                          154
 164 #define HMSS_AHB_CLK_SRC                                        155
 165 #define HMSS_RBCPR_CLK_SRC                                      156
 166 #define PCIE_AUX_CLK_SRC                                        157
 167 #define PDM2_CLK_SRC                                            158
 168 #define SDCC2_APPS_CLK_SRC                                      159
 169 #define SDCC4_APPS_CLK_SRC                                      160
 170 #define TSIF_REF_CLK_SRC                                        161
 171 #define UFS_AXI_CLK_SRC                                         162
 172 #define USB30_MASTER_CLK_SRC                                    163
 173 #define USB30_MOCK_UTMI_CLK_SRC                                 164
 174 #define USB3_PHY_AUX_CLK_SRC                                    165
 175 #define GCC_USB3_CLKREF_CLK                                     166
 176 #define GCC_HDMI_CLKREF_CLK                                     167
 177 #define GCC_UFS_CLKREF_CLK                                      168
 178 #define GCC_PCIE_CLKREF_CLK                                     169
 179 #define GCC_RX1_USB2_CLKREF_CLK                                 170
 180 #define GCC_MSS_CFG_AHB_CLK                                     171
 181 #define GCC_BOOT_ROM_AHB_CLK                                    172
 182 #define GCC_MSS_GPLL0_DIV_CLK_SRC                               173
 183 #define GCC_MSS_SNOC_AXI_CLK                                    174
 184 #define GCC_MSS_MNOC_BIMC_AXI_CLK                               175
 185 #define GCC_BIMC_GFX_CLK                                        176
 186 #define UFS_UNIPRO_CORE_CLK_SRC                                 177
 187 #define GCC_MMSS_GPLL0_CLK                                      178
 188 #define HMSS_GPLL0_CLK_SRC                                      179
 189 #define GCC_IM_SLEEP                                            180
 190 #define AGGRE2_SNOC_NORTH_AXI                                   181
 191 #define SSC_XO                                                  182
 192 #define SSC_CNOC_AHBS_CLK                                       183
 193 #define GCC_MMSS_GPLL0_DIV_CLK                                  184
 194 #define GCC_GPU_GPLL0_DIV_CLK                                   185
 195 #define GCC_GPU_GPLL0_CLK                                       186
 196
 197 #define PCIE_0_GDSC                                             0
 198 #define UFS_GDSC                                                1
 199 #define USB_30_GDSC                                             2
 200
 201 #define GCC_BLSP1_QUP1_BCR                                      0
 202 #define GCC_BLSP1_QUP2_BCR                                      1
 203 #define GCC_BLSP1_QUP3_BCR                                      2
 204 #define GCC_BLSP1_QUP4_BCR                                      3
 205 #define GCC_BLSP1_QUP5_BCR                                      4
 206 #define GCC_BLSP1_QUP6_BCR                                      5
 207 #define GCC_BLSP2_QUP1_BCR                                      6
 208 #define GCC_BLSP2_QUP2_BCR                                      7
 209 #define GCC_BLSP2_QUP3_BCR                                      8
 210 #define GCC_BLSP2_QUP4_BCR                                      9
 211 #define GCC_BLSP2_QUP5_BCR                                      10
 212 #define GCC_BLSP2_QUP6_BCR                                      11
 213 #define GCC_PCIE_0_BCR                                          12
 214 #define GCC_PDM_BCR                                             13
 215 #define GCC_SDCC2_BCR                                           14
 216 #define GCC_SDCC4_BCR                                           15
 217 #define GCC_TSIF_BCR                                            16
 218 #define GCC_UFS_BCR                                             17
 219 #define GCC_USB_30_BCR                                          18
 220 #define GCC_SYSTEM_NOC_BCR                                      19
 221 #define GCC_CONFIG_NOC_BCR                                      20
 222 #define GCC_AHB2PHY_EAST_BCR                                    21
 223 #define GCC_IMEM_BCR                                            22
 224 #define GCC_PIMEM_BCR                                           23
 225 #define GCC_MMSS_BCR                                            24
 226 #define GCC_QDSS_BCR                                            25
 227 #define GCC_WCSS_BCR                                            26
 228 #define GCC_BLSP1_BCR                                           27
 229 #define GCC_BLSP1_UART1_BCR                                     28
 230 #define GCC_BLSP1_UART2_BCR                                     29
 231 #define GCC_BLSP1_UART3_BCR                                     30
 232 #define GCC_CM_PHY_REFGEN1_BCR                                  31
 233 #define GCC_CM_PHY_REFGEN2_BCR                                  32
 234 #define GCC_BLSP2_BCR                                           33
 235 #define GCC_BLSP2_UART1_BCR                                     34
 236 #define GCC_BLSP2_UART2_BCR                                     35
 237 #define GCC_BLSP2_UART3_BCR                                     36
 238 #define GCC_SRAM_SENSOR_BCR                                     37
 239 #define GCC_PRNG_BCR                                            38
 240 #define GCC_TSIF_0_RESET                                        39
 241 #define GCC_TSIF_1_RESET                                        40
 242 #define GCC_TCSR_BCR                                            41
 243 #define GCC_BOOT_ROM_BCR                                        42
 244 #define GCC_MSG_RAM_BCR                                         43
 245 #define GCC_TLMM_BCR                                            44
 246 #define GCC_MPM_BCR                                             45
 247 #define GCC_SEC_CTRL_BCR                                        46
 248 #define GCC_SPMI_BCR                                            47
 249 #define GCC_SPDM_BCR                                            48
 250 #define GCC_CE1_BCR                                             49
 251 #define GCC_BIMC_BCR                                            50
 252 #define GCC_SNOC_BUS_TIMEOUT0_BCR                               51
 253 #define GCC_SNOC_BUS_TIMEOUT1_BCR                               52
 254 #define GCC_SNOC_BUS_TIMEOUT3_BCR                               53
 255 #define GCC_SNOC_BUS_TIMEOUT_EXTREF_BCR                         54
 256 #define GCC_PNOC_BUS_TIMEOUT0_BCR                               55
 257 #define GCC_CNOC_PERIPH_BUS_TIMEOUT1_BCR                        56
 258 #define GCC_CNOC_PERIPH_BUS_TIMEOUT2_BCR                        57
 259 #define GCC_CNOC_BUS_TIMEOUT0_BCR                               58
 260 #define GCC_CNOC_BUS_TIMEOUT1_BCR                               59
 261 #define GCC_CNOC_BUS_TIMEOUT2_BCR                               60
 262 #define GCC_CNOC_BUS_TIMEOUT3_BCR                               61
 263 #define GCC_CNOC_BUS_TIMEOUT4_BCR                               62
 264 #define GCC_CNOC_BUS_TIMEOUT5_BCR                               63
 265 #define GCC_CNOC_BUS_TIMEOUT6_BCR                               64
 266 #define GCC_CNOC_BUS_TIMEOUT7_BCR                               65
 267 #define GCC_APB2JTAG_BCR                                        66
 268 #define GCC_RBCPR_CX_BCR                                        67
 269 #define GCC_RBCPR_MX_BCR                                        68
 270 #define GCC_USB3_PHY_BCR                                        69
 271 #define GCC_USB3PHY_PHY_BCR                                     70
 272 #define GCC_USB3_DP_PHY_BCR                                     71
 273 #define GCC_SSC_BCR                                             72
 274 #define GCC_SSC_RESET                                           73
 275 #define GCC_USB_PHY_CFG_AHB2PHY_BCR                             74
 276 #define GCC_PCIE_0_LINK_DOWN_BCR                                75
 277 #define GCC_PCIE_0_PHY_BCR                                      76
 278 #define GCC_PCIE_0_NOCSR_COM_PHY_BCR                            77
 279 #define GCC_PCIE_PHY_BCR                                        78
 280 #define GCC_PCIE_PHY_NOCSR_COM_PHY_BCR                          79
 281 #define GCC_PCIE_PHY_CFG_AHB_BCR                                80
 282 #define GCC_PCIE_PHY_COM_BCR                                    81
 283 #define GCC_GPU_BCR                                             82
 284 #define GCC_SPSS_BCR                                            83
 285 #define GCC_OBT_ODT_BCR                                         84
 286 #define GCC_VS_BCR                                              85
 287 #define GCC_MSS_VS_RESET                                        86
 288 #define GCC_GPU_VS_RESET                                        87
 289 #define GCC_APC0_VS_RESET                                       88
 290 #define GCC_APC1_VS_RESET                                       89
 291 #define GCC_CNOC_BUS_TIMEOUT8_BCR                               90
 292 #define GCC_CNOC_BUS_TIMEOUT9_BCR                               91
 293 #define GCC_CNOC_BUS_TIMEOUT10_BCR                              92
 294 #define GCC_CNOC_BUS_TIMEOUT11_BCR                              93
 295 #define GCC_CNOC_BUS_TIMEOUT12_BCR                              94
 296 #define GCC_CNOC_BUS_TIMEOUT13_BCR                              95
 297 #define GCC_CNOC_BUS_TIMEOUT14_BCR                              96
 298 #define GCC_CNOC_BUS_TIMEOUT_EXTREF_BCR                         97
 299 #define GCC_AGGRE1_NOC_BCR                                      98
 300 #define GCC_AGGRE2_NOC_BCR                                      99
 301 #define GCC_DCC_BCR                                             100
 302 #define GCC_QREFS_VBG_CAL_BCR                                   101
 303 #define GCC_IPA_BCR                                             102
 304 #define GCC_GLM_BCR                                             103
 305 #define GCC_SKL_BCR                                             104
 306 #define GCC_MSMPU_BCR                                           105
 307 #define GCC_QUSB2PHY_PRIM_BCR                                   106
 308 #define GCC_QUSB2PHY_SEC_BCR                                    107
 309 #define GCC_MSS_RESTART                                         108
 310
 311 #endif