GNU Linux-libre 6.9.1-gnu
[releases.git] / include / dt-bindings / clock / qcom,gcc-msm8960.h
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4  */
5
6 #ifndef _DT_BINDINGS_CLK_MSM_GCC_8960_H
7 #define _DT_BINDINGS_CLK_MSM_GCC_8960_H
8
9 #define AFAB_CLK_SRC                            0
10 #define AFAB_CORE_CLK                           1
11 #define SFAB_MSS_Q6_SW_A_CLK                    2
12 #define SFAB_MSS_Q6_FW_A_CLK                    3
13 #define QDSS_STM_CLK                            4
14 #define SCSS_A_CLK                              5
15 #define SCSS_H_CLK                              6
16 #define SCSS_XO_SRC_CLK                         7
17 #define AFAB_EBI1_CH0_A_CLK                     8
18 #define AFAB_EBI1_CH1_A_CLK                     9
19 #define AFAB_AXI_S0_FCLK                        10
20 #define AFAB_AXI_S1_FCLK                        11
21 #define AFAB_AXI_S2_FCLK                        12
22 #define AFAB_AXI_S3_FCLK                        13
23 #define AFAB_AXI_S4_FCLK                        14
24 #define SFAB_CORE_CLK                           15
25 #define SFAB_AXI_S0_FCLK                        16
26 #define SFAB_AXI_S1_FCLK                        17
27 #define SFAB_AXI_S2_FCLK                        18
28 #define SFAB_AXI_S3_FCLK                        19
29 #define SFAB_AXI_S4_FCLK                        20
30 #define SFAB_AHB_S0_FCLK                        21
31 #define SFAB_AHB_S1_FCLK                        22
32 #define SFAB_AHB_S2_FCLK                        23
33 #define SFAB_AHB_S3_FCLK                        24
34 #define SFAB_AHB_S4_FCLK                        25
35 #define SFAB_AHB_S5_FCLK                        26
36 #define SFAB_AHB_S6_FCLK                        27
37 #define SFAB_AHB_S7_FCLK                        28
38 #define QDSS_AT_CLK_SRC                         29
39 #define QDSS_AT_CLK                             30
40 #define QDSS_TRACECLKIN_CLK_SRC                 31
41 #define QDSS_TRACECLKIN_CLK                     32
42 #define QDSS_TSCTR_CLK_SRC                      33
43 #define QDSS_TSCTR_CLK                          34
44 #define SFAB_ADM0_M0_A_CLK                      35
45 #define SFAB_ADM0_M1_A_CLK                      36
46 #define SFAB_ADM0_M2_H_CLK                      37
47 #define ADM0_CLK                                38
48 #define ADM0_PBUS_CLK                           39
49 #define MSS_XPU_CLK                             40
50 #define IMEM0_A_CLK                             41
51 #define QDSS_H_CLK                              42
52 #define PCIE_A_CLK                              43
53 #define PCIE_AUX_CLK                            44
54 #define PCIE_PHY_REF_CLK                        45
55 #define PCIE_H_CLK                              46
56 #define SFAB_CLK_SRC                            47
57 #define MAHB0_CLK                               48
58 #define Q6SW_CLK_SRC                            49
59 #define Q6SW_CLK                                50
60 #define Q6FW_CLK_SRC                            51
61 #define Q6FW_CLK                                52
62 #define SFAB_MSS_M_A_CLK                        53
63 #define SFAB_USB3_M_A_CLK                       54
64 #define SFAB_LPASS_Q6_A_CLK                     55
65 #define SFAB_AFAB_M_A_CLK                       56
66 #define AFAB_SFAB_M0_A_CLK                      57
67 #define AFAB_SFAB_M1_A_CLK                      58
68 #define SFAB_SATA_S_H_CLK                       59
69 #define DFAB_CLK_SRC                            60
70 #define DFAB_CLK                                61
71 #define SFAB_DFAB_M_A_CLK                       62
72 #define DFAB_SFAB_M_A_CLK                       63
73 #define DFAB_SWAY0_H_CLK                        64
74 #define DFAB_SWAY1_H_CLK                        65
75 #define DFAB_ARB0_H_CLK                         66
76 #define DFAB_ARB1_H_CLK                         67
77 #define PPSS_H_CLK                              68
78 #define PPSS_PROC_CLK                           69
79 #define PPSS_TIMER0_CLK                         70
80 #define PPSS_TIMER1_CLK                         71
81 #define PMEM_A_CLK                              72
82 #define DMA_BAM_H_CLK                           73
83 #define SIC_H_CLK                               74
84 #define SPS_TIC_H_CLK                           75
85 #define SLIMBUS_H_CLK                           76
86 #define SLIMBUS_XO_SRC_CLK                      77
87 #define CFPB_2X_CLK_SRC                         78
88 #define CFPB_CLK                                79
89 #define CFPB0_H_CLK                             80
90 #define CFPB1_H_CLK                             81
91 #define CFPB2_H_CLK                             82
92 #define SFAB_CFPB_M_H_CLK                       83
93 #define CFPB_MASTER_H_CLK                       84
94 #define SFAB_CFPB_S_H_CLK                       85
95 #define CFPB_SPLITTER_H_CLK                     86
96 #define TSIF_H_CLK                              87
97 #define TSIF_INACTIVITY_TIMERS_CLK              88
98 #define TSIF_REF_SRC                            89
99 #define TSIF_REF_CLK                            90
100 #define CE1_H_CLK                               91
101 #define CE1_CORE_CLK                            92
102 #define CE1_SLEEP_CLK                           93
103 #define CE2_H_CLK                               94
104 #define CE2_CORE_CLK                            95
105 #define SFPB_H_CLK_SRC                          97
106 #define SFPB_H_CLK                              98
107 #define SFAB_SFPB_M_H_CLK                       99
108 #define SFAB_SFPB_S_H_CLK                       100
109 #define RPM_PROC_CLK                            101
110 #define RPM_BUS_H_CLK                           102
111 #define RPM_SLEEP_CLK                           103
112 #define RPM_TIMER_CLK                           104
113 #define RPM_MSG_RAM_H_CLK                       105
114 #define PMIC_ARB0_H_CLK                         106
115 #define PMIC_ARB1_H_CLK                         107
116 #define PMIC_SSBI2_SRC                          108
117 #define PMIC_SSBI2_CLK                          109
118 #define SDC1_H_CLK                              110
119 #define SDC2_H_CLK                              111
120 #define SDC3_H_CLK                              112
121 #define SDC4_H_CLK                              113
122 #define SDC5_H_CLK                              114
123 #define SDC1_SRC                                115
124 #define SDC2_SRC                                116
125 #define SDC3_SRC                                117
126 #define SDC4_SRC                                118
127 #define SDC5_SRC                                119
128 #define SDC1_CLK                                120
129 #define SDC2_CLK                                121
130 #define SDC3_CLK                                122
131 #define SDC4_CLK                                123
132 #define SDC5_CLK                                124
133 #define DFAB_A2_H_CLK                           125
134 #define USB_HS1_H_CLK                           126
135 #define USB_HS1_XCVR_SRC                        127
136 #define USB_HS1_XCVR_CLK                        128
137 #define USB_HSIC_H_CLK                          129
138 #define USB_HSIC_XCVR_FS_SRC                    130
139 #define USB_HSIC_XCVR_FS_CLK                    131
140 #define USB_HSIC_SYSTEM_CLK_SRC                 132
141 #define USB_HSIC_SYSTEM_CLK                     133
142 #define CFPB0_C0_H_CLK                          134
143 #define CFPB0_C1_H_CLK                          135
144 #define CFPB0_D0_H_CLK                          136
145 #define CFPB0_D1_H_CLK                          137
146 #define USB_FS1_H_CLK                           138
147 #define USB_FS1_XCVR_FS_SRC                     139
148 #define USB_FS1_XCVR_FS_CLK                     140
149 #define USB_FS1_SYSTEM_CLK                      141
150 #define USB_FS2_H_CLK                           142
151 #define USB_FS2_XCVR_FS_SRC                     143
152 #define USB_FS2_XCVR_FS_CLK                     144
153 #define USB_FS2_SYSTEM_CLK                      145
154 #define GSBI_COMMON_SIM_SRC                     146
155 #define GSBI1_H_CLK                             147
156 #define GSBI2_H_CLK                             148
157 #define GSBI3_H_CLK                             149
158 #define GSBI4_H_CLK                             150
159 #define GSBI5_H_CLK                             151
160 #define GSBI6_H_CLK                             152
161 #define GSBI7_H_CLK                             153
162 #define GSBI8_H_CLK                             154
163 #define GSBI9_H_CLK                             155
164 #define GSBI10_H_CLK                            156
165 #define GSBI11_H_CLK                            157
166 #define GSBI12_H_CLK                            158
167 #define GSBI1_UART_SRC                          159
168 #define GSBI1_UART_CLK                          160
169 #define GSBI2_UART_SRC                          161
170 #define GSBI2_UART_CLK                          162
171 #define GSBI3_UART_SRC                          163
172 #define GSBI3_UART_CLK                          164
173 #define GSBI4_UART_SRC                          165
174 #define GSBI4_UART_CLK                          166
175 #define GSBI5_UART_SRC                          167
176 #define GSBI5_UART_CLK                          168
177 #define GSBI6_UART_SRC                          169
178 #define GSBI6_UART_CLK                          170
179 #define GSBI7_UART_SRC                          171
180 #define GSBI7_UART_CLK                          172
181 #define GSBI8_UART_SRC                          173
182 #define GSBI8_UART_CLK                          174
183 #define GSBI9_UART_SRC                          175
184 #define GSBI9_UART_CLK                          176
185 #define GSBI10_UART_SRC                         177
186 #define GSBI10_UART_CLK                         178
187 #define GSBI11_UART_SRC                         179
188 #define GSBI11_UART_CLK                         180
189 #define GSBI12_UART_SRC                         181
190 #define GSBI12_UART_CLK                         182
191 #define GSBI1_QUP_SRC                           183
192 #define GSBI1_QUP_CLK                           184
193 #define GSBI2_QUP_SRC                           185
194 #define GSBI2_QUP_CLK                           186
195 #define GSBI3_QUP_SRC                           187
196 #define GSBI3_QUP_CLK                           188
197 #define GSBI4_QUP_SRC                           189
198 #define GSBI4_QUP_CLK                           190
199 #define GSBI5_QUP_SRC                           191
200 #define GSBI5_QUP_CLK                           192
201 #define GSBI6_QUP_SRC                           193
202 #define GSBI6_QUP_CLK                           194
203 #define GSBI7_QUP_SRC                           195
204 #define GSBI7_QUP_CLK                           196
205 #define GSBI8_QUP_SRC                           197
206 #define GSBI8_QUP_CLK                           198
207 #define GSBI9_QUP_SRC                           199
208 #define GSBI9_QUP_CLK                           200
209 #define GSBI10_QUP_SRC                          201
210 #define GSBI10_QUP_CLK                          202
211 #define GSBI11_QUP_SRC                          203
212 #define GSBI11_QUP_CLK                          204
213 #define GSBI12_QUP_SRC                          205
214 #define GSBI12_QUP_CLK                          206
215 #define GSBI1_SIM_CLK                           207
216 #define GSBI2_SIM_CLK                           208
217 #define GSBI3_SIM_CLK                           209
218 #define GSBI4_SIM_CLK                           210
219 #define GSBI5_SIM_CLK                           211
220 #define GSBI6_SIM_CLK                           212
221 #define GSBI7_SIM_CLK                           213
222 #define GSBI8_SIM_CLK                           214
223 #define GSBI9_SIM_CLK                           215
224 #define GSBI10_SIM_CLK                          216
225 #define GSBI11_SIM_CLK                          217
226 #define GSBI12_SIM_CLK                          218
227 #define USB_HSIC_HSIC_CLK_SRC                   219
228 #define USB_HSIC_HSIC_CLK                       220
229 #define USB_HSIC_HSIO_CAL_CLK                   221
230 #define SPDM_CFG_H_CLK                          222
231 #define SPDM_MSTR_H_CLK                         223
232 #define SPDM_FF_CLK_SRC                         224
233 #define SPDM_FF_CLK                             225
234 #define SEC_CTRL_CLK                            226
235 #define SEC_CTRL_ACC_CLK_SRC                    227
236 #define SEC_CTRL_ACC_CLK                        228
237 #define TLMM_H_CLK                              229
238 #define TLMM_CLK                                230
239 #define SFAB_MSS_S_H_CLK                        231
240 #define MSS_SLP_CLK                             232
241 #define MSS_Q6SW_JTAG_CLK                       233
242 #define MSS_Q6FW_JTAG_CLK                       234
243 #define MSS_S_H_CLK                             235
244 #define MSS_CXO_SRC_CLK                         236
245 #define SATA_H_CLK                              237
246 #define SATA_CLK_SRC                            238
247 #define SATA_RXOOB_CLK                          239
248 #define SATA_PMALIVE_CLK                        240
249 #define SATA_PHY_REF_CLK                        241
250 #define TSSC_CLK_SRC                            242
251 #define TSSC_CLK                                243
252 #define PDM_SRC                                 244
253 #define PDM_CLK                                 245
254 #define GP0_SRC                                 246
255 #define GP0_CLK                                 247
256 #define GP1_SRC                                 248
257 #define GP1_CLK                                 249
258 #define GP2_SRC                                 250
259 #define GP2_CLK                                 251
260 #define MPM_CLK                                 252
261 #define EBI1_CLK_SRC                            253
262 #define EBI1_CH0_CLK                            254
263 #define EBI1_CH1_CLK                            255
264 #define EBI1_2X_CLK                             256
265 #define EBI1_CH0_DQ_CLK                         257
266 #define EBI1_CH1_DQ_CLK                         258
267 #define EBI1_CH0_CA_CLK                         259
268 #define EBI1_CH1_CA_CLK                         260
269 #define EBI1_XO_CLK                             261
270 #define SFAB_SMPSS_S_H_CLK                      262
271 #define PRNG_SRC                                263
272 #define PRNG_CLK                                264
273 #define PXO_SRC                                 265
274 #define LPASS_CXO_CLK                           266
275 #define LPASS_PXO_CLK                           267
276 #define SPDM_CY_PORT0_CLK                       268
277 #define SPDM_CY_PORT1_CLK                       269
278 #define SPDM_CY_PORT2_CLK                       270
279 #define SPDM_CY_PORT3_CLK                       271
280 #define SPDM_CY_PORT4_CLK                       272
281 #define SPDM_CY_PORT5_CLK                       273
282 #define SPDM_CY_PORT6_CLK                       274
283 #define SPDM_CY_PORT7_CLK                       275
284 #define PLL0                                    276
285 #define PLL0_VOTE                               277
286 #define PLL3                                    278
287 #define PLL3_VOTE                               279
288 #define PLL4_VOTE                               280
289 #define PLL5                                    281
290 #define PLL5_VOTE                               282
291 #define PLL6                                    283
292 #define PLL6_VOTE                               284
293 #define PLL7_VOTE                               285
294 #define PLL8                                    286
295 #define PLL8_VOTE                               287
296 #define PLL9                                    288
297 #define PLL10                                   289
298 #define PLL11                                   290
299 #define PLL12                                   291
300 #define PLL13                                   292
301 #define PLL14                                   293
302 #define PLL14_VOTE                              294
303 #define USB_HS3_H_CLK                           295
304 #define USB_HS3_XCVR_SRC                        296
305 #define USB_HS3_XCVR_CLK                        297
306 #define USB_HS4_H_CLK                           298
307 #define USB_HS4_XCVR_SRC                        299
308 #define USB_HS4_XCVR_CLK                        300
309 #define SATA_PHY_CFG_CLK                        301
310 #define SATA_A_CLK                              302
311 #define CE3_SRC                                 303
312 #define CE3_CORE_CLK                            304
313 #define CE3_H_CLK                               305
314 #define PLL16                                   306
315 #define PLL17                                   307
316
317 #endif