include/dt-bindings/clock/qcom,camcc-sdm845.h

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #ifndef _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
   7 #define _DT_BINDINGS_CLK_SDM_CAM_CC_SDM845_H
   8
   9 /* CAM_CC clock registers */
  10 #define CAM_CC_BPS_AHB_CLK                              0
  11 #define CAM_CC_BPS_AREG_CLK                             1
  12 #define CAM_CC_BPS_AXI_CLK                              2
  13 #define CAM_CC_BPS_CLK                                  3
  14 #define CAM_CC_BPS_CLK_SRC                              4
  15 #define CAM_CC_CAMNOC_ATB_CLK                           5
  16 #define CAM_CC_CAMNOC_AXI_CLK                           6
  17 #define CAM_CC_CCI_CLK                                  7
  18 #define CAM_CC_CCI_CLK_SRC                              8
  19 #define CAM_CC_CPAS_AHB_CLK                             9
  20 #define CAM_CC_CPHY_RX_CLK_SRC                          10
  21 #define CAM_CC_CSI0PHYTIMER_CLK                         11
  22 #define CAM_CC_CSI0PHYTIMER_CLK_SRC                     12
  23 #define CAM_CC_CSI1PHYTIMER_CLK                         13
  24 #define CAM_CC_CSI1PHYTIMER_CLK_SRC                     14
  25 #define CAM_CC_CSI2PHYTIMER_CLK                         15
  26 #define CAM_CC_CSI2PHYTIMER_CLK_SRC                     16
  27 #define CAM_CC_CSI3PHYTIMER_CLK                         17
  28 #define CAM_CC_CSI3PHYTIMER_CLK_SRC                     18
  29 #define CAM_CC_CSIPHY0_CLK                              19
  30 #define CAM_CC_CSIPHY1_CLK                              20
  31 #define CAM_CC_CSIPHY2_CLK                              21
  32 #define CAM_CC_CSIPHY3_CLK                              22
  33 #define CAM_CC_FAST_AHB_CLK_SRC                         23
  34 #define CAM_CC_FD_CORE_CLK                              24
  35 #define CAM_CC_FD_CORE_CLK_SRC                          25
  36 #define CAM_CC_FD_CORE_UAR_CLK                          26
  37 #define CAM_CC_ICP_APB_CLK                              27
  38 #define CAM_CC_ICP_ATB_CLK                              28
  39 #define CAM_CC_ICP_CLK                                  29
  40 #define CAM_CC_ICP_CLK_SRC                              30
  41 #define CAM_CC_ICP_CTI_CLK                              31
  42 #define CAM_CC_ICP_TS_CLK                               32
  43 #define CAM_CC_IFE_0_AXI_CLK                            33
  44 #define CAM_CC_IFE_0_CLK                                34
  45 #define CAM_CC_IFE_0_CLK_SRC                            35
  46 #define CAM_CC_IFE_0_CPHY_RX_CLK                        36
  47 #define CAM_CC_IFE_0_CSID_CLK                           37
  48 #define CAM_CC_IFE_0_CSID_CLK_SRC                       38
  49 #define CAM_CC_IFE_0_DSP_CLK                            39
  50 #define CAM_CC_IFE_1_AXI_CLK                            40
  51 #define CAM_CC_IFE_1_CLK                                41
  52 #define CAM_CC_IFE_1_CLK_SRC                            42
  53 #define CAM_CC_IFE_1_CPHY_RX_CLK                        43
  54 #define CAM_CC_IFE_1_CSID_CLK                           44
  55 #define CAM_CC_IFE_1_CSID_CLK_SRC                       45
  56 #define CAM_CC_IFE_1_DSP_CLK                            46
  57 #define CAM_CC_IFE_LITE_CLK                             47
  58 #define CAM_CC_IFE_LITE_CLK_SRC                         48
  59 #define CAM_CC_IFE_LITE_CPHY_RX_CLK                     49
  60 #define CAM_CC_IFE_LITE_CSID_CLK                        50
  61 #define CAM_CC_IFE_LITE_CSID_CLK_SRC                    51
  62 #define CAM_CC_IPE_0_AHB_CLK                            52
  63 #define CAM_CC_IPE_0_AREG_CLK                           53
  64 #define CAM_CC_IPE_0_AXI_CLK                            54
  65 #define CAM_CC_IPE_0_CLK                                55
  66 #define CAM_CC_IPE_0_CLK_SRC                            56
  67 #define CAM_CC_IPE_1_AHB_CLK                            57
  68 #define CAM_CC_IPE_1_AREG_CLK                           58
  69 #define CAM_CC_IPE_1_AXI_CLK                            59
  70 #define CAM_CC_IPE_1_CLK                                60
  71 #define CAM_CC_IPE_1_CLK_SRC                            61
  72 #define CAM_CC_JPEG_CLK                                 62
  73 #define CAM_CC_JPEG_CLK_SRC                             63
  74 #define CAM_CC_LRME_CLK                                 64
  75 #define CAM_CC_LRME_CLK_SRC                             65
  76 #define CAM_CC_MCLK0_CLK                                66
  77 #define CAM_CC_MCLK0_CLK_SRC                            67
  78 #define CAM_CC_MCLK1_CLK                                68
  79 #define CAM_CC_MCLK1_CLK_SRC                            69
  80 #define CAM_CC_MCLK2_CLK                                70
  81 #define CAM_CC_MCLK2_CLK_SRC                            71
  82 #define CAM_CC_MCLK3_CLK                                72
  83 #define CAM_CC_MCLK3_CLK_SRC                            73
  84 #define CAM_CC_PLL0                                     74
  85 #define CAM_CC_PLL0_OUT_EVEN                            75
  86 #define CAM_CC_PLL1                                     76
  87 #define CAM_CC_PLL1_OUT_EVEN                            77
  88 #define CAM_CC_PLL2                                     78
  89 #define CAM_CC_PLL2_OUT_EVEN                            79
  90 #define CAM_CC_PLL3                                     80
  91 #define CAM_CC_PLL3_OUT_EVEN                            81
  92 #define CAM_CC_SLOW_AHB_CLK_SRC                         82
  93 #define CAM_CC_SOC_AHB_CLK                              83
  94 #define CAM_CC_SYS_TMR_CLK                              84
  95
  96 /* CAM_CC Resets */
  97 #define TITAN_CAM_CC_CCI_BCR                            0
  98 #define TITAN_CAM_CC_CPAS_BCR                           1
  99 #define TITAN_CAM_CC_CSI0PHY_BCR                        2
 100 #define TITAN_CAM_CC_CSI1PHY_BCR                        3
 101 #define TITAN_CAM_CC_CSI2PHY_BCR                        4
 102 #define TITAN_CAM_CC_MCLK0_BCR                          5
 103 #define TITAN_CAM_CC_MCLK1_BCR                          6
 104 #define TITAN_CAM_CC_MCLK2_BCR                          7
 105 #define TITAN_CAM_CC_MCLK3_BCR                          8
 106 #define TITAN_CAM_CC_TITAN_TOP_BCR                      9
 107
 108 /* CAM_CC GDSCRs */
 109 #define BPS_GDSC                                        0
 110 #define IPE_0_GDSC                                      1
 111 #define IPE_1_GDSC                                      2
 112 #define IFE_0_GDSC                                      3
 113 #define IFE_1_GDSC                                      4
 114 #define TITAN_TOP_GDSC                                  5
 115
 116 #endif