GNU Linux-libre 6.9.1-gnu
[releases.git] / include / dt-bindings / clock / pistachio-clk.h
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2014 Google, Inc.
4  */
5
6 #ifndef _DT_BINDINGS_CLOCK_PISTACHIO_H
7 #define _DT_BINDINGS_CLOCK_PISTACHIO_H
8
9 /* PLLs */
10 #define CLK_MIPS_PLL                    0
11 #define CLK_AUDIO_PLL                   1
12 #define CLK_RPU_V_PLL                   2
13 #define CLK_RPU_L_PLL                   3
14 #define CLK_SYS_PLL                     4
15 #define CLK_WIFI_PLL                    5
16 #define CLK_BT_PLL                      6
17
18 /* Fixed-factor clocks */
19 #define CLK_WIFI_DIV4                   16
20 #define CLK_WIFI_DIV8                   17
21
22 /* Gate clocks */
23 #define CLK_MIPS                        32
24 #define CLK_AUDIO_IN                    33
25 #define CLK_AUDIO                       34
26 #define CLK_I2S                         35
27 #define CLK_SPDIF                       36
28 #define CLK_AUDIO_DAC                   37
29 #define CLK_RPU_V                       38
30 #define CLK_RPU_L                       39
31 #define CLK_RPU_SLEEP                   40
32 #define CLK_WIFI_PLL_GATE               41
33 #define CLK_RPU_CORE                    42
34 #define CLK_WIFI_ADC                    43
35 #define CLK_WIFI_DAC                    44
36 #define CLK_USB_PHY                     45
37 #define CLK_ENET_IN                     46
38 #define CLK_ENET                        47
39 #define CLK_UART0                       48
40 #define CLK_UART1                       49
41 #define CLK_PERIPH_SYS                  50
42 #define CLK_SPI0                        51
43 #define CLK_SPI1                        52
44 #define CLK_EVENT_TIMER                 53
45 #define CLK_AUX_ADC_INTERNAL            54
46 #define CLK_AUX_ADC                     55
47 #define CLK_SD_HOST                     56
48 #define CLK_BT                          57
49 #define CLK_BT_DIV4                     58
50 #define CLK_BT_DIV8                     59
51 #define CLK_BT_1MHZ                     60
52
53 /* Divider clocks */
54 #define CLK_MIPS_INTERNAL_DIV           64
55 #define CLK_MIPS_DIV                    65
56 #define CLK_AUDIO_DIV                   66
57 #define CLK_I2S_DIV                     67
58 #define CLK_SPDIF_DIV                   68
59 #define CLK_AUDIO_DAC_DIV               69
60 #define CLK_RPU_V_DIV                   70
61 #define CLK_RPU_L_DIV                   71
62 #define CLK_RPU_SLEEP_DIV               72
63 #define CLK_RPU_CORE_DIV                73
64 #define CLK_USB_PHY_DIV                 74
65 #define CLK_ENET_DIV                    75
66 #define CLK_UART0_INTERNAL_DIV          76
67 #define CLK_UART0_DIV                   77
68 #define CLK_UART1_INTERNAL_DIV          78
69 #define CLK_UART1_DIV                   79
70 #define CLK_SYS_INTERNAL_DIV            80
71 #define CLK_SPI0_INTERNAL_DIV           81
72 #define CLK_SPI0_DIV                    82
73 #define CLK_SPI1_INTERNAL_DIV           83
74 #define CLK_SPI1_DIV                    84
75 #define CLK_EVENT_TIMER_INTERNAL_DIV    85
76 #define CLK_EVENT_TIMER_DIV             86
77 #define CLK_AUX_ADC_INTERNAL_DIV        87
78 #define CLK_AUX_ADC_DIV                 88
79 #define CLK_SD_HOST_DIV                 89
80 #define CLK_BT_DIV                      90
81 #define CLK_BT_DIV4_DIV                 91
82 #define CLK_BT_DIV8_DIV                 92
83 #define CLK_BT_1MHZ_INTERNAL_DIV        93
84 #define CLK_BT_1MHZ_DIV                 94
85
86 /* Mux clocks */
87 #define CLK_AUDIO_REF_MUX               96
88 #define CLK_MIPS_PLL_MUX                97
89 #define CLK_AUDIO_PLL_MUX               98
90 #define CLK_AUDIO_MUX                   99
91 #define CLK_RPU_V_PLL_MUX               100
92 #define CLK_RPU_L_PLL_MUX               101
93 #define CLK_RPU_L_MUX                   102
94 #define CLK_WIFI_PLL_MUX                103
95 #define CLK_WIFI_DIV4_MUX               104
96 #define CLK_WIFI_DIV8_MUX               105
97 #define CLK_RPU_CORE_MUX                106
98 #define CLK_SYS_PLL_MUX                 107
99 #define CLK_ENET_MUX                    108
100 #define CLK_EVENT_TIMER_MUX             109
101 #define CLK_SD_HOST_MUX                 110
102 #define CLK_BT_PLL_MUX                  111
103 #define CLK_DEBUG_MUX                   112
104
105 #define CLK_NR_CLKS                     113
106
107 /* Peripheral gate clocks */
108 #define PERIPH_CLK_SYS                  0
109 #define PERIPH_CLK_SYS_BUS              1
110 #define PERIPH_CLK_DDR                  2
111 #define PERIPH_CLK_ROM                  3
112 #define PERIPH_CLK_COUNTER_FAST         4
113 #define PERIPH_CLK_COUNTER_SLOW         5
114 #define PERIPH_CLK_IR                   6
115 #define PERIPH_CLK_WD                   7
116 #define PERIPH_CLK_PDM                  8
117 #define PERIPH_CLK_PWM                  9
118 #define PERIPH_CLK_I2C0                 10
119 #define PERIPH_CLK_I2C1                 11
120 #define PERIPH_CLK_I2C2                 12
121 #define PERIPH_CLK_I2C3                 13
122
123 /* Peripheral divider clocks */
124 #define PERIPH_CLK_ROM_DIV              32
125 #define PERIPH_CLK_COUNTER_FAST_DIV     33
126 #define PERIPH_CLK_COUNTER_SLOW_PRE_DIV 34
127 #define PERIPH_CLK_COUNTER_SLOW_DIV     35
128 #define PERIPH_CLK_IR_PRE_DIV           36
129 #define PERIPH_CLK_IR_DIV               37
130 #define PERIPH_CLK_WD_PRE_DIV           38
131 #define PERIPH_CLK_WD_DIV               39
132 #define PERIPH_CLK_PDM_PRE_DIV          40
133 #define PERIPH_CLK_PDM_DIV              41
134 #define PERIPH_CLK_PWM_PRE_DIV          42
135 #define PERIPH_CLK_PWM_DIV              43
136 #define PERIPH_CLK_I2C0_PRE_DIV         44
137 #define PERIPH_CLK_I2C0_DIV             45
138 #define PERIPH_CLK_I2C1_PRE_DIV         46
139 #define PERIPH_CLK_I2C1_DIV             47
140 #define PERIPH_CLK_I2C2_PRE_DIV         48
141 #define PERIPH_CLK_I2C2_DIV             49
142 #define PERIPH_CLK_I2C3_PRE_DIV         50
143 #define PERIPH_CLK_I2C3_DIV             51
144
145 #define PERIPH_CLK_NR_CLKS              52
146
147 /* System gate clocks */
148 #define SYS_CLK_I2C0                    0
149 #define SYS_CLK_I2C1                    1
150 #define SYS_CLK_I2C2                    2
151 #define SYS_CLK_I2C3                    3
152 #define SYS_CLK_I2S_IN                  4
153 #define SYS_CLK_PAUD_OUT                5
154 #define SYS_CLK_SPDIF_OUT               6
155 #define SYS_CLK_SPI0_MASTER             7
156 #define SYS_CLK_SPI0_SLAVE              8
157 #define SYS_CLK_PWM                     9
158 #define SYS_CLK_UART0                   10
159 #define SYS_CLK_UART1                   11
160 #define SYS_CLK_SPI1                    12
161 #define SYS_CLK_MDC                     13
162 #define SYS_CLK_SD_HOST                 14
163 #define SYS_CLK_ENET                    15
164 #define SYS_CLK_IR                      16
165 #define SYS_CLK_WD                      17
166 #define SYS_CLK_TIMER                   18
167 #define SYS_CLK_I2S_OUT                 24
168 #define SYS_CLK_SPDIF_IN                25
169 #define SYS_CLK_EVENT_TIMER             26
170 #define SYS_CLK_HASH                    27
171
172 #define SYS_CLK_NR_CLKS                 28
173
174 /* Gates for external input clocks */
175 #define EXT_CLK_AUDIO_IN                0
176 #define EXT_CLK_ENET_IN                 1
177
178 #define EXT_CLK_NR_CLKS                 2
179
180 #endif /* _DT_BINDINGS_CLOCK_PISTACHIO_H */