GNU Linux-libre 6.9.1-gnu
[releases.git] / include / dt-bindings / clock / mt8516-clk.h
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2019 MediaTek Inc.
4  * Copyright (c) 2019 BayLibre, SAS.
5  * Author: James Liao <jamesjj.liao@mediatek.com>
6  */
7
8 #ifndef _DT_BINDINGS_CLK_MT8516_H
9 #define _DT_BINDINGS_CLK_MT8516_H
10
11 /* APMIXEDSYS */
12
13 #define CLK_APMIXED_ARMPLL              0
14 #define CLK_APMIXED_MAINPLL             1
15 #define CLK_APMIXED_UNIVPLL             2
16 #define CLK_APMIXED_MMPLL               3
17 #define CLK_APMIXED_APLL1               4
18 #define CLK_APMIXED_APLL2               5
19 #define CLK_APMIXED_NR_CLK              6
20
21 /* INFRACFG */
22
23 #define CLK_IFR_MUX1_SEL                0
24 #define CLK_IFR_ETH_25M_SEL             1
25 #define CLK_IFR_I2C0_SEL                2
26 #define CLK_IFR_I2C1_SEL                3
27 #define CLK_IFR_I2C2_SEL                4
28 #define CLK_IFR_NR_CLK                  5
29
30 /* TOPCKGEN */
31
32 #define CLK_TOP_CLK_NULL                0
33 #define CLK_TOP_I2S_INFRA_BCK           1
34 #define CLK_TOP_MEMPLL                  2
35 #define CLK_TOP_DMPLL                   3
36 #define CLK_TOP_MAINPLL_D2              4
37 #define CLK_TOP_MAINPLL_D4              5
38 #define CLK_TOP_MAINPLL_D8              6
39 #define CLK_TOP_MAINPLL_D16             7
40 #define CLK_TOP_MAINPLL_D11             8
41 #define CLK_TOP_MAINPLL_D22             9
42 #define CLK_TOP_MAINPLL_D3              10
43 #define CLK_TOP_MAINPLL_D6              11
44 #define CLK_TOP_MAINPLL_D12             12
45 #define CLK_TOP_MAINPLL_D5              13
46 #define CLK_TOP_MAINPLL_D10             14
47 #define CLK_TOP_MAINPLL_D20             15
48 #define CLK_TOP_MAINPLL_D40             16
49 #define CLK_TOP_MAINPLL_D7              17
50 #define CLK_TOP_MAINPLL_D14             18
51 #define CLK_TOP_UNIVPLL_D2              19
52 #define CLK_TOP_UNIVPLL_D4              20
53 #define CLK_TOP_UNIVPLL_D8              21
54 #define CLK_TOP_UNIVPLL_D16             22
55 #define CLK_TOP_UNIVPLL_D3              23
56 #define CLK_TOP_UNIVPLL_D6              24
57 #define CLK_TOP_UNIVPLL_D12             25
58 #define CLK_TOP_UNIVPLL_D24             26
59 #define CLK_TOP_UNIVPLL_D5              27
60 #define CLK_TOP_UNIVPLL_D20             28
61 #define CLK_TOP_MMPLL380M               29
62 #define CLK_TOP_MMPLL_D2                30
63 #define CLK_TOP_MMPLL_200M              31
64 #define CLK_TOP_USB_PHY48M              32
65 #define CLK_TOP_APLL1                   33
66 #define CLK_TOP_APLL1_D2                34
67 #define CLK_TOP_APLL1_D4                35
68 #define CLK_TOP_APLL1_D8                36
69 #define CLK_TOP_APLL2                   37
70 #define CLK_TOP_APLL2_D2                38
71 #define CLK_TOP_APLL2_D4                39
72 #define CLK_TOP_APLL2_D8                40
73 #define CLK_TOP_CLK26M                  41
74 #define CLK_TOP_CLK26M_D2               42
75 #define CLK_TOP_AHB_INFRA_D2            43
76 #define CLK_TOP_NFI1X                   44
77 #define CLK_TOP_ETH_D2                  45
78 #define CLK_TOP_THEM                    46
79 #define CLK_TOP_APDMA                   47
80 #define CLK_TOP_I2C0                    48
81 #define CLK_TOP_I2C1                    49
82 #define CLK_TOP_AUXADC1                 50
83 #define CLK_TOP_NFI                     51
84 #define CLK_TOP_NFIECC                  52
85 #define CLK_TOP_DEBUGSYS                53
86 #define CLK_TOP_PWM                     54
87 #define CLK_TOP_UART0                   55
88 #define CLK_TOP_UART1                   56
89 #define CLK_TOP_BTIF                    57
90 #define CLK_TOP_USB                     58
91 #define CLK_TOP_FLASHIF_26M             59
92 #define CLK_TOP_AUXADC2                 60
93 #define CLK_TOP_I2C2                    61
94 #define CLK_TOP_MSDC0                   62
95 #define CLK_TOP_MSDC1                   63
96 #define CLK_TOP_NFI2X                   64
97 #define CLK_TOP_PMICWRAP_AP             65
98 #define CLK_TOP_SEJ                     66
99 #define CLK_TOP_MEMSLP_DLYER            67
100 #define CLK_TOP_SPI                     68
101 #define CLK_TOP_APXGPT                  69
102 #define CLK_TOP_AUDIO                   70
103 #define CLK_TOP_PMICWRAP_MD             71
104 #define CLK_TOP_PMICWRAP_CONN           72
105 #define CLK_TOP_PMICWRAP_26M            73
106 #define CLK_TOP_AUX_ADC                 74
107 #define CLK_TOP_AUX_TP                  75
108 #define CLK_TOP_MSDC2                   76
109 #define CLK_TOP_RBIST                   77
110 #define CLK_TOP_NFI_BUS                 78
111 #define CLK_TOP_GCE                     79
112 #define CLK_TOP_TRNG                    80
113 #define CLK_TOP_SEJ_13M                 81
114 #define CLK_TOP_AES                     82
115 #define CLK_TOP_PWM_B                   83
116 #define CLK_TOP_PWM1_FB                 84
117 #define CLK_TOP_PWM2_FB                 85
118 #define CLK_TOP_PWM3_FB                 86
119 #define CLK_TOP_PWM4_FB                 87
120 #define CLK_TOP_PWM5_FB                 88
121 #define CLK_TOP_USB_1P                  89
122 #define CLK_TOP_FLASHIF_FREERUN         90
123 #define CLK_TOP_66M_ETH                 91
124 #define CLK_TOP_133M_ETH                92
125 #define CLK_TOP_FETH_25M                93
126 #define CLK_TOP_FETH_50M                94
127 #define CLK_TOP_FLASHIF_AXI             95
128 #define CLK_TOP_USBIF                   96
129 #define CLK_TOP_UART2                   97
130 #define CLK_TOP_BSI                     98
131 #define CLK_TOP_RG_SPINOR               99
132 #define CLK_TOP_RG_MSDC2                100
133 #define CLK_TOP_RG_ETH                  101
134 #define CLK_TOP_RG_AUD1                 102
135 #define CLK_TOP_RG_AUD2                 103
136 #define CLK_TOP_RG_AUD_ENGEN1           104
137 #define CLK_TOP_RG_AUD_ENGEN2           105
138 #define CLK_TOP_RG_I2C                  106
139 #define CLK_TOP_RG_PWM_INFRA            107
140 #define CLK_TOP_RG_AUD_SPDIF_IN         108
141 #define CLK_TOP_RG_UART2                109
142 #define CLK_TOP_RG_BSI                  110
143 #define CLK_TOP_RG_DBG_ATCLK            111
144 #define CLK_TOP_RG_NFIECC               112
145 #define CLK_TOP_RG_APLL1_D2_EN          113
146 #define CLK_TOP_RG_APLL1_D4_EN          114
147 #define CLK_TOP_RG_APLL1_D8_EN          115
148 #define CLK_TOP_RG_APLL2_D2_EN          116
149 #define CLK_TOP_RG_APLL2_D4_EN          117
150 #define CLK_TOP_RG_APLL2_D8_EN          118
151 #define CLK_TOP_APLL12_DIV0             119
152 #define CLK_TOP_APLL12_DIV1             120
153 #define CLK_TOP_APLL12_DIV2             121
154 #define CLK_TOP_APLL12_DIV3             122
155 #define CLK_TOP_APLL12_DIV4             123
156 #define CLK_TOP_APLL12_DIV4B            124
157 #define CLK_TOP_APLL12_DIV5             125
158 #define CLK_TOP_APLL12_DIV5B            126
159 #define CLK_TOP_APLL12_DIV6             127
160 #define CLK_TOP_UART0_SEL               128
161 #define CLK_TOP_EMI_DDRPHY_SEL          129
162 #define CLK_TOP_AHB_INFRA_SEL           130
163 #define CLK_TOP_MSDC0_SEL               131
164 #define CLK_TOP_UART1_SEL               132
165 #define CLK_TOP_MSDC1_SEL               133
166 #define CLK_TOP_PMICSPI_SEL             134
167 #define CLK_TOP_QAXI_AUD26M_SEL         135
168 #define CLK_TOP_AUD_INTBUS_SEL          136
169 #define CLK_TOP_NFI2X_PAD_SEL           137
170 #define CLK_TOP_NFI1X_PAD_SEL           138
171 #define CLK_TOP_DDRPHYCFG_SEL           139
172 #define CLK_TOP_USB_78M_SEL             140
173 #define CLK_TOP_SPINOR_SEL              141
174 #define CLK_TOP_MSDC2_SEL               142
175 #define CLK_TOP_ETH_SEL                 143
176 #define CLK_TOP_AUD1_SEL                144
177 #define CLK_TOP_AUD2_SEL                145
178 #define CLK_TOP_AUD_ENGEN1_SEL          146
179 #define CLK_TOP_AUD_ENGEN2_SEL          147
180 #define CLK_TOP_I2C_SEL                 148
181 #define CLK_TOP_AUD_I2S0_M_SEL          149
182 #define CLK_TOP_AUD_I2S1_M_SEL          150
183 #define CLK_TOP_AUD_I2S2_M_SEL          151
184 #define CLK_TOP_AUD_I2S3_M_SEL          152
185 #define CLK_TOP_AUD_I2S4_M_SEL          153
186 #define CLK_TOP_AUD_I2S5_M_SEL          154
187 #define CLK_TOP_AUD_SPDIF_B_SEL         155
188 #define CLK_TOP_PWM_SEL                 156
189 #define CLK_TOP_SPI_SEL                 157
190 #define CLK_TOP_AUD_SPDIFIN_SEL         158
191 #define CLK_TOP_UART2_SEL               159
192 #define CLK_TOP_BSI_SEL                 160
193 #define CLK_TOP_DBG_ATCLK_SEL           161
194 #define CLK_TOP_CSW_NFIECC_SEL          162
195 #define CLK_TOP_NFIECC_SEL              163
196 #define CLK_TOP_APLL12_CK_DIV0          164
197 #define CLK_TOP_APLL12_CK_DIV1          165
198 #define CLK_TOP_APLL12_CK_DIV2          166
199 #define CLK_TOP_APLL12_CK_DIV3          167
200 #define CLK_TOP_APLL12_CK_DIV4          168
201 #define CLK_TOP_APLL12_CK_DIV4B         169
202 #define CLK_TOP_APLL12_CK_DIV5          170
203 #define CLK_TOP_APLL12_CK_DIV5B         171
204 #define CLK_TOP_APLL12_CK_DIV6          172
205 #define CLK_TOP_USB_78M                 173
206 #define CLK_TOP_MSDC0_INFRA             174
207 #define CLK_TOP_MSDC1_INFRA             175
208 #define CLK_TOP_MSDC2_INFRA             176
209 #define CLK_TOP_NR_CLK                  177
210
211 /* AUDSYS */
212
213 #define CLK_AUD_AFE                     0
214 #define CLK_AUD_I2S                     1
215 #define CLK_AUD_22M                     2
216 #define CLK_AUD_24M                     3
217 #define CLK_AUD_INTDIR                  4
218 #define CLK_AUD_APLL2_TUNER             5
219 #define CLK_AUD_APLL_TUNER              6
220 #define CLK_AUD_HDMI                    7
221 #define CLK_AUD_SPDF                    8
222 #define CLK_AUD_ADC                     9
223 #define CLK_AUD_DAC                     10
224 #define CLK_AUD_DAC_PREDIS              11
225 #define CLK_AUD_TML                     12
226 #define CLK_AUD_NR_CLK                  13
227
228 #endif /* _DT_BINDINGS_CLK_MT8516_H */