GNU Linux-libre 6.9.1-gnu
[releases.git] / include / dt-bindings / clock / mt8186-clk.h
1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /*
3  * Copyright (c) 2022 MediaTek Inc.
4  * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
5  */
6
7 #ifndef _DT_BINDINGS_CLK_MT8186_H
8 #define _DT_BINDINGS_CLK_MT8186_H
9
10 /* MCUSYS */
11
12 #define CLK_MCU_ARMPLL_LL_SEL           0
13 #define CLK_MCU_ARMPLL_BL_SEL           1
14 #define CLK_MCU_ARMPLL_BUS_SEL          2
15 #define CLK_MCU_NR_CLK                  3
16
17 /* TOPCKGEN */
18
19 #define CLK_TOP_AXI                     0
20 #define CLK_TOP_SCP                     1
21 #define CLK_TOP_MFG                     2
22 #define CLK_TOP_CAMTG                   3
23 #define CLK_TOP_CAMTG1                  4
24 #define CLK_TOP_CAMTG2                  5
25 #define CLK_TOP_CAMTG3                  6
26 #define CLK_TOP_CAMTG4                  7
27 #define CLK_TOP_CAMTG5                  8
28 #define CLK_TOP_CAMTG6                  9
29 #define CLK_TOP_UART                    10
30 #define CLK_TOP_SPI                     11
31 #define CLK_TOP_MSDC50_0_HCLK           12
32 #define CLK_TOP_MSDC50_0                13
33 #define CLK_TOP_MSDC30_1                14
34 #define CLK_TOP_AUDIO                   15
35 #define CLK_TOP_AUD_INTBUS              16
36 #define CLK_TOP_AUD_1                   17
37 #define CLK_TOP_AUD_2                   18
38 #define CLK_TOP_AUD_ENGEN1              19
39 #define CLK_TOP_AUD_ENGEN2              20
40 #define CLK_TOP_DISP_PWM                21
41 #define CLK_TOP_SSPM                    22
42 #define CLK_TOP_DXCC                    23
43 #define CLK_TOP_USB_TOP                 24
44 #define CLK_TOP_SRCK                    25
45 #define CLK_TOP_SPM                     26
46 #define CLK_TOP_I2C                     27
47 #define CLK_TOP_PWM                     28
48 #define CLK_TOP_SENINF                  29
49 #define CLK_TOP_SENINF1                 30
50 #define CLK_TOP_SENINF2                 31
51 #define CLK_TOP_SENINF3                 32
52 #define CLK_TOP_AES_MSDCFDE             33
53 #define CLK_TOP_PWRAP_ULPOSC            34
54 #define CLK_TOP_CAMTM                   35
55 #define CLK_TOP_VENC                    36
56 #define CLK_TOP_CAM                     37
57 #define CLK_TOP_IMG1                    38
58 #define CLK_TOP_IPE                     39
59 #define CLK_TOP_DPMAIF                  40
60 #define CLK_TOP_VDEC                    41
61 #define CLK_TOP_DISP                    42
62 #define CLK_TOP_MDP                     43
63 #define CLK_TOP_AUDIO_H                 44
64 #define CLK_TOP_UFS                     45
65 #define CLK_TOP_AES_FDE                 46
66 #define CLK_TOP_AUDIODSP                47
67 #define CLK_TOP_DVFSRC                  48
68 #define CLK_TOP_DSI_OCC                 49
69 #define CLK_TOP_SPMI_MST                50
70 #define CLK_TOP_SPINOR                  51
71 #define CLK_TOP_NNA                     52
72 #define CLK_TOP_NNA1                    53
73 #define CLK_TOP_NNA2                    54
74 #define CLK_TOP_SSUSB_XHCI              55
75 #define CLK_TOP_SSUSB_TOP_1P            56
76 #define CLK_TOP_SSUSB_XHCI_1P           57
77 #define CLK_TOP_WPE                     58
78 #define CLK_TOP_DPI                     59
79 #define CLK_TOP_U3_OCC_250M             60
80 #define CLK_TOP_U3_OCC_500M             61
81 #define CLK_TOP_ADSP_BUS                62
82 #define CLK_TOP_APLL_I2S0_MCK_SEL       63
83 #define CLK_TOP_APLL_I2S1_MCK_SEL       64
84 #define CLK_TOP_APLL_I2S2_MCK_SEL       65
85 #define CLK_TOP_APLL_I2S4_MCK_SEL       66
86 #define CLK_TOP_APLL_TDMOUT_MCK_SEL     67
87 #define CLK_TOP_MAINPLL_D2              68
88 #define CLK_TOP_MAINPLL_D2_D2           69
89 #define CLK_TOP_MAINPLL_D2_D4           70
90 #define CLK_TOP_MAINPLL_D2_D16          71
91 #define CLK_TOP_MAINPLL_D3              72
92 #define CLK_TOP_MAINPLL_D3_D2           73
93 #define CLK_TOP_MAINPLL_D3_D4           74
94 #define CLK_TOP_MAINPLL_D5              75
95 #define CLK_TOP_MAINPLL_D5_D2           76
96 #define CLK_TOP_MAINPLL_D5_D4           77
97 #define CLK_TOP_MAINPLL_D7              78
98 #define CLK_TOP_MAINPLL_D7_D2           79
99 #define CLK_TOP_MAINPLL_D7_D4           80
100 #define CLK_TOP_UNIVPLL                 81
101 #define CLK_TOP_UNIVPLL_D2              82
102 #define CLK_TOP_UNIVPLL_D2_D2           83
103 #define CLK_TOP_UNIVPLL_D2_D4           84
104 #define CLK_TOP_UNIVPLL_D3              85
105 #define CLK_TOP_UNIVPLL_D3_D2           86
106 #define CLK_TOP_UNIVPLL_D3_D4           87
107 #define CLK_TOP_UNIVPLL_D3_D8           88
108 #define CLK_TOP_UNIVPLL_D3_D32          89
109 #define CLK_TOP_UNIVPLL_D5              90
110 #define CLK_TOP_UNIVPLL_D5_D2           91
111 #define CLK_TOP_UNIVPLL_D5_D4           92
112 #define CLK_TOP_UNIVPLL_D7              93
113 #define CLK_TOP_UNIVPLL_192M            94
114 #define CLK_TOP_UNIVPLL_192M_D4         95
115 #define CLK_TOP_UNIVPLL_192M_D8         96
116 #define CLK_TOP_UNIVPLL_192M_D16        97
117 #define CLK_TOP_UNIVPLL_192M_D32        98
118 #define CLK_TOP_APLL1_D2                99
119 #define CLK_TOP_APLL1_D4                100
120 #define CLK_TOP_APLL1_D8                101
121 #define CLK_TOP_APLL2_D2                102
122 #define CLK_TOP_APLL2_D4                103
123 #define CLK_TOP_APLL2_D8                104
124 #define CLK_TOP_MMPLL_D2                105
125 #define CLK_TOP_TVDPLL_D2               106
126 #define CLK_TOP_TVDPLL_D4               107
127 #define CLK_TOP_TVDPLL_D8               108
128 #define CLK_TOP_TVDPLL_D16              109
129 #define CLK_TOP_TVDPLL_D32              110
130 #define CLK_TOP_MSDCPLL_D2              111
131 #define CLK_TOP_ULPOSC1                 112
132 #define CLK_TOP_ULPOSC1_D2              113
133 #define CLK_TOP_ULPOSC1_D4              114
134 #define CLK_TOP_ULPOSC1_D8              115
135 #define CLK_TOP_ULPOSC1_D10             116
136 #define CLK_TOP_ULPOSC1_D16             117
137 #define CLK_TOP_ULPOSC1_D32             118
138 #define CLK_TOP_ADSPPLL_D2              119
139 #define CLK_TOP_ADSPPLL_D4              120
140 #define CLK_TOP_ADSPPLL_D8              121
141 #define CLK_TOP_NNAPLL_D2               122
142 #define CLK_TOP_NNAPLL_D4               123
143 #define CLK_TOP_NNAPLL_D8               124
144 #define CLK_TOP_NNA2PLL_D2              125
145 #define CLK_TOP_NNA2PLL_D4              126
146 #define CLK_TOP_NNA2PLL_D8              127
147 #define CLK_TOP_F_BIST2FPC              128
148 #define CLK_TOP_466M_FMEM               129
149 #define CLK_TOP_MPLL                    130
150 #define CLK_TOP_APLL12_CK_DIV0          131
151 #define CLK_TOP_APLL12_CK_DIV1          132
152 #define CLK_TOP_APLL12_CK_DIV2          133
153 #define CLK_TOP_APLL12_CK_DIV4          134
154 #define CLK_TOP_APLL12_CK_DIV_TDMOUT_M  135
155 #define CLK_TOP_NR_CLK                  136
156
157 /* INFRACFG_AO */
158
159 #define CLK_INFRA_AO_PMIC_TMR           0
160 #define CLK_INFRA_AO_PMIC_AP            1
161 #define CLK_INFRA_AO_PMIC_MD            2
162 #define CLK_INFRA_AO_PMIC_CONN          3
163 #define CLK_INFRA_AO_SCP_CORE           4
164 #define CLK_INFRA_AO_SEJ                5
165 #define CLK_INFRA_AO_APXGPT             6
166 #define CLK_INFRA_AO_ICUSB              7
167 #define CLK_INFRA_AO_GCE                8
168 #define CLK_INFRA_AO_THERM              9
169 #define CLK_INFRA_AO_I2C_AP             10
170 #define CLK_INFRA_AO_I2C_CCU            11
171 #define CLK_INFRA_AO_I2C_SSPM           12
172 #define CLK_INFRA_AO_I2C_RSV            13
173 #define CLK_INFRA_AO_PWM_HCLK           14
174 #define CLK_INFRA_AO_PWM1               15
175 #define CLK_INFRA_AO_PWM2               16
176 #define CLK_INFRA_AO_PWM3               17
177 #define CLK_INFRA_AO_PWM4               18
178 #define CLK_INFRA_AO_PWM5               19
179 #define CLK_INFRA_AO_PWM                20
180 #define CLK_INFRA_AO_UART0              21
181 #define CLK_INFRA_AO_UART1              22
182 #define CLK_INFRA_AO_UART2              23
183 #define CLK_INFRA_AO_GCE_26M            24
184 #define CLK_INFRA_AO_CQ_DMA_FPC         25
185 #define CLK_INFRA_AO_BTIF               26
186 #define CLK_INFRA_AO_SPI0               27
187 #define CLK_INFRA_AO_MSDC0              28
188 #define CLK_INFRA_AO_MSDCFDE            29
189 #define CLK_INFRA_AO_MSDC1              30
190 #define CLK_INFRA_AO_DVFSRC             31
191 #define CLK_INFRA_AO_GCPU               32
192 #define CLK_INFRA_AO_TRNG               33
193 #define CLK_INFRA_AO_AUXADC             34
194 #define CLK_INFRA_AO_CPUM               35
195 #define CLK_INFRA_AO_CCIF1_AP           36
196 #define CLK_INFRA_AO_CCIF1_MD           37
197 #define CLK_INFRA_AO_AUXADC_MD          38
198 #define CLK_INFRA_AO_AP_DMA             39
199 #define CLK_INFRA_AO_XIU                40
200 #define CLK_INFRA_AO_DEVICE_APC         41
201 #define CLK_INFRA_AO_CCIF_AP            42
202 #define CLK_INFRA_AO_DEBUGTOP           43
203 #define CLK_INFRA_AO_AUDIO              44
204 #define CLK_INFRA_AO_CCIF_MD            45
205 #define CLK_INFRA_AO_DXCC_SEC_CORE      46
206 #define CLK_INFRA_AO_DXCC_AO            47
207 #define CLK_INFRA_AO_IMP_IIC            48
208 #define CLK_INFRA_AO_DRAMC_F26M         49
209 #define CLK_INFRA_AO_RG_PWM_FBCLK6      50
210 #define CLK_INFRA_AO_SSUSB_TOP_HCLK     51
211 #define CLK_INFRA_AO_DISP_PWM           52
212 #define CLK_INFRA_AO_CLDMA_BCLK         53
213 #define CLK_INFRA_AO_AUDIO_26M_BCLK     54
214 #define CLK_INFRA_AO_SSUSB_TOP_P1_HCLK  55
215 #define CLK_INFRA_AO_SPI1               56
216 #define CLK_INFRA_AO_I2C4               57
217 #define CLK_INFRA_AO_MODEM_TEMP_SHARE   58
218 #define CLK_INFRA_AO_SPI2               59
219 #define CLK_INFRA_AO_SPI3               60
220 #define CLK_INFRA_AO_SSUSB_TOP_REF      61
221 #define CLK_INFRA_AO_SSUSB_TOP_XHCI     62
222 #define CLK_INFRA_AO_SSUSB_TOP_P1_REF   63
223 #define CLK_INFRA_AO_SSUSB_TOP_P1_XHCI  64
224 #define CLK_INFRA_AO_SSPM               65
225 #define CLK_INFRA_AO_SSUSB_TOP_P1_SYS   66
226 #define CLK_INFRA_AO_I2C5               67
227 #define CLK_INFRA_AO_I2C5_ARBITER       68
228 #define CLK_INFRA_AO_I2C5_IMM           69
229 #define CLK_INFRA_AO_I2C1_ARBITER       70
230 #define CLK_INFRA_AO_I2C1_IMM           71
231 #define CLK_INFRA_AO_I2C2_ARBITER       72
232 #define CLK_INFRA_AO_I2C2_IMM           73
233 #define CLK_INFRA_AO_SPI4               74
234 #define CLK_INFRA_AO_SPI5               75
235 #define CLK_INFRA_AO_CQ_DMA             76
236 #define CLK_INFRA_AO_BIST2FPC           77
237 #define CLK_INFRA_AO_MSDC0_SELF         78
238 #define CLK_INFRA_AO_SPINOR             79
239 #define CLK_INFRA_AO_SSPM_26M_SELF      80
240 #define CLK_INFRA_AO_SSPM_32K_SELF      81
241 #define CLK_INFRA_AO_I2C6               82
242 #define CLK_INFRA_AO_AP_MSDC0           83
243 #define CLK_INFRA_AO_MD_MSDC0           84
244 #define CLK_INFRA_AO_MSDC0_SRC          85
245 #define CLK_INFRA_AO_MSDC1_SRC          86
246 #define CLK_INFRA_AO_SEJ_F13M           87
247 #define CLK_INFRA_AO_AES_TOP0_BCLK      88
248 #define CLK_INFRA_AO_MCU_PM_BCLK        89
249 #define CLK_INFRA_AO_CCIF2_AP           90
250 #define CLK_INFRA_AO_CCIF2_MD           91
251 #define CLK_INFRA_AO_CCIF3_AP           92
252 #define CLK_INFRA_AO_CCIF3_MD           93
253 #define CLK_INFRA_AO_FADSP_26M          94
254 #define CLK_INFRA_AO_FADSP_32K          95
255 #define CLK_INFRA_AO_CCIF4_AP           96
256 #define CLK_INFRA_AO_CCIF4_MD           97
257 #define CLK_INFRA_AO_FADSP              98
258 #define CLK_INFRA_AO_FLASHIF_133M       99
259 #define CLK_INFRA_AO_FLASHIF_66M        100
260 #define CLK_INFRA_AO_NR_CLK             101
261
262 /* APMIXEDSYS */
263
264 #define CLK_APMIXED_ARMPLL_LL           0
265 #define CLK_APMIXED_ARMPLL_BL           1
266 #define CLK_APMIXED_CCIPLL              2
267 #define CLK_APMIXED_MAINPLL             3
268 #define CLK_APMIXED_UNIV2PLL            4
269 #define CLK_APMIXED_MSDCPLL             5
270 #define CLK_APMIXED_MMPLL               6
271 #define CLK_APMIXED_NNAPLL              7
272 #define CLK_APMIXED_NNA2PLL             8
273 #define CLK_APMIXED_ADSPPLL             9
274 #define CLK_APMIXED_MFGPLL              10
275 #define CLK_APMIXED_TVDPLL              11
276 #define CLK_APMIXED_APLL1               12
277 #define CLK_APMIXED_APLL2               13
278 #define CLK_APMIXED_NR_CLK              14
279
280 /* IMP_IIC_WRAP */
281
282 #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C0  0
283 #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C1  1
284 #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C2  2
285 #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C3  3
286 #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C4  4
287 #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C5  5
288 #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C6  6
289 #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C7  7
290 #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C8  8
291 #define CLK_IMP_IIC_WRAP_AP_CLOCK_I2C9  9
292 #define CLK_IMP_IIC_WRAP_NR_CLK         10
293
294 /* MFGCFG */
295
296 #define CLK_MFG_BG3D                    0
297 #define CLK_MFG_NR_CLK                  1
298
299 /* MMSYS */
300
301 #define CLK_MM_DISP_MUTEX0              0
302 #define CLK_MM_APB_MM_BUS               1
303 #define CLK_MM_DISP_OVL0                2
304 #define CLK_MM_DISP_RDMA0               3
305 #define CLK_MM_DISP_OVL0_2L             4
306 #define CLK_MM_DISP_WDMA0               5
307 #define CLK_MM_DISP_RSZ0                6
308 #define CLK_MM_DISP_AAL0                7
309 #define CLK_MM_DISP_CCORR0              8
310 #define CLK_MM_DISP_COLOR0              9
311 #define CLK_MM_SMI_INFRA                10
312 #define CLK_MM_DISP_DSC_WRAP0           11
313 #define CLK_MM_DISP_GAMMA0              12
314 #define CLK_MM_DISP_POSTMASK0           13
315 #define CLK_MM_DISP_DITHER0             14
316 #define CLK_MM_SMI_COMMON               15
317 #define CLK_MM_DSI0                     16
318 #define CLK_MM_DISP_FAKE_ENG0           17
319 #define CLK_MM_DISP_FAKE_ENG1           18
320 #define CLK_MM_SMI_GALS                 19
321 #define CLK_MM_SMI_IOMMU                20
322 #define CLK_MM_DISP_RDMA1               21
323 #define CLK_MM_DISP_DPI                 22
324 #define CLK_MM_DSI0_DSI_CK_DOMAIN       23
325 #define CLK_MM_DISP_26M                 24
326 #define CLK_MM_NR_CLK                   25
327
328 /* WPESYS */
329
330 #define CLK_WPE_CK_EN                   0
331 #define CLK_WPE_SMI_LARB8_CK_EN         1
332 #define CLK_WPE_SYS_EVENT_TX_CK_EN      2
333 #define CLK_WPE_SMI_LARB8_PCLK_EN       3
334 #define CLK_WPE_NR_CLK                  4
335
336 /* IMGSYS1 */
337
338 #define CLK_IMG1_LARB9_IMG1             0
339 #define CLK_IMG1_LARB10_IMG1            1
340 #define CLK_IMG1_DIP                    2
341 #define CLK_IMG1_GALS_IMG1              3
342 #define CLK_IMG1_NR_CLK                 4
343
344 /* IMGSYS2 */
345
346 #define CLK_IMG2_LARB9_IMG2             0
347 #define CLK_IMG2_LARB10_IMG2            1
348 #define CLK_IMG2_MFB                    2
349 #define CLK_IMG2_WPE                    3
350 #define CLK_IMG2_MSS                    4
351 #define CLK_IMG2_GALS_IMG2              5
352 #define CLK_IMG2_NR_CLK                 6
353
354 /* VDECSYS */
355
356 #define CLK_VDEC_LARB1_CKEN             0
357 #define CLK_VDEC_LAT_CKEN               1
358 #define CLK_VDEC_LAT_ACTIVE             2
359 #define CLK_VDEC_LAT_CKEN_ENG           3
360 #define CLK_VDEC_MINI_MDP_CKEN_CFG_RG   4
361 #define CLK_VDEC_CKEN                   5
362 #define CLK_VDEC_ACTIVE                 6
363 #define CLK_VDEC_CKEN_ENG               7
364 #define CLK_VDEC_NR_CLK                 8
365
366 /* VENCSYS */
367
368 #define CLK_VENC_CKE0_LARB              0
369 #define CLK_VENC_CKE1_VENC              1
370 #define CLK_VENC_CKE2_JPGENC            2
371 #define CLK_VENC_CKE5_GALS              3
372 #define CLK_VENC_NR_CLK                 4
373
374 /* CAMSYS */
375
376 #define CLK_CAM_LARB13                  0
377 #define CLK_CAM_DFP_VAD                 1
378 #define CLK_CAM_LARB14                  2
379 #define CLK_CAM                         3
380 #define CLK_CAMTG                       4
381 #define CLK_CAM_SENINF                  5
382 #define CLK_CAMSV1                      6
383 #define CLK_CAMSV2                      7
384 #define CLK_CAMSV3                      8
385 #define CLK_CAM_CCU0                    9
386 #define CLK_CAM_CCU1                    10
387 #define CLK_CAM_MRAW0                   11
388 #define CLK_CAM_FAKE_ENG                12
389 #define CLK_CAM_CCU_GALS                13
390 #define CLK_CAM2MM_GALS                 14
391 #define CLK_CAM_NR_CLK                  15
392
393 /* CAMSYS_RAWA */
394
395 #define CLK_CAM_RAWA_LARBX_RAWA         0
396 #define CLK_CAM_RAWA                    1
397 #define CLK_CAM_RAWA_CAMTG_RAWA         2
398 #define CLK_CAM_RAWA_NR_CLK             3
399
400 /* CAMSYS_RAWB */
401
402 #define CLK_CAM_RAWB_LARBX_RAWB         0
403 #define CLK_CAM_RAWB                    1
404 #define CLK_CAM_RAWB_CAMTG_RAWB         2
405 #define CLK_CAM_RAWB_NR_CLK             3
406
407 /* MDPSYS */
408
409 #define CLK_MDP_RDMA0                   0
410 #define CLK_MDP_TDSHP0                  1
411 #define CLK_MDP_IMG_DL_ASYNC0           2
412 #define CLK_MDP_IMG_DL_ASYNC1           3
413 #define CLK_MDP_DISP_RDMA               4
414 #define CLK_MDP_HMS                     5
415 #define CLK_MDP_SMI0                    6
416 #define CLK_MDP_APB_BUS                 7
417 #define CLK_MDP_WROT0                   8
418 #define CLK_MDP_RSZ0                    9
419 #define CLK_MDP_HDR0                    10
420 #define CLK_MDP_MUTEX0                  11
421 #define CLK_MDP_WROT1                   12
422 #define CLK_MDP_RSZ1                    13
423 #define CLK_MDP_FAKE_ENG0               14
424 #define CLK_MDP_AAL0                    15
425 #define CLK_MDP_DISP_WDMA               16
426 #define CLK_MDP_COLOR                   17
427 #define CLK_MDP_IMG_DL_ASYNC2           18
428 #define CLK_MDP_IMG_DL_RELAY0_ASYNC0    19
429 #define CLK_MDP_IMG_DL_RELAY1_ASYNC1    20
430 #define CLK_MDP_IMG_DL_RELAY2_ASYNC2    21
431 #define CLK_MDP_NR_CLK                  22
432
433 /* IPESYS */
434
435 #define CLK_IPE_LARB19                  0
436 #define CLK_IPE_LARB20                  1
437 #define CLK_IPE_SMI_SUBCOM              2
438 #define CLK_IPE_FD                      3
439 #define CLK_IPE_FE                      4
440 #define CLK_IPE_RSC                     5
441 #define CLK_IPE_DPE                     6
442 #define CLK_IPE_GALS_IPE                7
443 #define CLK_IPE_NR_CLK                  8
444
445 #endif /* _DT_BINDINGS_CLK_MT8186_H */