GNU Linux-libre 6.9.1-gnu
[releases.git] / include / dt-bindings / clock / mt7986-clk.h
1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2 /*
3  * Copyright (c) 2021 MediaTek Inc.
4  * Author: Sam Shih <sam.shih@mediatek.com>
5  */
6
7 #ifndef _DT_BINDINGS_CLK_MT7986_H
8 #define _DT_BINDINGS_CLK_MT7986_H
9
10 /* APMIXEDSYS */
11
12 #define CLK_APMIXED_ARMPLL              0
13 #define CLK_APMIXED_NET2PLL             1
14 #define CLK_APMIXED_MMPLL               2
15 #define CLK_APMIXED_SGMPLL              3
16 #define CLK_APMIXED_WEDMCUPLL           4
17 #define CLK_APMIXED_NET1PLL             5
18 #define CLK_APMIXED_MPLL                6
19 #define CLK_APMIXED_APLL2               7
20
21 /* TOPCKGEN */
22
23 #define CLK_TOP_XTAL                    0
24 #define CLK_TOP_XTAL_D2                 1
25 #define CLK_TOP_RTC_32K                 2
26 #define CLK_TOP_RTC_32P7K               3
27 #define CLK_TOP_MPLL_D2                 4
28 #define CLK_TOP_MPLL_D4                 5
29 #define CLK_TOP_MPLL_D8                 6
30 #define CLK_TOP_MPLL_D8_D2              7
31 #define CLK_TOP_MPLL_D3_D2              8
32 #define CLK_TOP_MMPLL_D2                9
33 #define CLK_TOP_MMPLL_D4                10
34 #define CLK_TOP_MMPLL_D8                11
35 #define CLK_TOP_MMPLL_D8_D2             12
36 #define CLK_TOP_MMPLL_D3_D8             13
37 #define CLK_TOP_MMPLL_U2PHY             14
38 #define CLK_TOP_APLL2_D4                15
39 #define CLK_TOP_NET1PLL_D4              16
40 #define CLK_TOP_NET1PLL_D5              17
41 #define CLK_TOP_NET1PLL_D5_D2           18
42 #define CLK_TOP_NET1PLL_D5_D4           19
43 #define CLK_TOP_NET1PLL_D8_D2           20
44 #define CLK_TOP_NET1PLL_D8_D4           21
45 #define CLK_TOP_NET2PLL_D4              22
46 #define CLK_TOP_NET2PLL_D4_D2           23
47 #define CLK_TOP_NET2PLL_D3_D2           24
48 #define CLK_TOP_WEDMCUPLL_D5_D2         25
49 #define CLK_TOP_NFI1X_SEL               26
50 #define CLK_TOP_SPINFI_SEL              27
51 #define CLK_TOP_SPI_SEL                 28
52 #define CLK_TOP_SPIM_MST_SEL            29
53 #define CLK_TOP_UART_SEL                30
54 #define CLK_TOP_PWM_SEL                 31
55 #define CLK_TOP_I2C_SEL                 32
56 #define CLK_TOP_PEXTP_TL_SEL            33
57 #define CLK_TOP_EMMC_250M_SEL           34
58 #define CLK_TOP_EMMC_416M_SEL           35
59 #define CLK_TOP_F_26M_ADC_SEL           36
60 #define CLK_TOP_DRAMC_SEL               37
61 #define CLK_TOP_DRAMC_MD32_SEL          38
62 #define CLK_TOP_SYSAXI_SEL              39
63 #define CLK_TOP_SYSAPB_SEL              40
64 #define CLK_TOP_ARM_DB_MAIN_SEL         41
65 #define CLK_TOP_ARM_DB_JTSEL            42
66 #define CLK_TOP_NETSYS_SEL              43
67 #define CLK_TOP_NETSYS_500M_SEL         44
68 #define CLK_TOP_NETSYS_MCU_SEL          45
69 #define CLK_TOP_NETSYS_2X_SEL           46
70 #define CLK_TOP_SGM_325M_SEL            47
71 #define CLK_TOP_SGM_REG_SEL             48
72 #define CLK_TOP_A1SYS_SEL               49
73 #define CLK_TOP_CONN_MCUSYS_SEL         50
74 #define CLK_TOP_EIP_B_SEL               51
75 #define CLK_TOP_PCIE_PHY_SEL            52
76 #define CLK_TOP_USB3_PHY_SEL            53
77 #define CLK_TOP_F26M_SEL                54
78 #define CLK_TOP_AUD_L_SEL               55
79 #define CLK_TOP_A_TUNER_SEL             56
80 #define CLK_TOP_U2U3_SEL                57
81 #define CLK_TOP_U2U3_SYS_SEL            58
82 #define CLK_TOP_U2U3_XHCI_SEL           59
83 #define CLK_TOP_DA_U2_REFSEL            60
84 #define CLK_TOP_DA_U2_CK_1P_SEL         61
85 #define CLK_TOP_AP2CNN_HOST_SEL         62
86 #define CLK_TOP_JTAG                    63
87
88 /* INFRACFG */
89
90 #define CLK_INFRA_SYSAXI_D2             0
91 #define CLK_INFRA_UART0_SEL             1
92 #define CLK_INFRA_UART1_SEL             2
93 #define CLK_INFRA_UART2_SEL             3
94 #define CLK_INFRA_SPI0_SEL              4
95 #define CLK_INFRA_SPI1_SEL              5
96 #define CLK_INFRA_PWM1_SEL              6
97 #define CLK_INFRA_PWM2_SEL              7
98 #define CLK_INFRA_PWM_BSEL              8
99 #define CLK_INFRA_PCIE_SEL              9
100 #define CLK_INFRA_GPT_STA               10
101 #define CLK_INFRA_PWM_HCK               11
102 #define CLK_INFRA_PWM_STA               12
103 #define CLK_INFRA_PWM1_CK               13
104 #define CLK_INFRA_PWM2_CK               14
105 #define CLK_INFRA_CQ_DMA_CK             15
106 #define CLK_INFRA_EIP97_CK              16
107 #define CLK_INFRA_AUD_BUS_CK            17
108 #define CLK_INFRA_AUD_26M_CK            18
109 #define CLK_INFRA_AUD_L_CK              19
110 #define CLK_INFRA_AUD_AUD_CK            20
111 #define CLK_INFRA_AUD_EG2_CK            21
112 #define CLK_INFRA_DRAMC_26M_CK          22
113 #define CLK_INFRA_DBG_CK                23
114 #define CLK_INFRA_AP_DMA_CK             24
115 #define CLK_INFRA_SEJ_CK                25
116 #define CLK_INFRA_SEJ_13M_CK            26
117 #define CLK_INFRA_THERM_CK              27
118 #define CLK_INFRA_I2C0_CK               28
119 #define CLK_INFRA_UART0_CK              29
120 #define CLK_INFRA_UART1_CK              30
121 #define CLK_INFRA_UART2_CK              31
122 #define CLK_INFRA_NFI1_CK               32
123 #define CLK_INFRA_SPINFI1_CK            33
124 #define CLK_INFRA_NFI_HCK_CK            34
125 #define CLK_INFRA_SPI0_CK               35
126 #define CLK_INFRA_SPI1_CK               36
127 #define CLK_INFRA_SPI0_HCK_CK           37
128 #define CLK_INFRA_SPI1_HCK_CK           38
129 #define CLK_INFRA_FRTC_CK               39
130 #define CLK_INFRA_MSDC_CK               40
131 #define CLK_INFRA_MSDC_HCK_CK           41
132 #define CLK_INFRA_MSDC_133M_CK          42
133 #define CLK_INFRA_MSDC_66M_CK           43
134 #define CLK_INFRA_ADC_26M_CK            44
135 #define CLK_INFRA_ADC_FRC_CK            45
136 #define CLK_INFRA_FBIST2FPC_CK          46
137 #define CLK_INFRA_IUSB_133_CK           47
138 #define CLK_INFRA_IUSB_66M_CK           48
139 #define CLK_INFRA_IUSB_SYS_CK           49
140 #define CLK_INFRA_IUSB_CK               50
141 #define CLK_INFRA_IPCIE_CK              51
142 #define CLK_INFRA_IPCIE_PIPE_CK         52
143 #define CLK_INFRA_IPCIER_CK             53
144 #define CLK_INFRA_IPCIEB_CK             54
145 #define CLK_INFRA_TRNG_CK               55
146
147 /* SGMIISYS_0 */
148
149 #define CLK_SGMII0_TX250M_EN            0
150 #define CLK_SGMII0_RX250M_EN            1
151 #define CLK_SGMII0_CDR_REF              2
152 #define CLK_SGMII0_CDR_FB               3
153
154 /* SGMIISYS_1 */
155
156 #define CLK_SGMII1_TX250M_EN            0
157 #define CLK_SGMII1_RX250M_EN            1
158 #define CLK_SGMII1_CDR_REF              2
159 #define CLK_SGMII1_CDR_FB               3
160
161 /* ETHSYS */
162
163 #define CLK_ETH_FE_EN                   0
164 #define CLK_ETH_GP2_EN                  1
165 #define CLK_ETH_GP1_EN                  2
166 #define CLK_ETH_WOCPU1_EN               3
167 #define CLK_ETH_WOCPU0_EN               4
168
169 #endif /* _DT_BINDINGS_CLK_MT7986_H */