1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
3 * Daire McNamara,<daire.mcnamara@microchip.com>
4 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
7 #ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
8 #define _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
21 #define CLK_MMUART2 10
22 #define CLK_MMUART3 11
23 #define CLK_MMUART4 12
31 #define CLK_RESERVED 20
48 /* Clock Conditioning Circuitry Clock IDs */
50 #define CLK_CCC_PLL0 0
51 #define CLK_CCC_PLL1 1
52 #define CLK_CCC_DLL0 2
53 #define CLK_CCC_DLL1 3
55 #define CLK_CCC_PLL0_OUT0 4
56 #define CLK_CCC_PLL0_OUT1 5
57 #define CLK_CCC_PLL0_OUT2 6
58 #define CLK_CCC_PLL0_OUT3 7
60 #define CLK_CCC_PLL1_OUT0 8
61 #define CLK_CCC_PLL1_OUT1 9
62 #define CLK_CCC_PLL1_OUT2 10
63 #define CLK_CCC_PLL1_OUT3 11
65 #define CLK_CCC_DLL0_OUT0 12
66 #define CLK_CCC_DLL0_OUT1 13
68 #define CLK_CCC_DLL1_OUT0 14
69 #define CLK_CCC_DLL1_OUT1 15
71 #endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */