1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Meson8b clock tree IDs
6 #ifndef __MESON8B_CLKC_H
7 #define __MESON8B_CLKC_H
9 #define CLKID_PLL_FIXED 2
10 #define CLKID_PLL_VID 3
11 #define CLKID_PLL_SYS 4
12 #define CLKID_FCLK_DIV2 5
13 #define CLKID_FCLK_DIV3 6
14 #define CLKID_FCLK_DIV4 7
15 #define CLKID_FCLK_DIV5 8
16 #define CLKID_FCLK_DIV7 9
17 #define CLKID_CLK81 10
19 #define CLKID_CPUCLK 12
21 #define CLKID_MPEG_SEL 14
22 #define CLKID_MPEG_DIV 15
26 #define CLKID_PL301 19
27 #define CLKID_PERIPHS 20
28 #define CLKID_SPICC 21
30 #define CLKID_SAR_ADC 23
31 #define CLKID_SMART_CARD 24
33 #define CLKID_UART0 26
35 #define CLKID_STREAM 28
36 #define CLKID_ASYNC_FIFO 29
39 #define CLKID_HIU_IFACE 32
40 #define CLKID_ASSIST_MISC 33
42 #define CLKID_I2S_SPDIF 35
44 #define CLKID_DEMUX 37
45 #define CLKID_AIU_GLUE 38
46 #define CLKID_IEC958 39
47 #define CLKID_I2S_OUT 40
48 #define CLKID_AMCLK 41
49 #define CLKID_AIFIFO2 42
50 #define CLKID_MIXER 43
51 #define CLKID_MIXER_IFACE 44
53 #define CLKID_BLKMV 46
55 #define CLKID_UART1 48
59 #define CLKID_RESET 52
61 #define CLKID_DOS_PARSER 54
63 #define CLKID_VDIN1 56
64 #define CLKID_AHB_ARB0 57
65 #define CLKID_EFUSE 58
66 #define CLKID_BOOT_ROM 59
67 #define CLKID_AHB_DATA_BUS 60
68 #define CLKID_AHB_CTRL_BUS 61
69 #define CLKID_HDMI_INTR_SYNC 62
70 #define CLKID_HDMI_PCLK 63
71 #define CLKID_USB1_DDR_BRIDGE 64
72 #define CLKID_USB0_DDR_BRIDGE 65
73 #define CLKID_MMC_PCLK 66
75 #define CLKID_UART2 68
77 #define CLKID_VPU_INTR 70
78 #define CLKID_SEC_AHB_AHB3_BRIDGE 71
79 #define CLKID_CLK81_A9 72
80 #define CLKID_VCLK2_VENCI0 73
81 #define CLKID_VCLK2_VENCI1 74
82 #define CLKID_VCLK2_VENCP0 75
83 #define CLKID_VCLK2_VENCP1 76
84 #define CLKID_GCLK_VENCI_INT 77
85 #define CLKID_GCLK_VENCP_INT 78
86 #define CLKID_DAC_CLK 79
87 #define CLKID_AOCLK_GATE 80
88 #define CLKID_IEC958_GATE 81
89 #define CLKID_ENC480P 82
91 #define CLKID_GCLK_VENCL_INT 84
92 #define CLKID_VCLK2_VENCLMCC 85
93 #define CLKID_VCLK2_VENCL 86
94 #define CLKID_VCLK2_OTHER 87
96 #define CLKID_AO_MEDIA_CPU 89
97 #define CLKID_AO_AHB_SRAM 90
98 #define CLKID_AO_AHB_BUS 91
99 #define CLKID_AO_IFACE 92
100 #define CLKID_MPLL0 93
101 #define CLKID_MPLL1 94
102 #define CLKID_MPLL2 95
103 #define CLKID_NAND_CLK 112
104 #define CLKID_APB 124
105 #define CLKID_PERIPH 126
106 #define CLKID_AXI 128
107 #define CLKID_L2_DRAM 130
108 #define CLKID_HDMI_PLL_HDMI_OUT 132
109 #define CLKID_VID_PLL_FINAL_DIV 137
110 #define CLKID_VCLK_IN_SEL 138
111 #define CLKID_VCLK2_IN_SEL 149
112 #define CLKID_CTS_ENCT 161
113 #define CLKID_CTS_ENCP 163
114 #define CLKID_CTS_ENCI 165
115 #define CLKID_HDMI_TX_PIXEL 167
116 #define CLKID_CTS_ENCL 169
117 #define CLKID_CTS_VDAC0 171
118 #define CLKID_HDMI_SYS 174
119 #define CLKID_VPU 190
120 #define CLKID_VDEC_1 196
121 #define CLKID_VDEC_HCODEC 199
122 #define CLKID_VDEC_2 202
123 #define CLKID_VDEC_HEVC 206
124 #define CLKID_CTS_AMCLK 209
125 #define CLKID_CTS_MCLK_I958 212
126 #define CLKID_CTS_I958 213
128 #endif /* __MESON8B_CLKC_H */