include/dt-bindings/clock/mediatek,mt8188-clk.h

   1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */
   2 /*
   3  * Copyright (c) 2022 MediaTek Inc.
   4  * Author: Garmin Chang <garmin.chang@mediatek.com>
   5  */
   6
   7 #ifndef _DT_BINDINGS_CLK_MT8188_H
   8 #define _DT_BINDINGS_CLK_MT8188_H
   9
  10 /* TOPCKGEN */
  11 #define CLK_TOP_AXI                             0
  12 #define CLK_TOP_SPM                             1
  13 #define CLK_TOP_SCP                             2
  14 #define CLK_TOP_BUS_AXIMEM                      3
  15 #define CLK_TOP_VPP                             4
  16 #define CLK_TOP_ETHDR                           5
  17 #define CLK_TOP_IPE                             6
  18 #define CLK_TOP_CAM                             7
  19 #define CLK_TOP_CCU                             8
  20 #define CLK_TOP_CCU_AHB                         9
  21 #define CLK_TOP_IMG                             10
  22 #define CLK_TOP_CAMTM                           11
  23 #define CLK_TOP_DSP                             12
  24 #define CLK_TOP_DSP1                            13
  25 #define CLK_TOP_DSP2                            14
  26 #define CLK_TOP_DSP3                            15
  27 #define CLK_TOP_DSP4                            16
  28 #define CLK_TOP_DSP5                            17
  29 #define CLK_TOP_DSP6                            18
  30 #define CLK_TOP_DSP7                            19
  31 #define CLK_TOP_MFG_CORE_TMP                    20
  32 #define CLK_TOP_CAMTG                           21
  33 #define CLK_TOP_CAMTG2                          22
  34 #define CLK_TOP_CAMTG3                          23
  35 #define CLK_TOP_UART                            24
  36 #define CLK_TOP_SPI                             25
  37 #define CLK_TOP_MSDC50_0_HCLK                   26
  38 #define CLK_TOP_MSDC50_0                        27
  39 #define CLK_TOP_MSDC30_1                        28
  40 #define CLK_TOP_MSDC30_2                        29
  41 #define CLK_TOP_INTDIR                          30
  42 #define CLK_TOP_AUD_INTBUS                      31
  43 #define CLK_TOP_AUDIO_H                         32
  44 #define CLK_TOP_PWRAP_ULPOSC                    33
  45 #define CLK_TOP_ATB                             34
  46 #define CLK_TOP_SSPM                            35
  47 #define CLK_TOP_DP                              36
  48 #define CLK_TOP_EDP                             37
  49 #define CLK_TOP_DPI                             38
  50 #define CLK_TOP_DISP_PWM0                       39
  51 #define CLK_TOP_DISP_PWM1                       40
  52 #define CLK_TOP_USB_TOP                         41
  53 #define CLK_TOP_SSUSB_XHCI                      42
  54 #define CLK_TOP_USB_TOP_2P                      43
  55 #define CLK_TOP_SSUSB_XHCI_2P                   44
  56 #define CLK_TOP_USB_TOP_3P                      45
  57 #define CLK_TOP_SSUSB_XHCI_3P                   46
  58 #define CLK_TOP_I2C                             47
  59 #define CLK_TOP_SENINF                          48
  60 #define CLK_TOP_SENINF1                         49
  61 #define CLK_TOP_GCPU                            50
  62 #define CLK_TOP_VENC                            51
  63 #define CLK_TOP_VDEC                            52
  64 #define CLK_TOP_PWM                             53
  65 #define CLK_TOP_MCUPM                           54
  66 #define CLK_TOP_SPMI_P_MST                      55
  67 #define CLK_TOP_SPMI_M_MST                      56
  68 #define CLK_TOP_DVFSRC                          57
  69 #define CLK_TOP_TL                              58
  70 #define CLK_TOP_AES_MSDCFDE                     59
  71 #define CLK_TOP_DSI_OCC                         60
  72 #define CLK_TOP_WPE_VPP                         61
  73 #define CLK_TOP_HDCP                            62
  74 #define CLK_TOP_HDCP_24M                        63
  75 #define CLK_TOP_HDMI_APB                        64
  76 #define CLK_TOP_SNPS_ETH_250M                   65
  77 #define CLK_TOP_SNPS_ETH_62P4M_PTP              66
  78 #define CLK_TOP_SNPS_ETH_50M_RMII               67
  79 #define CLK_TOP_ADSP                            68
  80 #define CLK_TOP_AUDIO_LOCAL_BUS                 69
  81 #define CLK_TOP_ASM_H                           70
  82 #define CLK_TOP_ASM_L                           71
  83 #define CLK_TOP_APLL1                           72
  84 #define CLK_TOP_APLL2                           73
  85 #define CLK_TOP_APLL3                           74
  86 #define CLK_TOP_APLL4                           75
  87 #define CLK_TOP_APLL5                           76
  88 #define CLK_TOP_I2SO1                           77
  89 #define CLK_TOP_I2SO2                           78
  90 #define CLK_TOP_I2SI1                           79
  91 #define CLK_TOP_I2SI2                           80
  92 #define CLK_TOP_DPTX                            81
  93 #define CLK_TOP_AUD_IEC                         82
  94 #define CLK_TOP_A1SYS_HP                        83
  95 #define CLK_TOP_A2SYS                           84
  96 #define CLK_TOP_A3SYS                           85
  97 #define CLK_TOP_A4SYS                           86
  98 #define CLK_TOP_ECC                             87
  99 #define CLK_TOP_SPINOR                          88
 100 #define CLK_TOP_ULPOSC                          89
 101 #define CLK_TOP_SRCK                            90
 102 #define CLK_TOP_MFG_CK_FAST_REF                 91
 103 #define CLK_TOP_MAINPLL_D3                      92
 104 #define CLK_TOP_MAINPLL_D4                      93
 105 #define CLK_TOP_MAINPLL_D4_D2                   94
 106 #define CLK_TOP_MAINPLL_D4_D4                   95
 107 #define CLK_TOP_MAINPLL_D4_D8                   96
 108 #define CLK_TOP_MAINPLL_D5                      97
 109 #define CLK_TOP_MAINPLL_D5_D2                   98
 110 #define CLK_TOP_MAINPLL_D5_D4                   99
 111 #define CLK_TOP_MAINPLL_D5_D8                   100
 112 #define CLK_TOP_MAINPLL_D6                      101
 113 #define CLK_TOP_MAINPLL_D6_D2                   102
 114 #define CLK_TOP_MAINPLL_D6_D4                   103
 115 #define CLK_TOP_MAINPLL_D6_D8                   104
 116 #define CLK_TOP_MAINPLL_D7                      105
 117 #define CLK_TOP_MAINPLL_D7_D2                   106
 118 #define CLK_TOP_MAINPLL_D7_D4                   107
 119 #define CLK_TOP_MAINPLL_D7_D8                   108
 120 #define CLK_TOP_MAINPLL_D9                      109
 121 #define CLK_TOP_UNIVPLL_D2                      110
 122 #define CLK_TOP_UNIVPLL_D3                      111
 123 #define CLK_TOP_UNIVPLL_D4                      112
 124 #define CLK_TOP_UNIVPLL_D4_D2                   113
 125 #define CLK_TOP_UNIVPLL_D4_D4                   114
 126 #define CLK_TOP_UNIVPLL_D4_D8                   115
 127 #define CLK_TOP_UNIVPLL_D5                      116
 128 #define CLK_TOP_UNIVPLL_D5_D2                   117
 129 #define CLK_TOP_UNIVPLL_D5_D4                   118
 130 #define CLK_TOP_UNIVPLL_D5_D8                   119
 131 #define CLK_TOP_UNIVPLL_D6                      120
 132 #define CLK_TOP_UNIVPLL_D6_D2                   121
 133 #define CLK_TOP_UNIVPLL_D6_D4                   122
 134 #define CLK_TOP_UNIVPLL_D6_D8                   123
 135 #define CLK_TOP_UNIVPLL_D7                      124
 136 #define CLK_TOP_UNIVPLL_192M                    125
 137 #define CLK_TOP_UNIVPLL_192M_D4                 126
 138 #define CLK_TOP_UNIVPLL_192M_D8                 127
 139 #define CLK_TOP_UNIVPLL_192M_D10                128
 140 #define CLK_TOP_UNIVPLL_192M_D16                129
 141 #define CLK_TOP_UNIVPLL_192M_D32                130
 142 #define CLK_TOP_APLL1_D3                        131
 143 #define CLK_TOP_APLL1_D4                        132
 144 #define CLK_TOP_APLL2_D3                        133
 145 #define CLK_TOP_APLL2_D4                        134
 146 #define CLK_TOP_APLL3_D4                        135
 147 #define CLK_TOP_APLL4_D4                        136
 148 #define CLK_TOP_APLL5_D4                        137
 149 #define CLK_TOP_MMPLL_D4                        138
 150 #define CLK_TOP_MMPLL_D4_D2                     139
 151 #define CLK_TOP_MMPLL_D5                        140
 152 #define CLK_TOP_MMPLL_D5_D2                     141
 153 #define CLK_TOP_MMPLL_D5_D4                     142
 154 #define CLK_TOP_MMPLL_D6                        143
 155 #define CLK_TOP_MMPLL_D6_D2                     144
 156 #define CLK_TOP_MMPLL_D7                        145
 157 #define CLK_TOP_MMPLL_D9                        146
 158 #define CLK_TOP_TVDPLL1                         147
 159 #define CLK_TOP_TVDPLL1_D2                      148
 160 #define CLK_TOP_TVDPLL1_D4                      149
 161 #define CLK_TOP_TVDPLL1_D8                      150
 162 #define CLK_TOP_TVDPLL1_D16                     151
 163 #define CLK_TOP_TVDPLL2                         152
 164 #define CLK_TOP_TVDPLL2_D2                      153
 165 #define CLK_TOP_TVDPLL2_D4                      154
 166 #define CLK_TOP_TVDPLL2_D8                      155
 167 #define CLK_TOP_TVDPLL2_D16                     156
 168 #define CLK_TOP_MSDCPLL_D2                      157
 169 #define CLK_TOP_MSDCPLL_D16                     158
 170 #define CLK_TOP_ETHPLL                          159
 171 #define CLK_TOP_ETHPLL_D2                       160
 172 #define CLK_TOP_ETHPLL_D4                       161
 173 #define CLK_TOP_ETHPLL_D8                       162
 174 #define CLK_TOP_ETHPLL_D10                      163
 175 #define CLK_TOP_ADSPPLL_D2                      164
 176 #define CLK_TOP_ADSPPLL_D4                      165
 177 #define CLK_TOP_ADSPPLL_D8                      166
 178 #define CLK_TOP_ULPOSC1                         167
 179 #define CLK_TOP_ULPOSC1_D2                      168
 180 #define CLK_TOP_ULPOSC1_D4                      169
 181 #define CLK_TOP_ULPOSC1_D8                      170
 182 #define CLK_TOP_ULPOSC1_D7                      171
 183 #define CLK_TOP_ULPOSC1_D10                     172
 184 #define CLK_TOP_ULPOSC1_D16                     173
 185 #define CLK_TOP_MPHONE_SLAVE_BCK                174
 186 #define CLK_TOP_PAD_FPC                         175
 187 #define CLK_TOP_466M_FMEM                       176
 188 #define CLK_TOP_PEXTP_PIPE                      177
 189 #define CLK_TOP_DSI_PHY                         178
 190 #define CLK_TOP_APLL12_CK_DIV0                  179
 191 #define CLK_TOP_APLL12_CK_DIV1                  180
 192 #define CLK_TOP_APLL12_CK_DIV2                  181
 193 #define CLK_TOP_APLL12_CK_DIV3                  182
 194 #define CLK_TOP_APLL12_CK_DIV4                  183
 195 #define CLK_TOP_APLL12_CK_DIV9                  184
 196 #define CLK_TOP_CFGREG_CLOCK_EN_VPP0            185
 197 #define CLK_TOP_CFGREG_CLOCK_EN_VPP1            186
 198 #define CLK_TOP_CFGREG_CLOCK_EN_VDO0            187
 199 #define CLK_TOP_CFGREG_CLOCK_EN_VDO1            188
 200 #define CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS       189
 201 #define CLK_TOP_CFGREG_F26M_VPP0                190
 202 #define CLK_TOP_CFGREG_F26M_VPP1                191
 203 #define CLK_TOP_CFGREG_F26M_VDO0                192
 204 #define CLK_TOP_CFGREG_F26M_VDO1                193
 205 #define CLK_TOP_CFGREG_AUD_F26M_AUD             194
 206 #define CLK_TOP_CFGREG_UNIPLL_SES               195
 207 #define CLK_TOP_CFGREG_F_PCIE_PHY_REF           196
 208 #define CLK_TOP_SSUSB_TOP_REF                   197
 209 #define CLK_TOP_SSUSB_PHY_REF                   198
 210 #define CLK_TOP_SSUSB_TOP_P1_REF                199
 211 #define CLK_TOP_SSUSB_PHY_P1_REF                200
 212 #define CLK_TOP_SSUSB_TOP_P2_REF                201
 213 #define CLK_TOP_SSUSB_PHY_P2_REF                202
 214 #define CLK_TOP_SSUSB_TOP_P3_REF                203
 215 #define CLK_TOP_SSUSB_PHY_P3_REF                204
 216 #define CLK_TOP_NR_CLK                          205
 217
 218 /* INFRACFG_AO */
 219 #define CLK_INFRA_AO_PMIC_TMR                   0
 220 #define CLK_INFRA_AO_PMIC_AP                    1
 221 #define CLK_INFRA_AO_PMIC_MD                    2
 222 #define CLK_INFRA_AO_PMIC_CONN                  3
 223 #define CLK_INFRA_AO_SEJ                        4
 224 #define CLK_INFRA_AO_APXGPT                     5
 225 #define CLK_INFRA_AO_GCE                        6
 226 #define CLK_INFRA_AO_GCE2                       7
 227 #define CLK_INFRA_AO_THERM                      8
 228 #define CLK_INFRA_AO_PWM_HCLK                   9
 229 #define CLK_INFRA_AO_PWM1                       10
 230 #define CLK_INFRA_AO_PWM2                       11
 231 #define CLK_INFRA_AO_PWM3                       12
 232 #define CLK_INFRA_AO_PWM4                       13
 233 #define CLK_INFRA_AO_PWM                        14
 234 #define CLK_INFRA_AO_UART0                      15
 235 #define CLK_INFRA_AO_UART1                      16
 236 #define CLK_INFRA_AO_UART2                      17
 237 #define CLK_INFRA_AO_UART3                      18
 238 #define CLK_INFRA_AO_UART4                      19
 239 #define CLK_INFRA_AO_GCE_26M                    20
 240 #define CLK_INFRA_AO_CQ_DMA_FPC                 21
 241 #define CLK_INFRA_AO_UART5                      22
 242 #define CLK_INFRA_AO_HDMI_26M                   23
 243 #define CLK_INFRA_AO_SPI0                       24
 244 #define CLK_INFRA_AO_MSDC0                      25
 245 #define CLK_INFRA_AO_MSDC1                      26
 246 #define CLK_INFRA_AO_MSDC2                      27
 247 #define CLK_INFRA_AO_MSDC0_SRC                  28
 248 #define CLK_INFRA_AO_DVFSRC                     29
 249 #define CLK_INFRA_AO_TRNG                       30
 250 #define CLK_INFRA_AO_AUXADC                     31
 251 #define CLK_INFRA_AO_CPUM                       32
 252 #define CLK_INFRA_AO_HDMI_32K                   33
 253 #define CLK_INFRA_AO_CEC_66M_HCLK               34
 254 #define CLK_INFRA_AO_PCIE_TL_26M                35
 255 #define CLK_INFRA_AO_MSDC1_SRC                  36
 256 #define CLK_INFRA_AO_CEC_66M_BCLK               37
 257 #define CLK_INFRA_AO_PCIE_TL_96M                38
 258 #define CLK_INFRA_AO_DEVICE_APC                 39
 259 #define CLK_INFRA_AO_ECC_66M_HCLK               40
 260 #define CLK_INFRA_AO_DEBUGSYS                   41
 261 #define CLK_INFRA_AO_AUDIO                      42
 262 #define CLK_INFRA_AO_PCIE_TL_32K                43
 263 #define CLK_INFRA_AO_DBG_TRACE                  44
 264 #define CLK_INFRA_AO_DRAMC_F26M                 45
 265 #define CLK_INFRA_AO_IRTX                       46
 266 #define CLK_INFRA_AO_DISP_PWM                   47
 267 #define CLK_INFRA_AO_CLDMA_BCLK                 48
 268 #define CLK_INFRA_AO_AUDIO_26M_BCLK             49
 269 #define CLK_INFRA_AO_SPI1                       50
 270 #define CLK_INFRA_AO_SPI2                       51
 271 #define CLK_INFRA_AO_SPI3                       52
 272 #define CLK_INFRA_AO_FSSPM                      53
 273 #define CLK_INFRA_AO_SSPM_BUS_HCLK              54
 274 #define CLK_INFRA_AO_APDMA_BCLK                 55
 275 #define CLK_INFRA_AO_SPI4                       56
 276 #define CLK_INFRA_AO_SPI5                       57
 277 #define CLK_INFRA_AO_CQ_DMA                     58
 278 #define CLK_INFRA_AO_MSDC0_SELF                 59
 279 #define CLK_INFRA_AO_MSDC1_SELF                 60
 280 #define CLK_INFRA_AO_MSDC2_SELF                 61
 281 #define CLK_INFRA_AO_I2S_DMA                    62
 282 #define CLK_INFRA_AO_AP_MSDC0                   63
 283 #define CLK_INFRA_AO_MD_MSDC0                   64
 284 #define CLK_INFRA_AO_MSDC30_2                   65
 285 #define CLK_INFRA_AO_GCPU                       66
 286 #define CLK_INFRA_AO_PCIE_PERI_26M              67
 287 #define CLK_INFRA_AO_GCPU_66M_BCLK              68
 288 #define CLK_INFRA_AO_GCPU_133M_BCLK             69
 289 #define CLK_INFRA_AO_DISP_PWM1                  70
 290 #define CLK_INFRA_AO_FBIST2FPC                  71
 291 #define CLK_INFRA_AO_DEVICE_APC_SYNC            72
 292 #define CLK_INFRA_AO_PCIE_P1_PERI_26M           73
 293 #define CLK_INFRA_AO_133M_MCLK_CK               74
 294 #define CLK_INFRA_AO_66M_MCLK_CK                75
 295 #define CLK_INFRA_AO_PCIE_PL_P_250M_P0          76
 296 #define CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P       77
 297 #define CLK_INFRA_AO_NR_CLK                     78
 298
 299 /* APMIXEDSYS */
 300 #define CLK_APMIXED_ETHPLL                      0
 301 #define CLK_APMIXED_MSDCPLL                     1
 302 #define CLK_APMIXED_TVDPLL1                     2
 303 #define CLK_APMIXED_TVDPLL2                     3
 304 #define CLK_APMIXED_MMPLL                       4
 305 #define CLK_APMIXED_MAINPLL                     5
 306 #define CLK_APMIXED_IMGPLL                      6
 307 #define CLK_APMIXED_UNIVPLL                     7
 308 #define CLK_APMIXED_ADSPPLL                     8
 309 #define CLK_APMIXED_APLL1                       9
 310 #define CLK_APMIXED_APLL2                       10
 311 #define CLK_APMIXED_APLL3                       11
 312 #define CLK_APMIXED_APLL4                       12
 313 #define CLK_APMIXED_APLL5                       13
 314 #define CLK_APMIXED_MFGPLL                      14
 315 #define CLK_APMIXED_PLL_SSUSB26M_EN             15
 316 #define CLK_APMIXED_NR_CLK                      16
 317
 318 /* AUDIODSP */
 319 #define CLK_AUDIODSP_AUDIO26M                   0
 320 #define CLK_AUDIODSP_NR_CLK                     1
 321
 322 /* PERICFG_AO */
 323 #define CLK_PERI_AO_ETHERNET                    0
 324 #define CLK_PERI_AO_ETHERNET_BUS                1
 325 #define CLK_PERI_AO_FLASHIF_BUS                 2
 326 #define CLK_PERI_AO_FLASHIF_26M                 3
 327 #define CLK_PERI_AO_FLASHIFLASHCK               4
 328 #define CLK_PERI_AO_SSUSB_2P_BUS                5
 329 #define CLK_PERI_AO_SSUSB_2P_XHCI               6
 330 #define CLK_PERI_AO_SSUSB_3P_BUS                7
 331 #define CLK_PERI_AO_SSUSB_3P_XHCI               8
 332 #define CLK_PERI_AO_SSUSB_BUS                   9
 333 #define CLK_PERI_AO_SSUSB_XHCI                  10
 334 #define CLK_PERI_AO_ETHERNET_MAC                11
 335 #define CLK_PERI_AO_PCIE_P0_FMEM                12
 336 #define CLK_PERI_AO_NR_CLK                      13
 337
 338 /* IMP_IIC_WRAP_C */
 339 #define CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0        0
 340 #define CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C2        1
 341 #define CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C3        2
 342 #define CLK_IMP_IIC_WRAP_C_NR_CLK               3
 343
 344 /* IMP_IIC_WRAP_W */
 345 #define CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C1        0
 346 #define CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C4        1
 347 #define CLK_IMP_IIC_WRAP_W_NR_CLK               2
 348
 349 /* IMP_IIC_WRAP_EN */
 350 #define CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5       0
 351 #define CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6       1
 352 #define CLK_IMP_IIC_WRAP_EN_NR_CLK              2
 353
 354 /* MFGCFG */
 355 #define CLK_MFGCFG_BG3D                         0
 356 #define CLK_MFGCFG_NR_CLK                       1
 357
 358 /* VPPSYS0 */
 359 #define CLK_VPP0_MDP_FG                         0
 360 #define CLK_VPP0_STITCH                         1
 361 #define CLK_VPP0_PADDING                        2
 362 #define CLK_VPP0_MDP_TCC                        3
 363 #define CLK_VPP0_WARP0_ASYNC_TX                 4
 364 #define CLK_VPP0_WARP1_ASYNC_TX                 5
 365 #define CLK_VPP0_MUTEX                          6
 366 #define CLK_VPP02VPP1_RELAY                     7
 367 #define CLK_VPP0_VPP12VPP0_ASYNC                8
 368 #define CLK_VPP0_MMSYSRAM_TOP                   9
 369 #define CLK_VPP0_MDP_AAL                        10
 370 #define CLK_VPP0_MDP_RSZ                        11
 371 #define CLK_VPP0_SMI_COMMON_MMSRAM              12
 372 #define CLK_VPP0_GALS_VDO0_LARB0_MMSRAM         13
 373 #define CLK_VPP0_GALS_VDO0_LARB1_MMSRAM         14
 374 #define CLK_VPP0_GALS_VENCSYS_MMSRAM            15
 375 #define CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM      16
 376 #define CLK_VPP0_GALS_INFRA_MMSRAM              17
 377 #define CLK_VPP0_GALS_CAMSYS_MMSRAM             18
 378 #define CLK_VPP0_GALS_VPP1_LARB5_MMSRAM         19
 379 #define CLK_VPP0_GALS_VPP1_LARB6_MMSRAM         20
 380 #define CLK_VPP0_SMI_REORDER_MMSRAM             21
 381 #define CLK_VPP0_SMI_IOMMU                      22
 382 #define CLK_VPP0_GALS_IMGSYS_CAMSYS             23
 383 #define CLK_VPP0_MDP_RDMA                       24
 384 #define CLK_VPP0_MDP_WROT                       25
 385 #define CLK_VPP0_GALS_EMI0_EMI1                 26
 386 #define CLK_VPP0_SMI_SUB_COMMON_REORDER         27
 387 #define CLK_VPP0_SMI_RSI                        28
 388 #define CLK_VPP0_SMI_COMMON_LARB4               29
 389 #define CLK_VPP0_GALS_VDEC_VDEC_CORE1           30
 390 #define CLK_VPP0_GALS_VPP1_WPESYS               31
 391 #define CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1   32
 392 #define CLK_VPP0_FAKE_ENG                       33
 393 #define CLK_VPP0_MDP_HDR                        34
 394 #define CLK_VPP0_MDP_TDSHP                      35
 395 #define CLK_VPP0_MDP_COLOR                      36
 396 #define CLK_VPP0_MDP_OVL                        37
 397 #define CLK_VPP0_DSIP_RDMA                      38
 398 #define CLK_VPP0_DISP_WDMA                      39
 399 #define CLK_VPP0_MDP_HMS                        40
 400 #define CLK_VPP0_WARP0_RELAY                    41
 401 #define CLK_VPP0_WARP0_ASYNC                    42
 402 #define CLK_VPP0_WARP1_RELAY                    43
 403 #define CLK_VPP0_WARP1_ASYNC                    44
 404 #define CLK_VPP0_NR_CLK                         45
 405
 406 /* WPESYS */
 407 #define CLK_WPE_TOP_WPE_VPP0                    0
 408 #define CLK_WPE_TOP_SMI_LARB7                   1
 409 #define CLK_WPE_TOP_WPESYS_EVENT_TX             2
 410 #define CLK_WPE_TOP_SMI_LARB7_PCLK_EN           3
 411 #define CLK_WPE_TOP_NR_CLK                      4
 412
 413 /* WPESYS_VPP0 */
 414 #define CLK_WPE_VPP0_VECI                       0
 415 #define CLK_WPE_VPP0_VEC2I                      1
 416 #define CLK_WPE_VPP0_VEC3I                      2
 417 #define CLK_WPE_VPP0_WPEO                       3
 418 #define CLK_WPE_VPP0_MSKO                       4
 419 #define CLK_WPE_VPP0_VGEN                       5
 420 #define CLK_WPE_VPP0_EXT                        6
 421 #define CLK_WPE_VPP0_VFC                        7
 422 #define CLK_WPE_VPP0_CACH0_TOP                  8
 423 #define CLK_WPE_VPP0_CACH0_DMA                  9
 424 #define CLK_WPE_VPP0_CACH1_TOP                  10
 425 #define CLK_WPE_VPP0_CACH1_DMA                  11
 426 #define CLK_WPE_VPP0_CACH2_TOP                  12
 427 #define CLK_WPE_VPP0_CACH2_DMA                  13
 428 #define CLK_WPE_VPP0_CACH3_TOP                  14
 429 #define CLK_WPE_VPP0_CACH3_DMA                  15
 430 #define CLK_WPE_VPP0_PSP                        16
 431 #define CLK_WPE_VPP0_PSP2                       17
 432 #define CLK_WPE_VPP0_SYNC                       18
 433 #define CLK_WPE_VPP0_C24                        19
 434 #define CLK_WPE_VPP0_MDP_CROP                   20
 435 #define CLK_WPE_VPP0_ISP_CROP                   21
 436 #define CLK_WPE_VPP0_TOP                        22
 437 #define CLK_WPE_VPP0_NR_CLK                     23
 438
 439 /* VPPSYS1 */
 440 #define CLK_VPP1_SVPP1_MDP_OVL                  0
 441 #define CLK_VPP1_SVPP1_MDP_TCC                  1
 442 #define CLK_VPP1_SVPP1_MDP_WROT                 2
 443 #define CLK_VPP1_SVPP1_VPP_PAD                  3
 444 #define CLK_VPP1_SVPP2_MDP_WROT                 4
 445 #define CLK_VPP1_SVPP2_VPP_PAD                  5
 446 #define CLK_VPP1_SVPP3_MDP_WROT                 6
 447 #define CLK_VPP1_SVPP3_VPP_PAD                  7
 448 #define CLK_VPP1_SVPP1_MDP_RDMA                 8
 449 #define CLK_VPP1_SVPP1_MDP_FG                   9
 450 #define CLK_VPP1_SVPP2_MDP_RDMA                 10
 451 #define CLK_VPP1_SVPP2_MDP_FG                   11
 452 #define CLK_VPP1_SVPP3_MDP_RDMA                 12
 453 #define CLK_VPP1_SVPP3_MDP_FG                   13
 454 #define CLK_VPP1_VPP_SPLIT                      14
 455 #define CLK_VPP1_SVPP2_VDO0_DL_RELAY            15
 456 #define CLK_VPP1_SVPP1_MDP_RSZ                  16
 457 #define CLK_VPP1_SVPP1_MDP_TDSHP                17
 458 #define CLK_VPP1_SVPP1_MDP_COLOR                18
 459 #define CLK_VPP1_SVPP3_VDO1_DL_RELAY            19
 460 #define CLK_VPP1_SVPP2_MDP_RSZ                  20
 461 #define CLK_VPP1_SVPP2_VPP_MERGE                21
 462 #define CLK_VPP1_SVPP2_MDP_TDSHP                22
 463 #define CLK_VPP1_SVPP2_MDP_COLOR                23
 464 #define CLK_VPP1_SVPP3_MDP_RSZ                  24
 465 #define CLK_VPP1_SVPP3_VPP_MERGE                25
 466 #define CLK_VPP1_SVPP3_MDP_TDSHP                26
 467 #define CLK_VPP1_SVPP3_MDP_COLOR                27
 468 #define CLK_VPP1_GALS5                          28
 469 #define CLK_VPP1_GALS6                          29
 470 #define CLK_VPP1_LARB5                          30
 471 #define CLK_VPP1_LARB6                          31
 472 #define CLK_VPP1_SVPP1_MDP_HDR                  32
 473 #define CLK_VPP1_SVPP1_MDP_AAL                  33
 474 #define CLK_VPP1_SVPP2_MDP_HDR                  34
 475 #define CLK_VPP1_SVPP2_MDP_AAL                  35
 476 #define CLK_VPP1_SVPP3_MDP_HDR                  36
 477 #define CLK_VPP1_SVPP3_MDP_AAL                  37
 478 #define CLK_VPP1_DISP_MUTEX                     38
 479 #define CLK_VPP1_SVPP2_VDO1_DL_RELAY            39
 480 #define CLK_VPP1_SVPP3_VDO0_DL_RELAY            40
 481 #define CLK_VPP1_VPP0_DL_ASYNC                  41
 482 #define CLK_VPP1_VPP0_DL1_RELAY                 42
 483 #define CLK_VPP1_LARB5_FAKE_ENG                 43
 484 #define CLK_VPP1_LARB6_FAKE_ENG                 44
 485 #define CLK_VPP1_HDMI_META                      45
 486 #define CLK_VPP1_VPP_SPLIT_HDMI                 46
 487 #define CLK_VPP1_DGI_IN                         47
 488 #define CLK_VPP1_DGI_OUT                        48
 489 #define CLK_VPP1_VPP_SPLIT_DGI                  49
 490 #define CLK_VPP1_DL_CON_OCC                     50
 491 #define CLK_VPP1_VPP_SPLIT_26M                  51
 492 #define CLK_VPP1_NR_CLK                         52
 493
 494 /* IMGSYS */
 495 #define CLK_IMGSYS_MAIN_LARB9                   0
 496 #define CLK_IMGSYS_MAIN_TRAW0                   1
 497 #define CLK_IMGSYS_MAIN_TRAW1                   2
 498 #define CLK_IMGSYS_MAIN_VCORE_GALS              3
 499 #define CLK_IMGSYS_MAIN_DIP0                    4
 500 #define CLK_IMGSYS_MAIN_WPE0                    5
 501 #define CLK_IMGSYS_MAIN_IPE                     6
 502 #define CLK_IMGSYS_MAIN_WPE1                    7
 503 #define CLK_IMGSYS_MAIN_WPE2                    8
 504 #define CLK_IMGSYS_MAIN_GALS                    9
 505 #define CLK_IMGSYS_MAIN_NR_CLK                  10
 506
 507 /* IMGSYS1_DIP_TOP */
 508 #define CLK_IMGSYS1_DIP_TOP_LARB10              0
 509 #define CLK_IMGSYS1_DIP_TOP_DIP_TOP             1
 510 #define CLK_IMGSYS1_DIP_TOP_NR_CLK              2
 511
 512 /* IMGSYS1_DIP_NR */
 513 #define CLK_IMGSYS1_DIP_NR_LARB15               0
 514 #define CLK_IMGSYS1_DIP_NR_DIP_NR               1
 515 #define CLK_IMGSYS1_DIP_NR_NR_CLK               2
 516
 517 /* IMGSYS_WPE1 */
 518 #define CLK_IMGSYS_WPE1_LARB11                  0
 519 #define CLK_IMGSYS_WPE1                         1
 520 #define CLK_IMGSYS_WPE1_NR_CLK                  2
 521
 522 /* IPESYS */
 523 #define CLK_IPE_DPE                             0
 524 #define CLK_IPE_FDVT                            1
 525 #define CLK_IPE_ME                              2
 526 #define CLK_IPESYS_TOP                          3
 527 #define CLK_IPE_SMI_LARB12                      4
 528 #define CLK_IPE_NR_CLK                          5
 529
 530 /* IMGSYS_WPE2 */
 531 #define CLK_IMGSYS_WPE2_LARB11                  0
 532 #define CLK_IMGSYS_WPE2                         1
 533 #define CLK_IMGSYS_WPE2_NR_CLK                  2
 534
 535 /* IMGSYS_WPE3 */
 536 #define CLK_IMGSYS_WPE3_LARB11                  0
 537 #define CLK_IMGSYS_WPE3                         1
 538 #define CLK_IMGSYS_WPE3_NR_CLK                  2
 539
 540 /* CAMSYS */
 541 #define CLK_CAM_MAIN_LARB13                     0
 542 #define CLK_CAM_MAIN_LARB14                     1
 543 #define CLK_CAM_MAIN_CAM                        2
 544 #define CLK_CAM_MAIN_CAM_SUBA                   3
 545 #define CLK_CAM_MAIN_CAM_SUBB                   4
 546 #define CLK_CAM_MAIN_CAMTG                      5
 547 #define CLK_CAM_MAIN_SENINF                     6
 548 #define CLK_CAM_MAIN_GCAMSVA                    7
 549 #define CLK_CAM_MAIN_GCAMSVB                    8
 550 #define CLK_CAM_MAIN_GCAMSVC                    9
 551 #define CLK_CAM_MAIN_GCAMSVD                    10
 552 #define CLK_CAM_MAIN_GCAMSVE                    11
 553 #define CLK_CAM_MAIN_GCAMSVF                    12
 554 #define CLK_CAM_MAIN_GCAMSVG                    13
 555 #define CLK_CAM_MAIN_GCAMSVH                    14
 556 #define CLK_CAM_MAIN_GCAMSVI                    15
 557 #define CLK_CAM_MAIN_GCAMSVJ                    16
 558 #define CLK_CAM_MAIN_CAMSV_TOP                  17
 559 #define CLK_CAM_MAIN_CAMSV_CQ_A                 18
 560 #define CLK_CAM_MAIN_CAMSV_CQ_B                 19
 561 #define CLK_CAM_MAIN_CAMSV_CQ_C                 20
 562 #define CLK_CAM_MAIN_FAKE_ENG                   21
 563 #define CLK_CAM_MAIN_CAM2MM0_GALS               22
 564 #define CLK_CAM_MAIN_CAM2MM1_GALS               23
 565 #define CLK_CAM_MAIN_CAM2SYS_GALS               24
 566 #define CLK_CAM_MAIN_NR_CLK                     25
 567
 568 /* CAMSYS_RAWA */
 569 #define CLK_CAM_RAWA_LARBX                      0
 570 #define CLK_CAM_RAWA_CAM                        1
 571 #define CLK_CAM_RAWA_CAMTG                      2
 572 #define CLK_CAM_RAWA_NR_CLK                     3
 573
 574 /* CAMSYS_YUVA */
 575 #define CLK_CAM_YUVA_LARBX                      0
 576 #define CLK_CAM_YUVA_CAM                        1
 577 #define CLK_CAM_YUVA_CAMTG                      2
 578 #define CLK_CAM_YUVA_NR_CLK                     3
 579
 580 /* CAMSYS_RAWB */
 581 #define CLK_CAM_RAWB_LARBX                      0
 582 #define CLK_CAM_RAWB_CAM                        1
 583 #define CLK_CAM_RAWB_CAMTG                      2
 584 #define CLK_CAM_RAWB_NR_CLK                     3
 585
 586 /* CAMSYS_YUVB */
 587 #define CLK_CAM_YUVB_LARBX                      0
 588 #define CLK_CAM_YUVB_CAM                        1
 589 #define CLK_CAM_YUVB_CAMTG                      2
 590 #define CLK_CAM_YUVB_NR_CLK                     3
 591
 592 /* CCUSYS */
 593 #define CLK_CCU_LARB27                          0
 594 #define CLK_CCU_AHB                             1
 595 #define CLK_CCU_CCU0                            2
 596 #define CLK_CCU_NR_CLK                          3
 597
 598 /* VDECSYS_SOC */
 599 #define CLK_VDEC1_SOC_LARB1                     0
 600 #define CLK_VDEC1_SOC_LAT                       1
 601 #define CLK_VDEC1_SOC_LAT_ACTIVE                        2
 602 #define CLK_VDEC1_SOC_LAT_ENG                   3
 603 #define CLK_VDEC1_SOC_VDEC                      4
 604 #define CLK_VDEC1_SOC_VDEC_ACTIVE               5
 605 #define CLK_VDEC1_SOC_VDEC_ENG                  6
 606 #define CLK_VDEC1_NR_CLK                                7
 607
 608 /* VDECSYS */
 609 #define CLK_VDEC2_LARB1                         0
 610 #define CLK_VDEC2_LAT                           1
 611 #define CLK_VDEC2_VDEC                          2
 612 #define CLK_VDEC2_VDEC_ACTIVE                   3
 613 #define CLK_VDEC2_VDEC_ENG                      4
 614 #define CLK_VDEC2_NR_CLK                                5
 615
 616 /* VENCSYS */
 617 #define CLK_VENC1_LARB                  0
 618 #define CLK_VENC1_VENC                  1
 619 #define CLK_VENC1_JPGENC                        2
 620 #define CLK_VENC1_JPGDEC                        3
 621 #define CLK_VENC1_JPGDEC_C1                     4
 622 #define CLK_VENC1_GALS                  5
 623 #define CLK_VENC1_GALS_SRAM                     6
 624 #define CLK_VENC1_NR_CLK                                7
 625
 626 /* VDOSYS0 */
 627 #define CLK_VDO0_DISP_OVL0                      0
 628 #define CLK_VDO0_FAKE_ENG0                      1
 629 #define CLK_VDO0_DISP_CCORR0                    2
 630 #define CLK_VDO0_DISP_MUTEX0                    3
 631 #define CLK_VDO0_DISP_GAMMA0                    4
 632 #define CLK_VDO0_DISP_DITHER0                   5
 633 #define CLK_VDO0_DISP_WDMA0                     6
 634 #define CLK_VDO0_DISP_RDMA0                     7
 635 #define CLK_VDO0_DSI0                           8
 636 #define CLK_VDO0_DSI1                           9
 637 #define CLK_VDO0_DSC_WRAP0                      10
 638 #define CLK_VDO0_VPP_MERGE0                     11
 639 #define CLK_VDO0_DP_INTF0                       12
 640 #define CLK_VDO0_DISP_AAL0                      13
 641 #define CLK_VDO0_INLINEROT0                     14
 642 #define CLK_VDO0_APB_BUS                        15
 643 #define CLK_VDO0_DISP_COLOR0                    16
 644 #define CLK_VDO0_MDP_WROT0                      17
 645 #define CLK_VDO0_DISP_RSZ0                      18
 646 #define CLK_VDO0_DISP_POSTMASK0                 19
 647 #define CLK_VDO0_FAKE_ENG1                      20
 648 #define CLK_VDO0_DL_ASYNC2                      21
 649 #define CLK_VDO0_DL_RELAY3                      22
 650 #define CLK_VDO0_DL_RELAY4                      23
 651 #define CLK_VDO0_SMI_GALS                       24
 652 #define CLK_VDO0_SMI_COMMON                     25
 653 #define CLK_VDO0_SMI_EMI                        26
 654 #define CLK_VDO0_SMI_IOMMU                      27
 655 #define CLK_VDO0_SMI_LARB                       28
 656 #define CLK_VDO0_SMI_RSI                        29
 657 #define CLK_VDO0_DSI0_DSI                       30
 658 #define CLK_VDO0_DSI1_DSI                       31
 659 #define CLK_VDO0_DP_INTF0_DP_INTF               32
 660 #define CLK_VDO0_NR_CLK                         33
 661
 662 /* VDOSYS1 */
 663 #define CLK_VDO1_SMI_LARB2                      0
 664 #define CLK_VDO1_SMI_LARB3                      1
 665 #define CLK_VDO1_GALS                           2
 666 #define CLK_VDO1_FAKE_ENG0                      3
 667 #define CLK_VDO1_FAKE_ENG1                      4
 668 #define CLK_VDO1_MDP_RDMA0                      5
 669 #define CLK_VDO1_MDP_RDMA1                      6
 670 #define CLK_VDO1_MDP_RDMA2                      7
 671 #define CLK_VDO1_MDP_RDMA3                      8
 672 #define CLK_VDO1_VPP_MERGE0                     9
 673 #define CLK_VDO1_VPP_MERGE1                     10
 674 #define CLK_VDO1_VPP_MERGE2                     11
 675 #define CLK_VDO1_VPP_MERGE3                     12
 676 #define CLK_VDO1_VPP_MERGE4                     13
 677 #define CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC          14
 678 #define CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC          15
 679 #define CLK_VDO1_DISP_MUTEX                     16
 680 #define CLK_VDO1_MDP_RDMA4                      17
 681 #define CLK_VDO1_MDP_RDMA5                      18
 682 #define CLK_VDO1_MDP_RDMA6                      19
 683 #define CLK_VDO1_MDP_RDMA7                      20
 684 #define CLK_VDO1_DP_INTF0_MMCK                  21
 685 #define CLK_VDO1_DPI0_MM                        22
 686 #define CLK_VDO1_DPI1_MM                        23
 687 #define CLK_VDO1_MERGE0_DL_ASYNC                24
 688 #define CLK_VDO1_MERGE1_DL_ASYNC                25
 689 #define CLK_VDO1_MERGE2_DL_ASYNC                26
 690 #define CLK_VDO1_MERGE3_DL_ASYNC                27
 691 #define CLK_VDO1_MERGE4_DL_ASYNC                28
 692 #define CLK_VDO1_DSC_VDO1_DL_ASYNC              29
 693 #define CLK_VDO1_MERGE_VDO1_DL_ASYNC            30
 694 #define CLK_VDO1_PADDING0                       31
 695 #define CLK_VDO1_PADDING1                       32
 696 #define CLK_VDO1_PADDING2                       33
 697 #define CLK_VDO1_PADDING3                       34
 698 #define CLK_VDO1_PADDING4                       35
 699 #define CLK_VDO1_PADDING5                       36
 700 #define CLK_VDO1_PADDING6                       37
 701 #define CLK_VDO1_PADDING7                       38
 702 #define CLK_VDO1_DISP_RSZ0                      39
 703 #define CLK_VDO1_DISP_RSZ1                      40
 704 #define CLK_VDO1_DISP_RSZ2                      41
 705 #define CLK_VDO1_DISP_RSZ3                      42
 706 #define CLK_VDO1_HDR_VDO_FE0                    43
 707 #define CLK_VDO1_HDR_GFX_FE0                    44
 708 #define CLK_VDO1_HDR_VDO_BE                     45
 709 #define CLK_VDO1_HDR_VDO_FE1                    46
 710 #define CLK_VDO1_HDR_GFX_FE1                    47
 711 #define CLK_VDO1_DISP_MIXER                     48
 712 #define CLK_VDO1_HDR_VDO_FE0_DL_ASYNC           49
 713 #define CLK_VDO1_HDR_VDO_FE1_DL_ASYNC           50
 714 #define CLK_VDO1_HDR_GFX_FE0_DL_ASYNC           51
 715 #define CLK_VDO1_HDR_GFX_FE1_DL_ASYNC           52
 716 #define CLK_VDO1_HDR_VDO_BE_DL_ASYNC            53
 717 #define CLK_VDO1_DPI0                           54
 718 #define CLK_VDO1_DISP_MONITOR_DPI0              55
 719 #define CLK_VDO1_DPI1                           56
 720 #define CLK_VDO1_DISP_MONITOR_DPI1              57
 721 #define CLK_VDO1_DPINTF                         58
 722 #define CLK_VDO1_DISP_MONITOR_DPINTF            59
 723 #define CLK_VDO1_26M_SLOW                       60
 724 #define CLK_VDO1_NR_CLK                         61
 725
 726 #endif /* _DT_BINDINGS_CLK_MT8188_H */