GNU Linux-libre 6.9.1-gnu
[releases.git] / include / dt-bindings / clock / mediatek,mt6795-clk.h
1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */
2 /*
3  * Copyright (c) 2022 Collabora Ltd.
4  * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
5  */
6
7 #ifndef _DT_BINDINGS_CLK_MT6795_H
8 #define _DT_BINDINGS_CLK_MT6795_H
9
10 /* TOPCKGEN */
11 #define CLK_TOP_ADSYS_26M               0
12 #define CLK_TOP_CLKPH_MCK_O             1
13 #define CLK_TOP_USB_SYSPLL_125M         2
14 #define CLK_TOP_DSI0_DIG                3
15 #define CLK_TOP_DSI1_DIG                4
16 #define CLK_TOP_ARMCA53PLL_754M         5
17 #define CLK_TOP_ARMCA53PLL_502M         6
18 #define CLK_TOP_MAIN_H546M              7
19 #define CLK_TOP_MAIN_H364M              8
20 #define CLK_TOP_MAIN_H218P4M            9
21 #define CLK_TOP_MAIN_H156M              10
22 #define CLK_TOP_TVDPLL_445P5M           11
23 #define CLK_TOP_TVDPLL_594M             12
24 #define CLK_TOP_UNIV_624M               13
25 #define CLK_TOP_UNIV_416M               14
26 #define CLK_TOP_UNIV_249P6M             15
27 #define CLK_TOP_UNIV_178P3M             16
28 #define CLK_TOP_UNIV_48M                17
29 #define CLK_TOP_CLKRTC_EXT              18
30 #define CLK_TOP_CLKRTC_INT              19
31 #define CLK_TOP_FPC                     20
32 #define CLK_TOP_HDMITXPLL_D2            21
33 #define CLK_TOP_HDMITXPLL_D3            22
34 #define CLK_TOP_ARMCA53PLL_D2           23
35 #define CLK_TOP_ARMCA53PLL_D3           24
36 #define CLK_TOP_APLL1                   25
37 #define CLK_TOP_APLL2                   26
38 #define CLK_TOP_DMPLL                   27
39 #define CLK_TOP_DMPLL_D2                28
40 #define CLK_TOP_DMPLL_D4                29
41 #define CLK_TOP_DMPLL_D8                30
42 #define CLK_TOP_DMPLL_D16               31
43 #define CLK_TOP_MMPLL                   32
44 #define CLK_TOP_MMPLL_D2                33
45 #define CLK_TOP_MSDCPLL                 34
46 #define CLK_TOP_MSDCPLL_D2              35
47 #define CLK_TOP_MSDCPLL_D4              36
48 #define CLK_TOP_MSDCPLL2                37
49 #define CLK_TOP_MSDCPLL2_D2             38
50 #define CLK_TOP_MSDCPLL2_D4             39
51 #define CLK_TOP_SYSPLL_D2               40
52 #define CLK_TOP_SYSPLL1_D2              41
53 #define CLK_TOP_SYSPLL1_D4              42
54 #define CLK_TOP_SYSPLL1_D8              43
55 #define CLK_TOP_SYSPLL1_D16             44
56 #define CLK_TOP_SYSPLL_D3               45
57 #define CLK_TOP_SYSPLL2_D2              46
58 #define CLK_TOP_SYSPLL2_D4              47
59 #define CLK_TOP_SYSPLL_D5               48
60 #define CLK_TOP_SYSPLL3_D2              49
61 #define CLK_TOP_SYSPLL3_D4              50
62 #define CLK_TOP_SYSPLL_D7               51
63 #define CLK_TOP_SYSPLL4_D2              52
64 #define CLK_TOP_SYSPLL4_D4              53
65 #define CLK_TOP_TVDPLL                  54
66 #define CLK_TOP_TVDPLL_D2               55
67 #define CLK_TOP_TVDPLL_D4               56
68 #define CLK_TOP_TVDPLL_D8               57
69 #define CLK_TOP_TVDPLL_D16              58
70 #define CLK_TOP_UNIVPLL_D2              59
71 #define CLK_TOP_UNIVPLL1_D2             60
72 #define CLK_TOP_UNIVPLL1_D4             61
73 #define CLK_TOP_UNIVPLL1_D8             62
74 #define CLK_TOP_UNIVPLL_D3              63
75 #define CLK_TOP_UNIVPLL2_D2             64
76 #define CLK_TOP_UNIVPLL2_D4             65
77 #define CLK_TOP_UNIVPLL2_D8             66
78 #define CLK_TOP_UNIVPLL_D5              67
79 #define CLK_TOP_UNIVPLL3_D2             68
80 #define CLK_TOP_UNIVPLL3_D4             69
81 #define CLK_TOP_UNIVPLL3_D8             70
82 #define CLK_TOP_UNIVPLL_D7              71
83 #define CLK_TOP_UNIVPLL_D26             72
84 #define CLK_TOP_UNIVPLL_D52             73
85 #define CLK_TOP_VCODECPLL               74
86 #define CLK_TOP_VCODECPLL_370P5         75
87 #define CLK_TOP_VENCPLL                 76
88 #define CLK_TOP_VENCPLL_D2              77
89 #define CLK_TOP_VENCPLL_D4              78
90 #define CLK_TOP_AXI_SEL                 79
91 #define CLK_TOP_MEM_SEL                 80
92 #define CLK_TOP_DDRPHYCFG_SEL           81
93 #define CLK_TOP_MM_SEL                  82
94 #define CLK_TOP_PWM_SEL                 83
95 #define CLK_TOP_VDEC_SEL                84
96 #define CLK_TOP_VENC_SEL                85
97 #define CLK_TOP_MFG_SEL                 86
98 #define CLK_TOP_CAMTG_SEL               87
99 #define CLK_TOP_UART_SEL                88
100 #define CLK_TOP_SPI_SEL                 89
101 #define CLK_TOP_USB20_SEL               90
102 #define CLK_TOP_USB30_SEL               91
103 #define CLK_TOP_MSDC50_0_H_SEL          92
104 #define CLK_TOP_MSDC50_0_SEL            93
105 #define CLK_TOP_MSDC30_1_SEL            94
106 #define CLK_TOP_MSDC30_2_SEL            95
107 #define CLK_TOP_MSDC30_3_SEL            96
108 #define CLK_TOP_AUDIO_SEL               97
109 #define CLK_TOP_AUD_INTBUS_SEL          98
110 #define CLK_TOP_PMICSPI_SEL             99
111 #define CLK_TOP_SCP_SEL                 100
112 #define CLK_TOP_MJC_SEL                 101
113 #define CLK_TOP_DPI0_SEL                102
114 #define CLK_TOP_IRDA_SEL                103
115 #define CLK_TOP_CCI400_SEL              104
116 #define CLK_TOP_AUD_1_SEL               105
117 #define CLK_TOP_AUD_2_SEL               106
118 #define CLK_TOP_MEM_MFG_IN_SEL          107
119 #define CLK_TOP_AXI_MFG_IN_SEL          108
120 #define CLK_TOP_SCAM_SEL                109
121 #define CLK_TOP_I2S0_M_SEL              110
122 #define CLK_TOP_I2S1_M_SEL              111
123 #define CLK_TOP_I2S2_M_SEL              112
124 #define CLK_TOP_I2S3_M_SEL              113
125 #define CLK_TOP_I2S3_B_SEL              114
126 #define CLK_TOP_APLL1_DIV0              115
127 #define CLK_TOP_APLL1_DIV1              116
128 #define CLK_TOP_APLL1_DIV2              117
129 #define CLK_TOP_APLL1_DIV3              118
130 #define CLK_TOP_APLL1_DIV4              119
131 #define CLK_TOP_APLL1_DIV5              120
132 #define CLK_TOP_APLL2_DIV0              121
133 #define CLK_TOP_APLL2_DIV1              122
134 #define CLK_TOP_APLL2_DIV2              123
135 #define CLK_TOP_APLL2_DIV3              124
136 #define CLK_TOP_APLL2_DIV4              125
137 #define CLK_TOP_APLL2_DIV5              126
138 #define CLK_TOP_NR_CLK                  127
139
140 /* APMIXED_SYS */
141 #define CLK_APMIXED_ARMCA53PLL          0
142 #define CLK_APMIXED_MAINPLL             1
143 #define CLK_APMIXED_UNIVPLL             2
144 #define CLK_APMIXED_MMPLL               3
145 #define CLK_APMIXED_MSDCPLL             4
146 #define CLK_APMIXED_VENCPLL             5
147 #define CLK_APMIXED_TVDPLL              6
148 #define CLK_APMIXED_MPLL                7
149 #define CLK_APMIXED_VCODECPLL           8
150 #define CLK_APMIXED_APLL1               9
151 #define CLK_APMIXED_APLL2               10
152 #define CLK_APMIXED_REF2USB_TX          11
153 #define CLK_APMIXED_NR_CLK              12
154
155 /* INFRA_SYS */
156 #define CLK_INFRA_DBGCLK                0
157 #define CLK_INFRA_SMI                   1
158 #define CLK_INFRA_AUDIO                 2
159 #define CLK_INFRA_GCE                   3
160 #define CLK_INFRA_L2C_SRAM              4
161 #define CLK_INFRA_M4U                   5
162 #define CLK_INFRA_MD1MCU                6
163 #define CLK_INFRA_MD1BUS                7
164 #define CLK_INFRA_MD1DBB                8
165 #define CLK_INFRA_DEVICE_APC            9
166 #define CLK_INFRA_TRNG                  10
167 #define CLK_INFRA_MD1LTE                11
168 #define CLK_INFRA_CPUM                  12
169 #define CLK_INFRA_KP                    13
170 #define CLK_INFRA_CA53_C0_SEL           14
171 #define CLK_INFRA_CA53_C1_SEL           15
172 #define CLK_INFRA_NR_CLK                16
173
174 /* PERI_SYS */
175 #define CLK_PERI_NFI                    0
176 #define CLK_PERI_THERM                  1
177 #define CLK_PERI_PWM1                   2
178 #define CLK_PERI_PWM2                   3
179 #define CLK_PERI_PWM3                   4
180 #define CLK_PERI_PWM4                   5
181 #define CLK_PERI_PWM5                   6
182 #define CLK_PERI_PWM6                   7
183 #define CLK_PERI_PWM7                   8
184 #define CLK_PERI_PWM                    9
185 #define CLK_PERI_USB0                   10
186 #define CLK_PERI_USB1                   11
187 #define CLK_PERI_AP_DMA                 12
188 #define CLK_PERI_MSDC30_0               13
189 #define CLK_PERI_MSDC30_1               14
190 #define CLK_PERI_MSDC30_2               15
191 #define CLK_PERI_MSDC30_3               16
192 #define CLK_PERI_NLI_ARB                17
193 #define CLK_PERI_IRDA                   18
194 #define CLK_PERI_UART0                  19
195 #define CLK_PERI_UART1                  20
196 #define CLK_PERI_UART2                  21
197 #define CLK_PERI_UART3                  22
198 #define CLK_PERI_I2C0                   23
199 #define CLK_PERI_I2C1                   24
200 #define CLK_PERI_I2C2                   25
201 #define CLK_PERI_I2C3                   26
202 #define CLK_PERI_I2C4                   27
203 #define CLK_PERI_AUXADC                 28
204 #define CLK_PERI_SPI0                   29
205 #define CLK_PERI_UART0_SEL              30
206 #define CLK_PERI_UART1_SEL              31
207 #define CLK_PERI_UART2_SEL              32
208 #define CLK_PERI_UART3_SEL              33
209 #define CLK_PERI_NR_CLK                 34
210
211 /* MFG */
212 #define CLK_MFG_BAXI                    0
213 #define CLK_MFG_BMEM                    1
214 #define CLK_MFG_BG3D                    2
215 #define CLK_MFG_B26M                    3
216 #define CLK_MFG_NR_CLK                  4
217
218 /* MM_SYS */
219 #define CLK_MM_SMI_COMMON               0
220 #define CLK_MM_SMI_LARB0                1
221 #define CLK_MM_CAM_MDP                  2
222 #define CLK_MM_MDP_RDMA0                3
223 #define CLK_MM_MDP_RDMA1                4
224 #define CLK_MM_MDP_RSZ0                 5
225 #define CLK_MM_MDP_RSZ1                 6
226 #define CLK_MM_MDP_RSZ2                 7
227 #define CLK_MM_MDP_TDSHP0               8
228 #define CLK_MM_MDP_TDSHP1               9
229 #define CLK_MM_MDP_CROP                 10
230 #define CLK_MM_MDP_WDMA                 11
231 #define CLK_MM_MDP_WROT0                12
232 #define CLK_MM_MDP_WROT1                13
233 #define CLK_MM_FAKE_ENG                 14
234 #define CLK_MM_MUTEX_32K                15
235 #define CLK_MM_DISP_OVL0                16
236 #define CLK_MM_DISP_OVL1                17
237 #define CLK_MM_DISP_RDMA0               18
238 #define CLK_MM_DISP_RDMA1               19
239 #define CLK_MM_DISP_RDMA2               20
240 #define CLK_MM_DISP_WDMA0               21
241 #define CLK_MM_DISP_WDMA1               22
242 #define CLK_MM_DISP_COLOR0              23
243 #define CLK_MM_DISP_COLOR1              24
244 #define CLK_MM_DISP_AAL                 25
245 #define CLK_MM_DISP_GAMMA               26
246 #define CLK_MM_DISP_UFOE                27
247 #define CLK_MM_DISP_SPLIT0              28
248 #define CLK_MM_DISP_SPLIT1              29
249 #define CLK_MM_DISP_MERGE               30
250 #define CLK_MM_DISP_OD                  31
251 #define CLK_MM_DISP_PWM0MM              32
252 #define CLK_MM_DISP_PWM026M             33
253 #define CLK_MM_DISP_PWM1MM              34
254 #define CLK_MM_DISP_PWM126M             35
255 #define CLK_MM_DSI0_ENGINE              36
256 #define CLK_MM_DSI0_DIGITAL             37
257 #define CLK_MM_DSI1_ENGINE              38
258 #define CLK_MM_DSI1_DIGITAL             39
259 #define CLK_MM_DPI_PIXEL                40
260 #define CLK_MM_DPI_ENGINE               41
261 #define CLK_MM_NR_CLK                   42
262
263 /* VDEC_SYS */
264 #define CLK_VDEC_CKEN                   0
265 #define CLK_VDEC_LARB_CKEN              1
266 #define CLK_VDEC_NR_CLK                 2
267
268 /* VENC_SYS */
269 #define CLK_VENC_LARB                   0
270 #define CLK_VENC_VENC                   1
271 #define CLK_VENC_JPGENC                 2
272 #define CLK_VENC_JPGDEC                 3
273 #define CLK_VENC_NR_CLK                 4
274
275 #endif /* _DT_BINDINGS_CLK_MT6795_H */