1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
6 #ifndef __DT_BINDINGS_CLOCK_IMX1_H
7 #define __DT_BINDINGS_CLOCK_IMX1_H
9 #define IMX1_CLK_DUMMY 0
10 #define IMX1_CLK_CLK32 1
11 #define IMX1_CLK_CLK16M_EXT 2
12 #define IMX1_CLK_CLK16M 3
13 #define IMX1_CLK_CLK32_PREMULT 4
14 #define IMX1_CLK_PREM 5
15 #define IMX1_CLK_MPLL 6
16 #define IMX1_CLK_MPLL_GATE 7
17 #define IMX1_CLK_SPLL 8
18 #define IMX1_CLK_SPLL_GATE 9
19 #define IMX1_CLK_MCU 10
20 #define IMX1_CLK_FCLK 11
21 #define IMX1_CLK_HCLK 12
22 #define IMX1_CLK_CLK48M 13
23 #define IMX1_CLK_PER1 14
24 #define IMX1_CLK_PER2 15
25 #define IMX1_CLK_PER3 16
26 #define IMX1_CLK_CLKO 17
27 #define IMX1_CLK_UART3_GATE 18
28 #define IMX1_CLK_SSI2_GATE 19
29 #define IMX1_CLK_BROM_GATE 20
30 #define IMX1_CLK_DMA_GATE 21
31 #define IMX1_CLK_CSI_GATE 22
32 #define IMX1_CLK_MMA_GATE 23
33 #define IMX1_CLK_USBD_GATE 24
34 #define IMX1_CLK_MAX 25