include/dt-bindings/clock/dra7.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright 2017 Texas Instruments, Inc.
   4  */
   5 #ifndef __DT_BINDINGS_CLK_DRA7_H
   6 #define __DT_BINDINGS_CLK_DRA7_H
   7
   8 #define DRA7_CLKCTRL_OFFSET     0x20
   9 #define DRA7_CLKCTRL_INDEX(offset)      ((offset) - DRA7_CLKCTRL_OFFSET)
  10
  11 /* mpu clocks */
  12 #define DRA7_MPU_MPU_CLKCTRL    DRA7_CLKCTRL_INDEX(0x20)
  13
  14 /* dsp1 clocks */
  15 #define DRA7_DSP1_MMU0_DSP1_CLKCTRL     DRA7_CLKCTRL_INDEX(0x20)
  16
  17 /* ipu1 clocks */
  18 #define DRA7_IPU1_MMU_IPU1_CLKCTRL      DRA7_CLKCTRL_INDEX(0x20)
  19
  20 /* ipu clocks */
  21 #define DRA7_IPU_CLKCTRL_OFFSET 0x50
  22 #define DRA7_IPU_CLKCTRL_INDEX(offset)  ((offset) - DRA7_IPU_CLKCTRL_OFFSET)
  23 #define DRA7_IPU_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50)
  24 #define DRA7_IPU_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58)
  25 #define DRA7_IPU_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60)
  26 #define DRA7_IPU_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68)
  27 #define DRA7_IPU_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70)
  28 #define DRA7_IPU_I2C5_CLKCTRL   DRA7_IPU_CLKCTRL_INDEX(0x78)
  29 #define DRA7_IPU_UART6_CLKCTRL  DRA7_IPU_CLKCTRL_INDEX(0x80)
  30
  31 /* dsp2 clocks */
  32 #define DRA7_DSP2_MMU0_DSP2_CLKCTRL     DRA7_CLKCTRL_INDEX(0x20)
  33
  34 /* rtc clocks */
  35 #define DRA7_RTC_RTCSS_CLKCTRL  DRA7_CLKCTRL_INDEX(0x44)
  36
  37 /* vip clocks */
  38 #define DRA7_CAM_VIP1_CLKCTRL   DRA7_CLKCTRL_INDEX(0x20)
  39 #define DRA7_CAM_VIP2_CLKCTRL   DRA7_CLKCTRL_INDEX(0x28)
  40 #define DRA7_CAM_VIP3_CLKCTRL   DRA7_CLKCTRL_INDEX(0x30)
  41
  42 /* vpe clocks */
  43 #define DRA7_VPE_CLKCTRL_OFFSET 0x60
  44 #define DRA7_VPE_CLKCTRL_INDEX(offset)  ((offset) - DRA7_VPE_CLKCTRL_OFFSET)
  45 #define DRA7_VPE_VPE_CLKCTRL    DRA7_VPE_CLKCTRL_INDEX(0x64)
  46
  47 /* coreaon clocks */
  48 #define DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL    DRA7_CLKCTRL_INDEX(0x28)
  49 #define DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL   DRA7_CLKCTRL_INDEX(0x38)
  50
  51 /* l3main1 clocks */
  52 #define DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL  DRA7_CLKCTRL_INDEX(0x20)
  53 #define DRA7_L3MAIN1_GPMC_CLKCTRL       DRA7_CLKCTRL_INDEX(0x28)
  54 #define DRA7_L3MAIN1_TPCC_CLKCTRL       DRA7_CLKCTRL_INDEX(0x70)
  55 #define DRA7_L3MAIN1_TPTC0_CLKCTRL      DRA7_CLKCTRL_INDEX(0x78)
  56 #define DRA7_L3MAIN1_TPTC1_CLKCTRL      DRA7_CLKCTRL_INDEX(0x80)
  57 #define DRA7_L3MAIN1_VCP1_CLKCTRL       DRA7_CLKCTRL_INDEX(0x88)
  58 #define DRA7_L3MAIN1_VCP2_CLKCTRL       DRA7_CLKCTRL_INDEX(0x90)
  59
  60 /* ipu2 clocks */
  61 #define DRA7_IPU2_MMU_IPU2_CLKCTRL      DRA7_CLKCTRL_INDEX(0x20)
  62
  63 /* dma clocks */
  64 #define DRA7_DMA_DMA_SYSTEM_CLKCTRL     DRA7_CLKCTRL_INDEX(0x20)
  65
  66 /* emif clocks */
  67 #define DRA7_EMIF_DMM_CLKCTRL   DRA7_CLKCTRL_INDEX(0x20)
  68
  69 /* atl clocks */
  70 #define DRA7_ATL_CLKCTRL_OFFSET 0x0
  71 #define DRA7_ATL_CLKCTRL_INDEX(offset)  ((offset) - DRA7_ATL_CLKCTRL_OFFSET)
  72 #define DRA7_ATL_ATL_CLKCTRL    DRA7_ATL_CLKCTRL_INDEX(0x0)
  73
  74 /* l4cfg clocks */
  75 #define DRA7_L4CFG_L4_CFG_CLKCTRL       DRA7_CLKCTRL_INDEX(0x20)
  76 #define DRA7_L4CFG_SPINLOCK_CLKCTRL     DRA7_CLKCTRL_INDEX(0x28)
  77 #define DRA7_L4CFG_MAILBOX1_CLKCTRL     DRA7_CLKCTRL_INDEX(0x30)
  78 #define DRA7_L4CFG_MAILBOX2_CLKCTRL     DRA7_CLKCTRL_INDEX(0x48)
  79 #define DRA7_L4CFG_MAILBOX3_CLKCTRL     DRA7_CLKCTRL_INDEX(0x50)
  80 #define DRA7_L4CFG_MAILBOX4_CLKCTRL     DRA7_CLKCTRL_INDEX(0x58)
  81 #define DRA7_L4CFG_MAILBOX5_CLKCTRL     DRA7_CLKCTRL_INDEX(0x60)
  82 #define DRA7_L4CFG_MAILBOX6_CLKCTRL     DRA7_CLKCTRL_INDEX(0x68)
  83 #define DRA7_L4CFG_MAILBOX7_CLKCTRL     DRA7_CLKCTRL_INDEX(0x70)
  84 #define DRA7_L4CFG_MAILBOX8_CLKCTRL     DRA7_CLKCTRL_INDEX(0x78)
  85 #define DRA7_L4CFG_MAILBOX9_CLKCTRL     DRA7_CLKCTRL_INDEX(0x80)
  86 #define DRA7_L4CFG_MAILBOX10_CLKCTRL    DRA7_CLKCTRL_INDEX(0x88)
  87 #define DRA7_L4CFG_MAILBOX11_CLKCTRL    DRA7_CLKCTRL_INDEX(0x90)
  88 #define DRA7_L4CFG_MAILBOX12_CLKCTRL    DRA7_CLKCTRL_INDEX(0x98)
  89 #define DRA7_L4CFG_MAILBOX13_CLKCTRL    DRA7_CLKCTRL_INDEX(0xa0)
  90
  91 /* l3instr clocks */
  92 #define DRA7_L3INSTR_L3_MAIN_2_CLKCTRL  DRA7_CLKCTRL_INDEX(0x20)
  93 #define DRA7_L3INSTR_L3_INSTR_CLKCTRL   DRA7_CLKCTRL_INDEX(0x28)
  94
  95 /* iva clocks */
  96 #define DRA7_IVA_CLKCTRL                DRA7_CLKCTRL_INDEX(0x20)
  97 #define DRA7_SL2IF_CLKCTRL              DRA7_CLKCTRL_INDEX(0x28)
  98
  99 /* dss clocks */
 100 #define DRA7_DSS_DSS_CORE_CLKCTRL       DRA7_CLKCTRL_INDEX(0x20)
 101 #define DRA7_DSS_BB2D_CLKCTRL   DRA7_CLKCTRL_INDEX(0x30)
 102
 103 /* gpu clocks */
 104 #define DRA7_GPU_CLKCTRL                DRA7_CLKCTRL_INDEX(0x20)
 105
 106 /* l3init clocks */
 107 #define DRA7_L3INIT_MMC1_CLKCTRL        DRA7_CLKCTRL_INDEX(0x28)
 108 #define DRA7_L3INIT_MMC2_CLKCTRL        DRA7_CLKCTRL_INDEX(0x30)
 109 #define DRA7_L3INIT_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40)
 110 #define DRA7_L3INIT_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48)
 111 #define DRA7_L3INIT_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
 112 #define DRA7_L3INIT_SATA_CLKCTRL        DRA7_CLKCTRL_INDEX(0x88)
 113 #define DRA7_L3INIT_OCP2SCP1_CLKCTRL    DRA7_CLKCTRL_INDEX(0xe0)
 114 #define DRA7_L3INIT_OCP2SCP3_CLKCTRL    DRA7_CLKCTRL_INDEX(0xe8)
 115 #define DRA7_L3INIT_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0)
 116
 117 /* pcie clocks */
 118 #define DRA7_PCIE_CLKCTRL_OFFSET        0xb0
 119 #define DRA7_PCIE_CLKCTRL_INDEX(offset) ((offset) - DRA7_PCIE_CLKCTRL_OFFSET)
 120 #define DRA7_PCIE_PCIE1_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb0)
 121 #define DRA7_PCIE_PCIE2_CLKCTRL DRA7_PCIE_CLKCTRL_INDEX(0xb8)
 122
 123 /* gmac clocks */
 124 #define DRA7_GMAC_CLKCTRL_OFFSET        0xd0
 125 #define DRA7_GMAC_CLKCTRL_INDEX(offset) ((offset) - DRA7_GMAC_CLKCTRL_OFFSET)
 126 #define DRA7_GMAC_GMAC_CLKCTRL  DRA7_GMAC_CLKCTRL_INDEX(0xd0)
 127
 128 /* l4per clocks */
 129 #define DRA7_L4PER_CLKCTRL_OFFSET       0x28
 130 #define DRA7_L4PER_CLKCTRL_INDEX(offset)        ((offset) - DRA7_L4PER_CLKCTRL_OFFSET)
 131 #define DRA7_L4PER_TIMER10_CLKCTRL      DRA7_L4PER_CLKCTRL_INDEX(0x28)
 132 #define DRA7_L4PER_TIMER11_CLKCTRL      DRA7_L4PER_CLKCTRL_INDEX(0x30)
 133 #define DRA7_L4PER_TIMER2_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0x38)
 134 #define DRA7_L4PER_TIMER3_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0x40)
 135 #define DRA7_L4PER_TIMER4_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0x48)
 136 #define DRA7_L4PER_TIMER9_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0x50)
 137 #define DRA7_L4PER_ELM_CLKCTRL  DRA7_L4PER_CLKCTRL_INDEX(0x58)
 138 #define DRA7_L4PER_GPIO2_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x60)
 139 #define DRA7_L4PER_GPIO3_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x68)
 140 #define DRA7_L4PER_GPIO4_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x70)
 141 #define DRA7_L4PER_GPIO5_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x78)
 142 #define DRA7_L4PER_GPIO6_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x80)
 143 #define DRA7_L4PER_HDQ1W_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x88)
 144 #define DRA7_L4PER_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0)
 145 #define DRA7_L4PER_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8)
 146 #define DRA7_L4PER_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0)
 147 #define DRA7_L4PER_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8)
 148 #define DRA7_L4PER_L4_PER1_CLKCTRL      DRA7_L4PER_CLKCTRL_INDEX(0xc0)
 149 #define DRA7_L4PER_MCSPI1_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0xf0)
 150 #define DRA7_L4PER_MCSPI2_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0xf8)
 151 #define DRA7_L4PER_MCSPI3_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0x100)
 152 #define DRA7_L4PER_MCSPI4_CLKCTRL       DRA7_L4PER_CLKCTRL_INDEX(0x108)
 153 #define DRA7_L4PER_GPIO7_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x110)
 154 #define DRA7_L4PER_GPIO8_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x118)
 155 #define DRA7_L4PER_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120)
 156 #define DRA7_L4PER_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128)
 157 #define DRA7_L4PER_UART1_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x140)
 158 #define DRA7_L4PER_UART2_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x148)
 159 #define DRA7_L4PER_UART3_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x150)
 160 #define DRA7_L4PER_UART4_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x158)
 161 #define DRA7_L4PER_UART5_CLKCTRL        DRA7_L4PER_CLKCTRL_INDEX(0x170)
 162
 163 /* l4sec clocks */
 164 #define DRA7_L4SEC_CLKCTRL_OFFSET       0x1a0
 165 #define DRA7_L4SEC_CLKCTRL_INDEX(offset)        ((offset) - DRA7_L4SEC_CLKCTRL_OFFSET)
 166 #define DRA7_L4SEC_AES1_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a0)
 167 #define DRA7_L4SEC_AES2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1a8)
 168 #define DRA7_L4SEC_DES_CLKCTRL  DRA7_L4SEC_CLKCTRL_INDEX(0x1b0)
 169 #define DRA7_L4SEC_RNG_CLKCTRL  DRA7_L4SEC_CLKCTRL_INDEX(0x1c0)
 170 #define DRA7_L4SEC_SHAM_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1c8)
 171 #define DRA7_L4SEC_SHAM2_CLKCTRL DRA7_L4SEC_CLKCTRL_INDEX(0x1f8)
 172
 173 /* l4per2 clocks */
 174 #define DRA7_L4PER2_CLKCTRL_OFFSET      0xc
 175 #define DRA7_L4PER2_CLKCTRL_INDEX(offset)       ((offset) - DRA7_L4PER2_CLKCTRL_OFFSET)
 176 #define DRA7_L4PER2_L4_PER2_CLKCTRL     DRA7_L4PER2_CLKCTRL_INDEX(0xc)
 177 #define DRA7_L4PER2_PRUSS1_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x18)
 178 #define DRA7_L4PER2_PRUSS2_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x20)
 179 #define DRA7_L4PER2_EPWMSS1_CLKCTRL     DRA7_L4PER2_CLKCTRL_INDEX(0x90)
 180 #define DRA7_L4PER2_EPWMSS2_CLKCTRL     DRA7_L4PER2_CLKCTRL_INDEX(0x98)
 181 #define DRA7_L4PER2_EPWMSS0_CLKCTRL     DRA7_L4PER2_CLKCTRL_INDEX(0xc4)
 182 #define DRA7_L4PER2_QSPI_CLKCTRL        DRA7_L4PER2_CLKCTRL_INDEX(0x138)
 183 #define DRA7_L4PER2_MCASP2_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x160)
 184 #define DRA7_L4PER2_MCASP3_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x168)
 185 #define DRA7_L4PER2_MCASP5_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x178)
 186 #define DRA7_L4PER2_MCASP8_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x190)
 187 #define DRA7_L4PER2_MCASP4_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x198)
 188 #define DRA7_L4PER2_UART7_CLKCTRL       DRA7_L4PER2_CLKCTRL_INDEX(0x1d0)
 189 #define DRA7_L4PER2_UART8_CLKCTRL       DRA7_L4PER2_CLKCTRL_INDEX(0x1e0)
 190 #define DRA7_L4PER2_UART9_CLKCTRL       DRA7_L4PER2_CLKCTRL_INDEX(0x1e8)
 191 #define DRA7_L4PER2_DCAN2_CLKCTRL       DRA7_L4PER2_CLKCTRL_INDEX(0x1f0)
 192 #define DRA7_L4PER2_MCASP6_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x204)
 193 #define DRA7_L4PER2_MCASP7_CLKCTRL      DRA7_L4PER2_CLKCTRL_INDEX(0x208)
 194
 195 /* l4per3 clocks */
 196 #define DRA7_L4PER3_CLKCTRL_OFFSET      0x14
 197 #define DRA7_L4PER3_CLKCTRL_INDEX(offset)       ((offset) - DRA7_L4PER3_CLKCTRL_OFFSET)
 198 #define DRA7_L4PER3_L4_PER3_CLKCTRL     DRA7_L4PER3_CLKCTRL_INDEX(0x14)
 199 #define DRA7_L4PER3_TIMER13_CLKCTRL     DRA7_L4PER3_CLKCTRL_INDEX(0xc8)
 200 #define DRA7_L4PER3_TIMER14_CLKCTRL     DRA7_L4PER3_CLKCTRL_INDEX(0xd0)
 201 #define DRA7_L4PER3_TIMER15_CLKCTRL     DRA7_L4PER3_CLKCTRL_INDEX(0xd8)
 202 #define DRA7_L4PER3_TIMER16_CLKCTRL     DRA7_L4PER3_CLKCTRL_INDEX(0x130)
 203
 204 /* wkupaon clocks */
 205 #define DRA7_WKUPAON_L4_WKUP_CLKCTRL    DRA7_CLKCTRL_INDEX(0x20)
 206 #define DRA7_WKUPAON_WD_TIMER2_CLKCTRL  DRA7_CLKCTRL_INDEX(0x30)
 207 #define DRA7_WKUPAON_GPIO1_CLKCTRL      DRA7_CLKCTRL_INDEX(0x38)
 208 #define DRA7_WKUPAON_TIMER1_CLKCTRL     DRA7_CLKCTRL_INDEX(0x40)
 209 #define DRA7_WKUPAON_TIMER12_CLKCTRL    DRA7_CLKCTRL_INDEX(0x48)
 210 #define DRA7_WKUPAON_COUNTER_32K_CLKCTRL        DRA7_CLKCTRL_INDEX(0x50)
 211 #define DRA7_WKUPAON_UART10_CLKCTRL     DRA7_CLKCTRL_INDEX(0x80)
 212 #define DRA7_WKUPAON_DCAN1_CLKCTRL      DRA7_CLKCTRL_INDEX(0x88)
 213 #define DRA7_WKUPAON_ADC_CLKCTRL        DRA7_CLKCTRL_INDEX(0xa0)
 214
 215 #endif