include/dt-bindings/clock/amlogic,s4-peripherals-clkc.h

   1 /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
   2 /*
   3  * Copyright (c) 2022-2023 Amlogic, Inc. All rights reserved.
   4  * Author: Yu Tu <yu.tu@amlogic.com>
   5  */
   6
   7 #ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H
   8 #define _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H
   9
  10 #define CLKID_RTC_32K_CLKIN             0
  11 #define CLKID_RTC_32K_DIV               1
  12 #define CLKID_RTC_32K_SEL               2
  13 #define CLKID_RTC_32K_XATL              3
  14 #define CLKID_RTC                       4
  15 #define CLKID_SYS_CLK_B_SEL             5
  16 #define CLKID_SYS_CLK_B_DIV             6
  17 #define CLKID_SYS_CLK_B                 7
  18 #define CLKID_SYS_CLK_A_SEL             8
  19 #define CLKID_SYS_CLK_A_DIV             9
  20 #define CLKID_SYS_CLK_A                 10
  21 #define CLKID_SYS                       11
  22 #define CLKID_CECA_32K_CLKIN            12
  23 #define CLKID_CECA_32K_DIV              13
  24 #define CLKID_CECA_32K_SEL_PRE          14
  25 #define CLKID_CECA_32K_SEL              15
  26 #define CLKID_CECA_32K_CLKOUT           16
  27 #define CLKID_CECB_32K_CLKIN            17
  28 #define CLKID_CECB_32K_DIV              18
  29 #define CLKID_CECB_32K_SEL_PRE          19
  30 #define CLKID_CECB_32K_SEL              20
  31 #define CLKID_CECB_32K_CLKOUT           21
  32 #define CLKID_SC_CLK_SEL                22
  33 #define CLKID_SC_CLK_DIV                23
  34 #define CLKID_SC                        24
  35 #define CLKID_12_24M                    25
  36 #define CLKID_12M_CLK_DIV               26
  37 #define CLKID_12_24M_CLK_SEL            27
  38 #define CLKID_VID_PLL_DIV               28
  39 #define CLKID_VID_PLL_SEL               29
  40 #define CLKID_VID_PLL                   30
  41 #define CLKID_VCLK_SEL                  31
  42 #define CLKID_VCLK2_SEL                 32
  43 #define CLKID_VCLK_INPUT                33
  44 #define CLKID_VCLK2_INPUT               34
  45 #define CLKID_VCLK_DIV                  35
  46 #define CLKID_VCLK2_DIV                 36
  47 #define CLKID_VCLK                      37
  48 #define CLKID_VCLK2                     38
  49 #define CLKID_VCLK_DIV1                 39
  50 #define CLKID_VCLK_DIV2_EN              40
  51 #define CLKID_VCLK_DIV4_EN              41
  52 #define CLKID_VCLK_DIV6_EN              42
  53 #define CLKID_VCLK_DIV12_EN             43
  54 #define CLKID_VCLK2_DIV1                44
  55 #define CLKID_VCLK2_DIV2_EN             45
  56 #define CLKID_VCLK2_DIV4_EN             46
  57 #define CLKID_VCLK2_DIV6_EN             47
  58 #define CLKID_VCLK2_DIV12_EN            48
  59 #define CLKID_VCLK_DIV2                 49
  60 #define CLKID_VCLK_DIV4                 50
  61 #define CLKID_VCLK_DIV6                 51
  62 #define CLKID_VCLK_DIV12                52
  63 #define CLKID_VCLK2_DIV2                53
  64 #define CLKID_VCLK2_DIV4                54
  65 #define CLKID_VCLK2_DIV6                55
  66 #define CLKID_VCLK2_DIV12               56
  67 #define CLKID_CTS_ENCI_SEL              57
  68 #define CLKID_CTS_ENCP_SEL              58
  69 #define CLKID_CTS_VDAC_SEL              59
  70 #define CLKID_HDMI_TX_SEL               60
  71 #define CLKID_CTS_ENCI                  61
  72 #define CLKID_CTS_ENCP                  62
  73 #define CLKID_CTS_VDAC                  63
  74 #define CLKID_HDMI_TX                   64
  75 #define CLKID_HDMI_SEL                  65
  76 #define CLKID_HDMI_DIV                  66
  77 #define CLKID_HDMI                      67
  78 #define CLKID_TS_CLK_DIV                68
  79 #define CLKID_TS                        69
  80 #define CLKID_MALI_0_SEL                70
  81 #define CLKID_MALI_0_DIV                71
  82 #define CLKID_MALI_0                    72
  83 #define CLKID_MALI_1_SEL                73
  84 #define CLKID_MALI_1_DIV                74
  85 #define CLKID_MALI_1                    75
  86 #define CLKID_MALI_SEL                  76
  87 #define CLKID_VDEC_P0_SEL               77
  88 #define CLKID_VDEC_P0_DIV               78
  89 #define CLKID_VDEC_P0                   79
  90 #define CLKID_VDEC_P1_SEL               80
  91 #define CLKID_VDEC_P1_DIV               81
  92 #define CLKID_VDEC_P1                   82
  93 #define CLKID_VDEC_SEL                  83
  94 #define CLKID_HEVCF_P0_SEL              84
  95 #define CLKID_HEVCF_P0_DIV              85
  96 #define CLKID_HEVCF_P0                  86
  97 #define CLKID_HEVCF_P1_SEL              87
  98 #define CLKID_HEVCF_P1_DIV              88
  99 #define CLKID_HEVCF_P1                  89
 100 #define CLKID_HEVCF_SEL                 90
 101 #define CLKID_VPU_0_SEL                 91
 102 #define CLKID_VPU_0_DIV                 92
 103 #define CLKID_VPU_0                     93
 104 #define CLKID_VPU_1_SEL                 94
 105 #define CLKID_VPU_1_DIV                 95
 106 #define CLKID_VPU_1                     96
 107 #define CLKID_VPU                       97
 108 #define CLKID_VPU_CLKB_TMP_SEL          98
 109 #define CLKID_VPU_CLKB_TMP_DIV          99
 110 #define CLKID_VPU_CLKB_TMP              100
 111 #define CLKID_VPU_CLKB_DIV              101
 112 #define CLKID_VPU_CLKB                  102
 113 #define CLKID_VPU_CLKC_P0_SEL           103
 114 #define CLKID_VPU_CLKC_P0_DIV           104
 115 #define CLKID_VPU_CLKC_P0               105
 116 #define CLKID_VPU_CLKC_P1_SEL           106
 117 #define CLKID_VPU_CLKC_P1_DIV           107
 118 #define CLKID_VPU_CLKC_P1               108
 119 #define CLKID_VPU_CLKC_SEL              109
 120 #define CLKID_VAPB_0_SEL                110
 121 #define CLKID_VAPB_0_DIV                111
 122 #define CLKID_VAPB_0                    112
 123 #define CLKID_VAPB_1_SEL                113
 124 #define CLKID_VAPB_1_DIV                114
 125 #define CLKID_VAPB_1                    115
 126 #define CLKID_VAPB                      116
 127 #define CLKID_GE2D                      117
 128 #define CLKID_VDIN_MEAS_SEL             118
 129 #define CLKID_VDIN_MEAS_DIV             119
 130 #define CLKID_VDIN_MEAS                 120
 131 #define CLKID_SD_EMMC_C_CLK_SEL         121
 132 #define CLKID_SD_EMMC_C_CLK_DIV         122
 133 #define CLKID_SD_EMMC_C                 123
 134 #define CLKID_SD_EMMC_A_CLK_SEL         124
 135 #define CLKID_SD_EMMC_A_CLK_DIV         125
 136 #define CLKID_SD_EMMC_A                 126
 137 #define CLKID_SD_EMMC_B_CLK_SEL         127
 138 #define CLKID_SD_EMMC_B_CLK_DIV         128
 139 #define CLKID_SD_EMMC_B                 129
 140 #define CLKID_SPICC0_SEL                130
 141 #define CLKID_SPICC0_DIV                131
 142 #define CLKID_SPICC0_EN                 132
 143 #define CLKID_PWM_A_SEL                 133
 144 #define CLKID_PWM_A_DIV                 134
 145 #define CLKID_PWM_A                     135
 146 #define CLKID_PWM_B_SEL                 136
 147 #define CLKID_PWM_B_DIV                 137
 148 #define CLKID_PWM_B                     138
 149 #define CLKID_PWM_C_SEL                 139
 150 #define CLKID_PWM_C_DIV                 140
 151 #define CLKID_PWM_C                     141
 152 #define CLKID_PWM_D_SEL                 142
 153 #define CLKID_PWM_D_DIV                 143
 154 #define CLKID_PWM_D                     144
 155 #define CLKID_PWM_E_SEL                 145
 156 #define CLKID_PWM_E_DIV                 146
 157 #define CLKID_PWM_E                     147
 158 #define CLKID_PWM_F_SEL                 148
 159 #define CLKID_PWM_F_DIV                 149
 160 #define CLKID_PWM_F                     150
 161 #define CLKID_PWM_G_SEL                 151
 162 #define CLKID_PWM_G_DIV                 152
 163 #define CLKID_PWM_G                     153
 164 #define CLKID_PWM_H_SEL                 154
 165 #define CLKID_PWM_H_DIV                 155
 166 #define CLKID_PWM_H                     156
 167 #define CLKID_PWM_I_SEL                 157
 168 #define CLKID_PWM_I_DIV                 158
 169 #define CLKID_PWM_I                     159
 170 #define CLKID_PWM_J_SEL                 160
 171 #define CLKID_PWM_J_DIV                 161
 172 #define CLKID_PWM_J                     162
 173 #define CLKID_SARADC_SEL                163
 174 #define CLKID_SARADC_DIV                164
 175 #define CLKID_SARADC                    165
 176 #define CLKID_GEN_SEL                   166
 177 #define CLKID_GEN_DIV                   167
 178 #define CLKID_GEN                       168
 179 #define CLKID_DDR                       169
 180 #define CLKID_DOS                       170
 181 #define CLKID_ETHPHY                    171
 182 #define CLKID_MALI                      172
 183 #define CLKID_AOCPU                     173
 184 #define CLKID_AUCPU                     174
 185 #define CLKID_CEC                       175
 186 #define CLKID_SDEMMC_A                  176
 187 #define CLKID_SDEMMC_B                  177
 188 #define CLKID_NAND                      178
 189 #define CLKID_SMARTCARD                 179
 190 #define CLKID_ACODEC                    180
 191 #define CLKID_SPIFC                     181
 192 #define CLKID_MSR                       182
 193 #define CLKID_IR_CTRL                   183
 194 #define CLKID_AUDIO                     184
 195 #define CLKID_ETH                       185
 196 #define CLKID_UART_A                    186
 197 #define CLKID_UART_B                    187
 198 #define CLKID_UART_C                    188
 199 #define CLKID_UART_D                    189
 200 #define CLKID_UART_E                    190
 201 #define CLKID_AIFIFO                    191
 202 #define CLKID_TS_DDR                    192
 203 #define CLKID_TS_PLL                    193
 204 #define CLKID_G2D                       194
 205 #define CLKID_SPICC0                    195
 206 #define CLKID_SPICC1                    196
 207 #define CLKID_USB                       197
 208 #define CLKID_I2C_M_A                   198
 209 #define CLKID_I2C_M_B                   199
 210 #define CLKID_I2C_M_C                   200
 211 #define CLKID_I2C_M_D                   201
 212 #define CLKID_I2C_M_E                   202
 213 #define CLKID_HDMITX_APB                203
 214 #define CLKID_I2C_S_A                   204
 215 #define CLKID_USB1_TO_DDR               205
 216 #define CLKID_HDCP22                    206
 217 #define CLKID_MMC_APB                   207
 218 #define CLKID_RSA                       208
 219 #define CLKID_CPU_DEBUG                 209
 220 #define CLKID_VPU_INTR                  210
 221 #define CLKID_DEMOD                     211
 222 #define CLKID_SAR_ADC                   212
 223 #define CLKID_GIC                       213
 224 #define CLKID_PWM_AB                    214
 225 #define CLKID_PWM_CD                    215
 226 #define CLKID_PWM_EF                    216
 227 #define CLKID_PWM_GH                    217
 228 #define CLKID_PWM_IJ                    218
 229 #define CLKID_HDCP22_ESMCLK_SEL         219
 230 #define CLKID_HDCP22_ESMCLK_DIV         220
 231 #define CLKID_HDCP22_ESMCLK             221
 232 #define CLKID_HDCP22_SKPCLK_SEL         222
 233 #define CLKID_HDCP22_SKPCLK_DIV         223
 234 #define CLKID_HDCP22_SKPCLK             224
 235
 236 #endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PERIPHERALS_CLKC_H */