2 * Copyright © 2008 Keith Packard
4 * Permission to use, copy, modify, distribute, and sell this software and its
5 * documentation for any purpose is hereby granted without fee, provided that
6 * the above copyright notice appear in all copies and that both that copyright
7 * notice and this permission notice appear in supporting documentation, and
8 * that the name of the copyright holders not be used in advertising or
9 * publicity pertaining to distribution of the software without specific,
10 * written prior permission. The copyright holders make no representations
11 * about the suitability of this software for any purpose. It is provided "as
12 * is" without express or implied warranty.
14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
23 #ifndef _DRM_DP_HELPER_H_
24 #define _DRM_DP_HELPER_H_
26 #include <linux/delay.h>
27 #include <linux/i2c.h>
29 #include <drm/display/drm_dp.h>
30 #include <drm/drm_connector.h>
36 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
38 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
40 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
42 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
44 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
47 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
48 enum drm_dp_phy dp_phy, bool uhbr);
49 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
50 enum drm_dp_phy dp_phy, bool uhbr);
52 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
53 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
54 void drm_dp_lttpr_link_train_clock_recovery_delay(void);
55 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
56 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
57 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
58 const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
60 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux);
61 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],
63 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],
65 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
66 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]);
67 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]);
69 u8 drm_dp_link_rate_to_bw_code(int link_rate);
70 int drm_dp_bw_code_to_link_rate(u8 link_bw);
73 * struct drm_dp_vsc_sdp - drm DP VSC SDP
75 * This structure represents a DP VSC SDP of drm
76 * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and
77 * [Table 2-117: VSC SDP Payload for DB16 through DB18]
79 * @sdp_type: secondary-data packet type
80 * @revision: revision number
81 * @length: number of valid data bytes
82 * @pixelformat: pixel encoding format
83 * @colorimetry: colorimetry format
85 * @dynamic_range: dynamic range information
86 * @content_type: CTA-861-G defines content types and expected processing by a sink device
88 struct drm_dp_vsc_sdp {
89 unsigned char sdp_type;
90 unsigned char revision;
92 enum dp_pixelformat pixelformat;
93 enum dp_colorimetry colorimetry;
95 enum dp_dynamic_range dynamic_range;
96 enum dp_content_type content_type;
99 void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
100 const struct drm_dp_vsc_sdp *vsc);
102 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
105 drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
107 return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
111 drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
113 return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
117 drm_dp_enhanced_frame_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
119 return dpcd[DP_DPCD_REV] >= 0x11 &&
120 (dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
124 drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
126 return dpcd[DP_DPCD_REV] >= 0x11 &&
127 (dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
131 drm_dp_tps3_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
133 return dpcd[DP_DPCD_REV] >= 0x12 &&
134 dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED;
138 drm_dp_max_downspread(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
140 return dpcd[DP_DPCD_REV] >= 0x11 ||
141 dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5;
145 drm_dp_tps4_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
147 return dpcd[DP_DPCD_REV] >= 0x14 &&
148 dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED;
152 drm_dp_training_pattern_mask(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
154 return (dpcd[DP_DPCD_REV] >= 0x14) ? DP_TRAINING_PATTERN_MASK_1_4 :
155 DP_TRAINING_PATTERN_MASK;
159 drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
161 return dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT;
164 /* DP/eDP DSC support */
165 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
167 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
168 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE],
172 drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
174 return dsc_dpcd[DP_DSC_SUPPORT - DP_DSC_SUPPORT] &
175 DP_DSC_DECOMPRESSION_IS_SUPPORTED;
179 drm_edp_dsc_sink_output_bpp(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
181 return dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
182 (dsc_dpcd[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] &
183 DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK <<
184 DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT);
188 drm_dp_dsc_sink_max_slice_width(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
190 /* Max Slicewidth = Number of Pixels * 320 */
191 return dsc_dpcd[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] *
192 DP_DSC_SLICE_WIDTH_MULTIPLIER;
195 /* Forward Error Correction Support on DP 1.4 */
197 drm_dp_sink_supports_fec(const u8 fec_capable)
199 return fec_capable & DP_FEC_CAPABLE;
203 drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
205 return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
209 drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
211 return dpcd[DP_EDP_CONFIGURATION_CAP] &
212 DP_ALTERNATE_SCRAMBLER_RESET_CAP;
215 /* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
217 drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
219 return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
220 DP_MSA_TIMING_PAR_IGNORED;
224 * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support
225 * @edp_dpcd: The DPCD to check
227 * Note that currently this function will return %false for panels which support various DPCD
228 * backlight features but which require the brightness be set through PWM, and don't support setting
229 * the brightness level via the DPCD.
231 * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false
235 drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
237 return !!(edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP);
241 * DisplayPort AUX channel
245 * struct drm_dp_aux_msg - DisplayPort AUX channel transaction
246 * @address: address of the (first) register to access
247 * @request: contains the type of transaction (see DP_AUX_* macros)
248 * @reply: upon completion, contains the reply type of the transaction
249 * @buffer: pointer to a transmission or reception buffer
250 * @size: size of @buffer
252 struct drm_dp_aux_msg {
253 unsigned int address;
262 struct drm_connector;
265 * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
266 * @lock: mutex protecting this struct
267 * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
268 * @connector: the connector this CEC adapter is associated with
269 * @unregister_work: unregister the CEC adapter
271 struct drm_dp_aux_cec {
273 struct cec_adapter *adap;
274 struct drm_connector *connector;
275 struct delayed_work unregister_work;
279 * struct drm_dp_aux - DisplayPort AUX channel
281 * An AUX channel can also be used to transport I2C messages to a sink. A
282 * typical application of that is to access an EDID that's present in the sink
283 * device. The @transfer() function can also be used to execute such
284 * transactions. The drm_dp_aux_register() function registers an I2C adapter
285 * that can be passed to drm_probe_ddc(). Upon removal, drivers should call
286 * drm_dp_aux_unregister() to remove the I2C adapter. The I2C adapter uses long
287 * transfers by default; if a partial response is received, the adapter will
288 * drop down to the size given by the partial response for this transaction
293 * @name: user-visible name of this AUX channel and the
294 * I2C-over-AUX adapter.
296 * It's also used to specify the name of the I2C adapter. If set
297 * to %NULL, dev_name() of @dev will be used.
302 * @ddc: I2C adapter that can be used for I2C-over-AUX
305 struct i2c_adapter ddc;
308 * @dev: pointer to struct device that is the parent for this
314 * @drm_dev: pointer to the &drm_device that owns this AUX channel.
315 * Beware, this may be %NULL before drm_dp_aux_register() has been
318 * It should be set to the &drm_device that will be using this AUX
319 * channel as early as possible. For many graphics drivers this should
320 * happen before drm_dp_aux_init(), however it's perfectly fine to set
321 * this field later so long as it's assigned before calling
322 * drm_dp_aux_register().
324 struct drm_device *drm_dev;
327 * @crtc: backpointer to the crtc that is currently using this
330 struct drm_crtc *crtc;
333 * @hw_mutex: internal mutex used for locking transfers.
335 * Note that if the underlying hardware is shared among multiple
336 * channels, the driver needs to do additional locking to
337 * prevent concurrent access.
339 struct mutex hw_mutex;
342 * @crc_work: worker that captures CRCs for each frame
344 struct work_struct crc_work;
347 * @crc_count: counter of captured frame CRCs
352 * @transfer: transfers a message representing a single AUX
355 * This is a hardware-specific implementation of how
356 * transactions are executed that the drivers must provide.
358 * A pointer to a &drm_dp_aux_msg structure describing the
359 * transaction is passed into this function. Upon success, the
360 * implementation should return the number of payload bytes that
361 * were transferred, or a negative error-code on failure.
363 * Helpers will propagate these errors, with the exception of
364 * the %-EBUSY error, which causes a transaction to be retried.
365 * On a short, helpers will return %-EPROTO to make it simpler
366 * to check for failure.
368 * The @transfer() function must only modify the reply field of
369 * the &drm_dp_aux_msg structure. The retry logic and i2c
370 * helpers assume this is the case.
372 * Also note that this callback can be called no matter the
373 * state @dev is in and also no matter what state the panel is
376 * - If the @dev providing the AUX bus is currently unpowered then
377 * it will power itself up for the transfer.
379 * - If we're on eDP (using a drm_panel) and the panel is not in a
380 * state where it can respond (it's not powered or it's in a
381 * low power state) then this function may return an error, but
382 * not crash. It's up to the caller of this code to make sure that
383 * the panel is powered on if getting an error back is not OK. If a
384 * drm_panel driver is initiating a DP AUX transfer it may power
385 * itself up however it wants. All other code should ensure that
386 * the pre_enable() bridge chain (which eventually calls the
387 * drm_panel prepare function) has powered the panel.
389 ssize_t (*transfer)(struct drm_dp_aux *aux,
390 struct drm_dp_aux_msg *msg);
393 * @wait_hpd_asserted: wait for HPD to be asserted
395 * This is mainly useful for eDP panels drivers to wait for an eDP
396 * panel to finish powering on. This is an optional function.
398 * This function will efficiently wait for the HPD signal to be
399 * asserted. The `wait_us` parameter that is passed in says that we
400 * know that the HPD signal is expected to be asserted within `wait_us`
401 * microseconds. This function could wait for longer than `wait_us` if
402 * the logic in the DP controller has a long debouncing time. The
403 * important thing is that if this function returns success that the
404 * DP controller is ready to send AUX transactions.
406 * This function returns 0 if HPD was asserted or -ETIMEDOUT if time
407 * expired and HPD wasn't asserted. This function should not print
408 * timeout errors to the log.
410 * The semantics of this function are designed to match the
411 * readx_poll_timeout() function. That means a `wait_us` of 0 means
412 * to wait forever. Like readx_poll_timeout(), this function may sleep.
414 * NOTE: this function specifically reports the state of the HPD pin
415 * that's associated with the DP AUX channel. This is different from
416 * the HPD concept in much of the rest of DRM which is more about
417 * physical presence of a display. For eDP, for instance, a display is
418 * assumed always present even if the HPD pin is deasserted.
420 int (*wait_hpd_asserted)(struct drm_dp_aux *aux, unsigned long wait_us);
423 * @i2c_nack_count: Counts I2C NACKs, used for DP validation.
425 unsigned i2c_nack_count;
427 * @i2c_defer_count: Counts I2C DEFERs, used for DP validation.
429 unsigned i2c_defer_count;
431 * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
433 struct drm_dp_aux_cec cec;
435 * @is_remote: Is this AUX CH actually using sideband messaging.
440 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset);
441 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
442 void *buffer, size_t size);
443 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
444 void *buffer, size_t size);
447 * drm_dp_dpcd_readb() - read a single byte from the DPCD
448 * @aux: DisplayPort AUX channel
449 * @offset: address of the register to read
450 * @valuep: location where the value of the register will be stored
452 * Returns the number of bytes transferred (1) on success, or a negative
453 * error code on failure.
455 static inline ssize_t drm_dp_dpcd_readb(struct drm_dp_aux *aux,
456 unsigned int offset, u8 *valuep)
458 return drm_dp_dpcd_read(aux, offset, valuep, 1);
462 * drm_dp_dpcd_writeb() - write a single byte to the DPCD
463 * @aux: DisplayPort AUX channel
464 * @offset: address of the register to write
465 * @value: value to write to the register
467 * Returns the number of bytes transferred (1) on success, or a negative
468 * error code on failure.
470 static inline ssize_t drm_dp_dpcd_writeb(struct drm_dp_aux *aux,
471 unsigned int offset, u8 value)
473 return drm_dp_dpcd_write(aux, offset, &value, 1);
476 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
477 u8 dpcd[DP_RECEIVER_CAP_SIZE]);
479 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
480 u8 status[DP_LINK_STATUS_SIZE]);
482 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
483 enum drm_dp_phy dp_phy,
484 u8 link_status[DP_LINK_STATUS_SIZE]);
486 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
487 u8 real_edid_checksum);
489 int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
490 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
491 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]);
492 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
493 const u8 port_cap[4], u8 type);
494 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
495 const u8 port_cap[4],
496 const struct edid *edid);
497 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
498 const u8 port_cap[4]);
499 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
500 const u8 port_cap[4],
501 const struct edid *edid);
502 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
503 const u8 port_cap[4],
504 const struct edid *edid);
505 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
506 const u8 port_cap[4],
507 const struct edid *edid);
508 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
509 const u8 port_cap[4]);
510 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
511 const u8 port_cap[4]);
512 struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
513 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
514 const u8 port_cap[4]);
515 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
516 void drm_dp_downstream_debug(struct seq_file *m,
517 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
518 const u8 port_cap[4],
519 const struct edid *edid,
520 struct drm_dp_aux *aux);
521 enum drm_mode_subconnector
522 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
523 const u8 port_cap[4]);
524 void drm_dp_set_subconnector_property(struct drm_connector *connector,
525 enum drm_connector_status status,
527 const u8 port_cap[4]);
530 bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
531 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
532 const struct drm_dp_desc *desc);
533 int drm_dp_read_sink_count(struct drm_dp_aux *aux);
535 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
536 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
537 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
538 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
539 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
540 enum drm_dp_phy dp_phy,
541 u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
542 int drm_dp_lttpr_count(const u8 cap[DP_LTTPR_COMMON_CAP_SIZE]);
543 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
544 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]);
545 bool drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
546 bool drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]);
548 void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
549 void drm_dp_aux_init(struct drm_dp_aux *aux);
550 int drm_dp_aux_register(struct drm_dp_aux *aux);
551 void drm_dp_aux_unregister(struct drm_dp_aux *aux);
553 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc);
554 int drm_dp_stop_crc(struct drm_dp_aux *aux);
556 struct drm_dp_dpcd_ident {
565 * struct drm_dp_desc - DP branch/sink device descriptor
566 * @ident: DP device identification from DPCD 0x400 (sink) or 0x500 (branch).
567 * @quirks: Quirks; use drm_dp_has_quirk() to query for the quirks.
570 struct drm_dp_dpcd_ident ident;
574 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
578 * enum drm_dp_quirk - Display Port sink/branch device specific quirks
580 * Display Port sink and branch devices in the wild have a variety of bugs, try
581 * to collect them here. The quirks are shared, but it's up to the drivers to
582 * implement workarounds for them.
586 * @DP_DPCD_QUIRK_CONSTANT_N:
588 * The device requires main link attributes Mvid and Nvid to be limited
589 * to 16 bits. So will give a constant value (0x8000) for compatability.
591 DP_DPCD_QUIRK_CONSTANT_N,
593 * @DP_DPCD_QUIRK_NO_PSR:
595 * The device does not support PSR even if reports that it supports or
596 * driver still need to implement proper handling for such device.
598 DP_DPCD_QUIRK_NO_PSR,
600 * @DP_DPCD_QUIRK_NO_SINK_COUNT:
602 * The device does not set SINK_COUNT to a non-zero value.
603 * The driver should ignore SINK_COUNT during detection. Note that
604 * drm_dp_read_sink_count_cap() automatically checks for this quirk.
606 DP_DPCD_QUIRK_NO_SINK_COUNT,
608 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD:
610 * The device supports MST DSC despite not supporting Virtual DPCD.
611 * The DSC caps can be read from the physical aux instead.
613 DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
615 * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS:
617 * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite
618 * the DP_MAX_LINK_RATE register reporting a lower max multiplier.
620 DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS,
624 * drm_dp_has_quirk() - does the DP device have a specific quirk
625 * @desc: Device descriptor filled by drm_dp_read_desc()
626 * @quirk: Quirk to query for
628 * Return true if DP device identified by @desc has @quirk.
631 drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
633 return desc->quirks & BIT(quirk);
637 * struct drm_edp_backlight_info - Probed eDP backlight info struct
638 * @pwmgen_bit_count: The pwmgen bit count
639 * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any
640 * @max: The maximum backlight level that may be set
641 * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register?
642 * @aux_enable: Does the panel support the AUX enable cap?
643 * @aux_set: Does the panel support setting the brightness through AUX?
645 * This structure contains various data about an eDP backlight, which can be populated by using
646 * drm_edp_backlight_init().
648 struct drm_edp_backlight_info {
650 u8 pwm_freq_pre_divider;
653 bool lsb_reg_used : 1;
659 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
660 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
661 u16 *current_level, u8 *current_mode);
662 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
664 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
666 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl);
668 #if IS_ENABLED(CONFIG_DRM_KMS_HELPER) && (IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \
669 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE)))
671 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux);
675 static inline int drm_panel_dp_aux_backlight(struct drm_panel *panel,
676 struct drm_dp_aux *aux)
683 #ifdef CONFIG_DRM_DP_CEC
684 void drm_dp_cec_irq(struct drm_dp_aux *aux);
685 void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
686 struct drm_connector *connector);
687 void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
688 void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
689 void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
691 static inline void drm_dp_cec_irq(struct drm_dp_aux *aux)
696 drm_dp_cec_register_connector(struct drm_dp_aux *aux,
697 struct drm_connector *connector)
701 static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux)
705 static inline void drm_dp_cec_set_edid(struct drm_dp_aux *aux,
706 const struct edid *edid)
710 static inline void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
717 * struct drm_dp_phy_test_params - DP Phy Compliance parameters
718 * @link_rate: Requested Link rate from DPCD 0x219
719 * @num_lanes: Number of lanes requested by sing through DPCD 0x220
720 * @phy_pattern: DP Phy test pattern from DPCD 0x248
721 * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
722 * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259
723 * @enhanced_frame_cap: flag for enhanced frame capability.
725 struct drm_dp_phy_test_params {
731 bool enhanced_frame_cap;
734 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
735 struct drm_dp_phy_test_params *data);
736 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
737 struct drm_dp_phy_test_params *data, u8 dp_rev);
738 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
739 const u8 port_cap[4]);
740 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd);
741 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux);
742 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
744 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
746 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux);
747 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux);
749 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux);
750 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask);
751 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
752 struct drm_connector *connector);
753 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
754 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
755 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
756 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]);
757 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux);
758 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]);
759 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]);
760 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
761 const u8 port_cap[4], u8 color_spc);
762 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc);
764 #endif /* _DRM_DP_HELPER_H_ */