2 * carl9170 firmware - used by the ar9170 wireless device
4 * This module contains DMA descriptor related definitions.
6 * Copyright (c) 2000-2005 ZyDAS Technology Corporation
7 * Copyright (c) 2007-2009 Atheros Communications, Inc.
8 * Copyright 2009 Johannes Berg <johannes@sipsolutions.net>
9 * Copyright 2009-2011 Christian Lamparter <chunkeey@googlemail.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
26 #ifndef __CARL9170FW_DMA_H
27 #define __CARL9170FW_DMA_H
33 #include "ieee80211.h"
37 volatile uint16_t status; /* Descriptor status */
38 volatile uint16_t ctrl; /* Descriptor control */
39 volatile uint16_t dataSize; /* Data size */
40 volatile uint16_t totalLen; /* Total length */
41 struct dma_desc *lastAddr; /* Last address of this chain */
43 uint8_t *_dataAddr; /* Data buffer address */
46 struct dma_desc *nextAddr; /* Next TD address */
47 } __packed __aligned(4);
49 /* Up, Dn, 5x Tx, retry, Rx, [USB Int], (CAB), (BA) */
50 #define AR9170_TERMINATOR_NUMBER_B 9
52 #define AR9170_TERMINATOR_NUMBER_INT 1
54 #ifdef CONFIG_CARL9170FW_CAB_QUEUE
55 #define AR9170_TERMINATOR_NUMBER_CAB CARL9170_INTF_NUM
57 #define AR9170_TERMINATOR_NUMBER_CAB 0
58 #endif /* CONFIG_CARL9170FW_CAB_QUEUE */
60 #ifdef CONFIG_CARL9170FW_HANDLE_BACK_REQ
61 #define AR9170_TERMINATOR_NUMBER_BA 1
63 #define AR9170_TERMINATOR_NUMBER_BA 0
64 #endif /* CONFIG_CARL9170FW_HANDLE_BACK_REQ */
65 #define AR9170_TERMINATOR_NUMBER (AR9170_TERMINATOR_NUMBER_B + \
66 AR9170_TERMINATOR_NUMBER_INT + \
67 AR9170_TERMINATOR_NUMBER_CAB + \
68 AR9170_TERMINATOR_NUMBER_BA)
70 #define AR9170_BLOCK_SIZE (256 + 64)
72 #define AR9170_DESCRIPTOR_SIZE (sizeof(struct dma_desc))
74 struct ar9170_tx_ba_frame {
75 struct ar9170_tx_hwdesc hdr;
76 struct ieee80211_ba ba;
79 struct carl9170_tx_ba_superframe {
80 struct carl9170_tx_superdesc s;
81 struct ar9170_tx_ba_frame f;
84 #define CARL9170_BA_BUFFER_LEN (__roundup(sizeof(struct carl9170_tx_ba_superframe), 16))
85 #define CARL9170_RSP_BUFFER_LEN AR9170_BLOCK_SIZE
87 struct carl9170_sram_reserved {
88 #ifdef CONFIG_CARL9170FW_HANDLE_BACK_REQ
90 uint32_t buf[CARL9170_BA_BUFFER_LEN / sizeof(uint32_t)];
91 struct carl9170_tx_ba_superframe ba;
93 #endif /* CONFIG_CARL9170FW_HANDLE_BACK_REQ */
95 uint32_t buf[CARL9170_MAX_CMD_LEN / sizeof(uint32_t)];
96 struct carl9170_cmd cmd;
100 uint32_t buf[CARL9170_RSP_BUFFER_LEN / sizeof(uint32_t)];
101 struct carl9170_rsp rsp;
105 uint32_t buf[CARL9170_INTF_NUM][AR9170_MAC_BCN_LENGTH_MAX / sizeof(uint32_t)];
110 * Memory layout in RAM:
113 * | terminator descriptors (dma_desc)
114 * | - Up (to USB host)
115 * | - Down (from USB host)
116 * | - TX (5x, to wifi)
120 * | - FW cmd & req descriptor
121 * | - BlockAck descriptor
122 * | total: AR9170_TERMINATOR_NUMBER
124 * | block descriptors (dma_desc)
125 * | (AR9170_BLOCK_NUMBER)
126 * AR9170_BLOCK_BUFFER_BASE +-- align to multiple of 64
127 * | block buffers (AR9170_BLOCK_SIZE each)
128 * | (AR9170_BLOCK_NUMBER)
129 * approx. 0x117c00 +--
130 * | BA buffer (128 bytes)
132 * | CMD buffer (128 bytes)
134 * | RSP buffer (320 bytes)
136 * | BEACON buffer (256 bytes)
138 * | unaccounted space / padding
143 #define CARL9170_SRAM_RESERVED (sizeof(struct carl9170_sram_reserved))
145 #define AR9170_FRAME_MEMORY_SIZE (AR9170_SRAM_SIZE - CARL9170_SRAM_RESERVED)
147 #define BLOCK_ALIGNMENT 64
149 #define NONBLOCK_DESCRIPTORS_SIZE \
150 (AR9170_DESCRIPTOR_SIZE * (AR9170_TERMINATOR_NUMBER))
152 #define NONBLOCK_DESCRIPTORS_SIZE_ALIGNED \
153 (ALIGN(NONBLOCK_DESCRIPTORS_SIZE, BLOCK_ALIGNMENT))
155 #define AR9170_BLOCK_NUMBER ((AR9170_FRAME_MEMORY_SIZE - NONBLOCK_DESCRIPTORS_SIZE_ALIGNED) / \
156 (AR9170_BLOCK_SIZE + AR9170_DESCRIPTOR_SIZE))
158 struct ar9170_data_block {
159 uint8_t data[AR9170_BLOCK_SIZE];
162 struct ar9170_dma_memory {
163 struct dma_desc terminator[AR9170_TERMINATOR_NUMBER];
164 struct dma_desc block[AR9170_BLOCK_NUMBER];
165 struct ar9170_data_block data[AR9170_BLOCK_NUMBER] __aligned(BLOCK_ALIGNMENT);
166 struct carl9170_sram_reserved reserved __aligned(BLOCK_ALIGNMENT);
169 extern struct ar9170_dma_memory dma_mem;
171 #define AR9170_DOWN_BLOCK_RATIO 2
172 #define AR9170_RX_BLOCK_RATIO 1
173 /* Tx 16*2 = 32 packets => 32*(5*320) */
174 #define AR9170_TX_BLOCK_NUMBER (AR9170_BLOCK_NUMBER * AR9170_DOWN_BLOCK_RATIO / \
175 (AR9170_RX_BLOCK_RATIO + AR9170_DOWN_BLOCK_RATIO))
176 #define AR9170_RX_BLOCK_NUMBER (AR9170_BLOCK_NUMBER - AR9170_TX_BLOCK_NUMBER)
179 #define AR9170_ERR_FS_BIT 1
180 #define AR9170_ERR_LS_BIT 2
181 #define AR9170_ERR_OWN_BITS 3
182 #define AR9170_ERR_DATA_SIZE 4
183 #define AR9170_ERR_TOTAL_LEN 5
184 #define AR9170_ERR_DATA 6
185 #define AR9170_ERR_SEQ 7
186 #define AR9170_ERR_LEN 8
188 /* Status bits definitions */
189 /* Own bits definitions */
190 #define AR9170_OWN_BITS 0x3
191 #define AR9170_OWN_BITS_S 0
192 #define AR9170_OWN_BITS_SW 0x0
193 #define AR9170_OWN_BITS_HW 0x1
194 #define AR9170_OWN_BITS_SE 0x2
196 /* Control bits definitions */
197 #define AR9170_CTRL_TXFAIL 1
198 #define AR9170_CTRL_BAFAIL 2
199 #define AR9170_CTRL_FAIL (AR9170_CTRL_TXFAIL | AR9170_CTRL_BAFAIL)
201 /* First segament bit */
202 #define AR9170_CTRL_LS_BIT 0x100
203 /* Last segament bit */
204 #define AR9170_CTRL_FS_BIT 0x200
207 struct dma_desc *head;
208 struct dma_desc *terminator;
211 #define DESC_PAYLOAD(a) ((void *)a->dataAddr)
212 #define DESC_PAYLOAD_OFF(a, offset) ((void *)((unsigned long)(a->_dataAddr) + offset))
214 struct dma_desc *dma_unlink_head(struct dma_queue *queue);
215 void dma_init_descriptors(void);
216 void dma_reclaim(struct dma_queue *q, struct dma_desc *desc);
217 void dma_put(struct dma_queue *q, struct dma_desc *desc);
218 void dma_queue_reclaim(struct dma_queue *dst, struct dma_queue *src);
220 static inline __inline bool is_terminator(struct dma_queue *q, struct dma_desc *desc)
222 return q->terminator == desc;
225 static inline __inline bool queue_empty(struct dma_queue *q)
227 return q->head == q->terminator;
231 * Get a completed packet with # descriptors. Return the first
232 * descriptor and pointer the head directly by lastAddr->nextAddr
234 static inline __inline struct dma_desc *dma_dequeue_bits(struct dma_queue *q,
237 struct dma_desc *desc = NULL;
239 if ((q->head->status & AR9170_OWN_BITS) == bits)
240 desc = dma_unlink_head(q);
245 static inline __inline struct dma_desc *dma_dequeue_not_bits(struct dma_queue *q,
248 struct dma_desc *desc = NULL;
250 /* AR9170_OWN_BITS_HW will be filtered out here too. */
251 if ((q->head->status & AR9170_OWN_BITS) != bits)
252 desc = dma_unlink_head(q);
257 #define for_each_desc_bits(desc, queue, bits) \
258 while ((desc = dma_dequeue_bits(queue, bits)))
260 #define for_each_desc_not_bits(desc, queue, bits) \
261 while ((desc = dma_dequeue_not_bits(queue, bits)))
263 #define for_each_desc(desc, queue) \
264 while ((desc = dma_unlink_head(queue)))
266 #define __for_each_desc_bits(desc, queue, bits) \
267 for (desc = (queue)->head; \
268 (desc != (queue)->terminator && \
269 (desc->status & AR9170_OWN_BITS) == bits); \
270 desc = desc->lastAddr->nextAddr)
272 #define __while_desc_bits(desc, queue, bits) \
273 for (desc = (queue)->head; \
274 (!queue_empty(queue) && \
275 (desc->status & AR9170_OWN_BITS) == bits); \
276 desc = (queue)->head)
278 #define __for_each_desc(desc, queue) \
279 for (desc = (queue)->head; \
280 desc != (queue)->terminator; \
281 desc = (desc)->lastAddr->nextAddr)
283 #define __for_each_desc_safe(desc, tmp, queue) \
284 for (desc = (queue)->head, tmp = desc->lastAddr->nextAddr; \
285 desc != (queue)->terminator; \
286 desc = tmp, tmp = tmp->lastAddr->nextAddr)
288 #define __while_subdesc(desc, queue) \
289 for (desc = (queue)->head; \
290 desc != (queue)->terminator; \
291 desc = (desc)->nextAddr)
293 static inline __inline unsigned int queue_len(struct dma_queue *q)
295 struct dma_desc *desc;
298 __while_subdesc(desc, q)
305 * rearm a completed packet, so it will be processed agian.
307 static inline __inline void dma_rearm(struct dma_desc *desc)
309 /* Set OWN bit to HW */
310 desc->status = ((desc->status & (~AR9170_OWN_BITS)) |
314 static inline void __check_desc(void)
316 struct ar9170_dma_memory mem;
317 BUILD_BUG_ON(sizeof(struct ar9170_data_block) != AR9170_BLOCK_SIZE);
318 BUILD_BUG_ON(sizeof(struct dma_desc) != 20);
320 BUILD_BUG_ON(sizeof(mem) > AR9170_SRAM_SIZE);
322 #ifdef CONFIG_CARL9170FW_HANDLE_BACK_REQ
323 BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, ba.buf) & (BLOCK_ALIGNMENT - 1));
324 #endif /* CONFIG_CARL9170FW_HANDLE_BACK_REQ */
325 BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, cmd.buf) & (BLOCK_ALIGNMENT - 1));
326 BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, rsp.buf) & (BLOCK_ALIGNMENT - 1));
327 BUILD_BUG_ON(offsetof(struct carl9170_sram_reserved, bcn.buf) & (BLOCK_ALIGNMENT - 1));
330 #endif /* __CARL9170FW_DMA_H */