1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * FP/SIMD state saving and restoring macros
5 * Copyright (C) 2012 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
9 .macro fpsimd_save state, tmpnr
10 stp q0, q1, [\state, #16 * 0]
11 stp q2, q3, [\state, #16 * 2]
12 stp q4, q5, [\state, #16 * 4]
13 stp q6, q7, [\state, #16 * 6]
14 stp q8, q9, [\state, #16 * 8]
15 stp q10, q11, [\state, #16 * 10]
16 stp q12, q13, [\state, #16 * 12]
17 stp q14, q15, [\state, #16 * 14]
18 stp q16, q17, [\state, #16 * 16]
19 stp q18, q19, [\state, #16 * 18]
20 stp q20, q21, [\state, #16 * 20]
21 stp q22, q23, [\state, #16 * 22]
22 stp q24, q25, [\state, #16 * 24]
23 stp q26, q27, [\state, #16 * 26]
24 stp q28, q29, [\state, #16 * 28]
25 stp q30, q31, [\state, #16 * 30]!
27 str w\tmpnr, [\state, #16 * 2]
29 str w\tmpnr, [\state, #16 * 2 + 4]
32 .macro fpsimd_restore_fpcr state, tmp
34 * Writes to fpcr may be self-synchronising, so avoid restoring
35 * the register if it hasn't changed.
45 .macro fpsimd_restore state, tmpnr
46 ldp q0, q1, [\state, #16 * 0]
47 ldp q2, q3, [\state, #16 * 2]
48 ldp q4, q5, [\state, #16 * 4]
49 ldp q6, q7, [\state, #16 * 6]
50 ldp q8, q9, [\state, #16 * 8]
51 ldp q10, q11, [\state, #16 * 10]
52 ldp q12, q13, [\state, #16 * 12]
53 ldp q14, q15, [\state, #16 * 14]
54 ldp q16, q17, [\state, #16 * 16]
55 ldp q18, q19, [\state, #16 * 18]
56 ldp q20, q21, [\state, #16 * 20]
57 ldp q22, q23, [\state, #16 * 22]
58 ldp q24, q25, [\state, #16 * 24]
59 ldp q26, q27, [\state, #16 * 26]
60 ldp q28, q29, [\state, #16 * 28]
61 ldp q30, q31, [\state, #16 * 30]!
62 ldr w\tmpnr, [\state, #16 * 2]
64 ldr w\tmpnr, [\state, #16 * 2 + 4]
65 fpsimd_restore_fpcr x\tmpnr, \state
68 /* Sanity-check macros to help avoid encoding garbage instructions */
70 .macro _check_general_reg nr
71 .if (\nr) < 0 || (\nr) > 30
72 .error "Bad register number \nr."
76 .macro _sve_check_zreg znr
77 .if (\znr) < 0 || (\znr) > 31
78 .error "Bad Scalable Vector Extension vector register number \znr."
82 .macro _sve_check_preg pnr
83 .if (\pnr) < 0 || (\pnr) > 15
84 .error "Bad Scalable Vector Extension predicate register number \pnr."
88 .macro _check_num n, min, max
89 .if (\n) < (\min) || (\n) > (\max)
90 .error "Number \n out of range [\min,\max]"
94 /* SVE instruction encodings for non-SVE-capable assemblers */
96 /* STR (vector): STR Z\nz, [X\nxbase, #\offset, MUL VL] */
97 .macro _sve_str_v nz, nxbase, offset=0
99 _check_general_reg \nxbase
100 _check_num (\offset), -0x100, 0xff
104 | (((\offset) & 7) << 10) \
105 | (((\offset) & 0x1f8) << 13)
108 /* LDR (vector): LDR Z\nz, [X\nxbase, #\offset, MUL VL] */
109 .macro _sve_ldr_v nz, nxbase, offset=0
111 _check_general_reg \nxbase
112 _check_num (\offset), -0x100, 0xff
116 | (((\offset) & 7) << 10) \
117 | (((\offset) & 0x1f8) << 13)
120 /* STR (predicate): STR P\np, [X\nxbase, #\offset, MUL VL] */
121 .macro _sve_str_p np, nxbase, offset=0
123 _check_general_reg \nxbase
124 _check_num (\offset), -0x100, 0xff
128 | (((\offset) & 7) << 10) \
129 | (((\offset) & 0x1f8) << 13)
132 /* LDR (predicate): LDR P\np, [X\nxbase, #\offset, MUL VL] */
133 .macro _sve_ldr_p np, nxbase, offset=0
135 _check_general_reg \nxbase
136 _check_num (\offset), -0x100, 0xff
140 | (((\offset) & 7) << 10) \
141 | (((\offset) & 0x1f8) << 13)
144 /* RDVL X\nx, #\imm */
145 .macro _sve_rdvl nx, imm
146 _check_general_reg \nx
147 _check_num (\imm), -0x20, 0x1f
150 | (((\imm) & 0x3f) << 5)
153 /* RDFFR (unpredicated): RDFFR P\np.B */
167 .macro __for from:req, to:req
171 __for \from, (\from) + ((\to) - (\from)) / 2
172 __for (\from) + ((\to) - (\from)) / 2 + 1, \to
176 .macro _for var:req, from:req, to:req, insn:vararg
177 .macro _for__body \var:req
186 .macro sve_save nxbase, xpfpsr, nxtmp
187 _for n, 0, 31, _sve_str_v \n, \nxbase, \n - 34
188 _for n, 0, 15, _sve_str_p \n, \nxbase, \n - 16
190 _sve_str_p 0, \nxbase
191 _sve_ldr_p 0, \nxbase, -16
194 str w\nxtmp, [\xpfpsr]
196 str w\nxtmp, [\xpfpsr, #4]
199 .macro sve_load nxbase, xpfpsr, xvqminus1, nxtmp, xtmp2
200 mrs_s x\nxtmp, SYS_ZCR_EL1
201 bic \xtmp2, x\nxtmp, ZCR_ELx_LEN_MASK
202 orr \xtmp2, \xtmp2, \xvqminus1
205 msr_s SYS_ZCR_EL1, \xtmp2 // self-synchronising
207 _for n, 0, 31, _sve_ldr_v \n, \nxbase, \n - 34
208 _sve_ldr_p 0, \nxbase
210 _for n, 0, 15, _sve_ldr_p \n, \nxbase, \n - 16
212 ldr w\nxtmp, [\xpfpsr]
214 ldr w\nxtmp, [\xpfpsr, #4]