1 #ifndef _ASM_X86_BITOPS_H
2 #define _ASM_X86_BITOPS_H
5 * Copyright 1992, Linus Torvalds.
7 * Note: inlines with more than a single statement should be marked
8 * __always_inline to avoid problems with older gcc's inlining heuristics.
11 #ifndef _LINUX_BITOPS_H
12 #error only <linux/bitops.h> can be included directly
15 #include <linux/compiler.h>
16 #include <asm/alternative.h>
17 #include <asm/rmwcc.h>
18 #include <asm/barrier.h>
20 #if BITS_PER_LONG == 32
21 # define _BITOPS_LONG_SHIFT 5
22 #elif BITS_PER_LONG == 64
23 # define _BITOPS_LONG_SHIFT 6
25 # error "Unexpected BITS_PER_LONG"
28 #define BIT_64(n) (U64_C(1) << (n))
31 * These have to be done with inline assembly: that way the bit-setting
32 * is guaranteed to be atomic. All bit operations return 0 if the bit
33 * was cleared before the operation and != 0 if it was not.
35 * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
38 #if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 1)
39 /* Technically wrong, but this avoids compilation errors on some gcc
41 #define BITOP_ADDR(x) "=m" (*(volatile long *) (x))
43 #define BITOP_ADDR(x) "+m" (*(volatile long *) (x))
46 #define ADDR BITOP_ADDR(addr)
49 * We do the locked ops that don't return the old value as
50 * a mask operation on a byte.
52 #define IS_IMMEDIATE(nr) (__builtin_constant_p(nr))
53 #define CONST_MASK_ADDR(nr, addr) BITOP_ADDR((void *)(addr) + ((nr)>>3))
54 #define CONST_MASK(nr) (1 << ((nr) & 7))
57 * set_bit - Atomically set a bit in memory
59 * @addr: the address to start counting from
61 * This function is atomic and may not be reordered. See __set_bit()
62 * if you do not require the atomic guarantees.
64 * Note: there are no guarantees that this function will not be reordered
65 * on non x86 architectures, so if you are writing portable code,
66 * make sure not to rely on its reordering guarantees.
68 * Note that @nr may be almost arbitrarily large; this function is not
69 * restricted to acting on a single-word quantity.
71 static __always_inline void
72 set_bit(long nr, volatile unsigned long *addr)
74 if (IS_IMMEDIATE(nr)) {
75 asm volatile(LOCK_PREFIX "orb %1,%0"
76 : CONST_MASK_ADDR(nr, addr)
77 : "iq" ((u8)CONST_MASK(nr))
80 asm volatile(LOCK_PREFIX __ASM_SIZE(bts) " %1,%0"
81 : BITOP_ADDR(addr) : "Ir" (nr) : "memory");
86 * __set_bit - Set a bit in memory
88 * @addr: the address to start counting from
90 * Unlike set_bit(), this function is non-atomic and may be reordered.
91 * If it's called on the same region of memory simultaneously, the effect
92 * may be that only one operation succeeds.
94 static __always_inline void __set_bit(long nr, volatile unsigned long *addr)
96 asm volatile(__ASM_SIZE(bts) " %1,%0" : ADDR : "Ir" (nr) : "memory");
100 * clear_bit - Clears a bit in memory
102 * @addr: Address to start counting from
104 * clear_bit() is atomic and may not be reordered. However, it does
105 * not contain a memory barrier, so if it is used for locking purposes,
106 * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic()
107 * in order to ensure changes are visible on other processors.
109 static __always_inline void
110 clear_bit(long nr, volatile unsigned long *addr)
112 if (IS_IMMEDIATE(nr)) {
113 asm volatile(LOCK_PREFIX "andb %1,%0"
114 : CONST_MASK_ADDR(nr, addr)
115 : "iq" ((u8)~CONST_MASK(nr)));
117 asm volatile(LOCK_PREFIX __ASM_SIZE(btr) " %1,%0"
124 * clear_bit_unlock - Clears a bit in memory
126 * @addr: Address to start counting from
128 * clear_bit() is atomic and implies release semantics before the memory
129 * operation. It can be used for an unlock.
131 static __always_inline void clear_bit_unlock(long nr, volatile unsigned long *addr)
137 static __always_inline void __clear_bit(long nr, volatile unsigned long *addr)
139 asm volatile(__ASM_SIZE(btr) " %1,%0" : ADDR : "Ir" (nr));
143 * __clear_bit_unlock - Clears a bit in memory
145 * @addr: Address to start counting from
147 * __clear_bit() is non-atomic and implies release semantics before the memory
148 * operation. It can be used for an unlock if no other CPUs can concurrently
149 * modify other bits in the word.
151 * No memory barrier is required here, because x86 cannot reorder stores past
152 * older loads. Same principle as spin_unlock.
154 static __always_inline void __clear_bit_unlock(long nr, volatile unsigned long *addr)
157 __clear_bit(nr, addr);
161 * __change_bit - Toggle a bit in memory
162 * @nr: the bit to change
163 * @addr: the address to start counting from
165 * Unlike change_bit(), this function is non-atomic and may be reordered.
166 * If it's called on the same region of memory simultaneously, the effect
167 * may be that only one operation succeeds.
169 static __always_inline void __change_bit(long nr, volatile unsigned long *addr)
171 asm volatile(__ASM_SIZE(btc) " %1,%0" : ADDR : "Ir" (nr));
175 * change_bit - Toggle a bit in memory
177 * @addr: Address to start counting from
179 * change_bit() is atomic and may not be reordered.
180 * Note that @nr may be almost arbitrarily large; this function is not
181 * restricted to acting on a single-word quantity.
183 static __always_inline void change_bit(long nr, volatile unsigned long *addr)
185 if (IS_IMMEDIATE(nr)) {
186 asm volatile(LOCK_PREFIX "xorb %1,%0"
187 : CONST_MASK_ADDR(nr, addr)
188 : "iq" ((u8)CONST_MASK(nr)));
190 asm volatile(LOCK_PREFIX __ASM_SIZE(btc) " %1,%0"
197 * test_and_set_bit - Set a bit and return its old value
199 * @addr: Address to count from
201 * This operation is atomic and cannot be reordered.
202 * It also implies a memory barrier.
204 static __always_inline bool test_and_set_bit(long nr, volatile unsigned long *addr)
206 GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(bts),
207 *addr, "Ir", nr, "%0", c);
211 * test_and_set_bit_lock - Set a bit and return its old value for lock
213 * @addr: Address to count from
215 * This is the same as test_and_set_bit on x86.
217 static __always_inline bool
218 test_and_set_bit_lock(long nr, volatile unsigned long *addr)
220 return test_and_set_bit(nr, addr);
224 * __test_and_set_bit - Set a bit and return its old value
226 * @addr: Address to count from
228 * This operation is non-atomic and can be reordered.
229 * If two examples of this operation race, one can appear to succeed
230 * but actually fail. You must protect multiple accesses with a lock.
232 static __always_inline bool __test_and_set_bit(long nr, volatile unsigned long *addr)
236 asm(__ASM_SIZE(bts) " %2,%1"
238 : CC_OUT(c) (oldbit), ADDR
244 * test_and_clear_bit - Clear a bit and return its old value
246 * @addr: Address to count from
248 * This operation is atomic and cannot be reordered.
249 * It also implies a memory barrier.
251 static __always_inline bool test_and_clear_bit(long nr, volatile unsigned long *addr)
253 GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btr),
254 *addr, "Ir", nr, "%0", c);
258 * __test_and_clear_bit - Clear a bit and return its old value
260 * @addr: Address to count from
262 * This operation is non-atomic and can be reordered.
263 * If two examples of this operation race, one can appear to succeed
264 * but actually fail. You must protect multiple accesses with a lock.
266 * Note: the operation is performed atomically with respect to
267 * the local CPU, but not other CPUs. Portable code should not
268 * rely on this behaviour.
269 * KVM relies on this behaviour on x86 for modifying memory that is also
270 * accessed from a hypervisor on the same CPU if running in a VM: don't change
271 * this without also updating arch/x86/kernel/kvm.c
273 static __always_inline bool __test_and_clear_bit(long nr, volatile unsigned long *addr)
277 asm volatile(__ASM_SIZE(btr) " %2,%1"
279 : CC_OUT(c) (oldbit), ADDR
284 /* WARNING: non atomic and it can be reordered! */
285 static __always_inline bool __test_and_change_bit(long nr, volatile unsigned long *addr)
289 asm volatile(__ASM_SIZE(btc) " %2,%1"
291 : CC_OUT(c) (oldbit), ADDR
292 : "Ir" (nr) : "memory");
298 * test_and_change_bit - Change a bit and return its old value
300 * @addr: Address to count from
302 * This operation is atomic and cannot be reordered.
303 * It also implies a memory barrier.
305 static __always_inline bool test_and_change_bit(long nr, volatile unsigned long *addr)
307 GEN_BINARY_RMWcc(LOCK_PREFIX __ASM_SIZE(btc),
308 *addr, "Ir", nr, "%0", c);
311 static __always_inline bool constant_test_bit(long nr, const volatile unsigned long *addr)
313 return ((1UL << (nr & (BITS_PER_LONG-1))) &
314 (addr[nr >> _BITOPS_LONG_SHIFT])) != 0;
317 static __always_inline bool variable_test_bit(long nr, volatile const unsigned long *addr)
321 asm volatile(__ASM_SIZE(bt) " %2,%1"
324 : "m" (*(unsigned long *)addr), "Ir" (nr));
329 #if 0 /* Fool kernel-doc since it doesn't do macros yet */
331 * test_bit - Determine whether a bit is set
332 * @nr: bit number to test
333 * @addr: Address to start counting from
335 static bool test_bit(int nr, const volatile unsigned long *addr);
338 #define test_bit(nr, addr) \
339 (__builtin_constant_p((nr)) \
340 ? constant_test_bit((nr), (addr)) \
341 : variable_test_bit((nr), (addr)))
344 * __ffs - find first set bit in word
345 * @word: The word to search
347 * Undefined if no bit exists, so code should check against 0 first.
349 static __always_inline unsigned long __ffs(unsigned long word)
358 * ffz - find first zero bit in word
359 * @word: The word to search
361 * Undefined if no zero exists, so code should check against ~0UL first.
363 static __always_inline unsigned long ffz(unsigned long word)
372 * __fls: find last set bit in word
373 * @word: The word to search
375 * Undefined if no set bit exists, so code should check against 0 first.
377 static __always_inline unsigned long __fls(unsigned long word)
389 * ffs - find first set bit in word
390 * @x: the word to search
392 * This is defined the same way as the libc and compiler builtin ffs
393 * routines, therefore differs in spirit from the other bitops.
395 * ffs(value) returns 0 if value is 0 or the position of the first
396 * set bit if value is nonzero. The first (least significant) bit
399 static __always_inline int ffs(int x)
405 * AMD64 says BSFL won't clobber the dest reg if x==0; Intel64 says the
406 * dest reg is undefined if x==0, but their CPU architect says its
407 * value is written to set it to the same as before, except that the
408 * top 32 bits will be cleared.
410 * We cannot do this on 32 bits because at the very least some
411 * 486 CPUs did not behave this way.
415 : "rm" (x), "0" (-1));
416 #elif defined(CONFIG_X86_CMOV)
419 : "=&r" (r) : "rm" (x), "r" (-1));
424 "1:" : "=r" (r) : "rm" (x));
430 * fls - find last set bit in word
431 * @x: the word to search
433 * This is defined in a similar way as the libc and compiler builtin
434 * ffs, but returns the position of the most significant set bit.
436 * fls(value) returns 0 if value is 0 or the position of the last
437 * set bit if value is nonzero. The last (most significant) bit is
440 static __always_inline int fls(int x)
446 * AMD64 says BSRL won't clobber the dest reg if x==0; Intel64 says the
447 * dest reg is undefined if x==0, but their CPU architect says its
448 * value is written to set it to the same as before, except that the
449 * top 32 bits will be cleared.
451 * We cannot do this on 32 bits because at the very least some
452 * 486 CPUs did not behave this way.
456 : "rm" (x), "0" (-1));
457 #elif defined(CONFIG_X86_CMOV)
460 : "=&r" (r) : "rm" (x), "rm" (-1));
465 "1:" : "=r" (r) : "rm" (x));
471 * fls64 - find last set bit in a 64-bit word
472 * @x: the word to search
474 * This is defined in a similar way as the libc and compiler builtin
475 * ffsll, but returns the position of the most significant set bit.
477 * fls64(value) returns 0 if value is 0 or the position of the last
478 * set bit if value is nonzero. The last (most significant) bit is
482 static __always_inline int fls64(__u64 x)
486 * AMD64 says BSRQ won't clobber the dest reg if x==0; Intel64 says the
487 * dest reg is undefined if x==0, but their CPU architect says its
488 * value is written to set it to the same as before.
496 #include <asm-generic/bitops/fls64.h>
499 #include <asm-generic/bitops/find.h>
501 #include <asm-generic/bitops/sched.h>
503 #include <asm/arch_hweight.h>
505 #include <asm-generic/bitops/const_hweight.h>
507 #include <asm-generic/bitops/le.h>
509 #include <asm-generic/bitops/ext2-atomic-setbit.h>
511 #endif /* __KERNEL__ */
512 #endif /* _ASM_X86_BITOPS_H */