1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de>
7 #include <linux/firmware/imx/ipc.h>
8 #include <linux/interrupt.h>
10 #include <linux/iopoll.h>
11 #include <linux/kernel.h>
12 #include <linux/mailbox_controller.h>
13 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/suspend.h>
17 #include <linux/slab.h>
19 #define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
20 #define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x)))
21 #define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x)))
22 #define IMX_MU_xSR_BRDIP BIT(9)
24 /* General Purpose Interrupt Enable */
25 #define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
26 /* Receive Interrupt Enable */
27 #define IMX_MU_xCR_RIEn(x) BIT(24 + (3 - (x)))
28 /* Transmit Interrupt Enable */
29 #define IMX_MU_xCR_TIEn(x) BIT(20 + (3 - (x)))
30 /* General Purpose Interrupt Request */
31 #define IMX_MU_xCR_GIRn(x) BIT(16 + (3 - (x)))
33 #define IMX_MU_CHANS 16
34 /* TX0/RX0/RXDB[0-3] */
35 #define IMX_MU_SCU_CHANS 6
36 #define IMX_MU_CHAN_NAME_SIZE 20
38 enum imx_mu_chan_type {
39 IMX_MU_TYPE_TX, /* Tx */
40 IMX_MU_TYPE_RX, /* Rx */
41 IMX_MU_TYPE_TXDB, /* Tx doorbell */
42 IMX_MU_TYPE_RXDB, /* Rx doorbell */
45 struct imx_sc_rpc_msg_max {
46 struct imx_sc_rpc_msg hdr;
50 struct imx_mu_con_priv {
52 char irq_desc[IMX_MU_CHAN_NAME_SIZE];
53 enum imx_mu_chan_type type;
54 struct mbox_chan *chan;
55 struct tasklet_struct txdb_tasklet;
61 spinlock_t xcr_lock; /* control register lock */
63 struct mbox_controller mbox;
64 struct mbox_chan mbox_chans[IMX_MU_CHANS];
66 struct imx_mu_con_priv con_priv[IMX_MU_CHANS];
67 const struct imx_mu_dcfg *dcfg;
78 int (*tx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data);
79 int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp);
80 void (*init)(struct imx_mu_priv *priv);
81 u32 xTR[4]; /* Transmit Registers */
82 u32 xRR[4]; /* Receive Registers */
83 u32 xSR; /* Status Register */
84 u32 xCR; /* Control Register */
87 static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
89 return container_of(mbox, struct imx_mu_priv, mbox);
92 static void imx_mu_write(struct imx_mu_priv *priv, u32 val, u32 offs)
94 iowrite32(val, priv->base + offs);
97 static u32 imx_mu_read(struct imx_mu_priv *priv, u32 offs)
99 return ioread32(priv->base + offs);
102 static u32 imx_mu_xcr_rmw(struct imx_mu_priv *priv, u32 set, u32 clr)
107 spin_lock_irqsave(&priv->xcr_lock, flags);
108 val = imx_mu_read(priv, priv->dcfg->xCR);
111 imx_mu_write(priv, val, priv->dcfg->xCR);
112 spin_unlock_irqrestore(&priv->xcr_lock, flags);
117 static int imx_mu_generic_tx(struct imx_mu_priv *priv,
118 struct imx_mu_con_priv *cp,
125 imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]);
126 imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
128 case IMX_MU_TYPE_TXDB:
129 imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0);
130 tasklet_schedule(&cp->txdb_tasklet);
133 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
140 static int imx_mu_generic_rx(struct imx_mu_priv *priv,
141 struct imx_mu_con_priv *cp)
145 dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]);
146 mbox_chan_received_data(cp->chan, (void *)&dat);
151 static int imx_mu_scu_tx(struct imx_mu_priv *priv,
152 struct imx_mu_con_priv *cp,
155 struct imx_sc_rpc_msg_max *msg = data;
163 * msg->hdr.size specifies the number of u32 words while
164 * sizeof yields bytes.
167 if (msg->hdr.size > sizeof(*msg) / 4) {
169 * The real message size can be different to
170 * struct imx_sc_rpc_msg_max size
172 dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on TX; got: %i bytes\n", sizeof(*msg), msg->hdr.size << 2);
176 for (i = 0; i < 4 && i < msg->hdr.size; i++)
177 imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
178 for (; i < msg->hdr.size; i++) {
179 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR,
181 xsr & IMX_MU_xSR_TEn(i % 4),
184 dev_err(priv->dev, "Send data index: %d timeout\n", i);
187 imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]);
190 imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0);
193 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type);
200 static int imx_mu_scu_rx(struct imx_mu_priv *priv,
201 struct imx_mu_con_priv *cp)
203 struct imx_sc_rpc_msg_max msg;
204 u32 *data = (u32 *)&msg;
208 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(0));
209 *data++ = imx_mu_read(priv, priv->dcfg->xRR[0]);
211 if (msg.hdr.size > sizeof(msg) / 4) {
212 dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on RX; got: %i bytes\n", sizeof(msg), msg.hdr.size << 2);
216 for (i = 1; i < msg.hdr.size; i++) {
217 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR, xsr,
218 xsr & IMX_MU_xSR_RFn(i % 4), 0, 100);
220 dev_err(priv->dev, "timeout read idx %d\n", i);
223 *data++ = imx_mu_read(priv, priv->dcfg->xRR[i % 4]);
226 imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(0), 0);
227 mbox_chan_received_data(cp->chan, (void *)&msg);
232 static void imx_mu_txdb_tasklet(unsigned long data)
234 struct imx_mu_con_priv *cp = (struct imx_mu_con_priv *)data;
236 mbox_chan_txdone(cp->chan, 0);
239 static irqreturn_t imx_mu_isr(int irq, void *p)
241 struct mbox_chan *chan = p;
242 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
243 struct imx_mu_con_priv *cp = chan->con_priv;
246 ctrl = imx_mu_read(priv, priv->dcfg->xCR);
247 val = imx_mu_read(priv, priv->dcfg->xSR);
251 val &= IMX_MU_xSR_TEn(cp->idx) &
252 (ctrl & IMX_MU_xCR_TIEn(cp->idx));
255 val &= IMX_MU_xSR_RFn(cp->idx) &
256 (ctrl & IMX_MU_xCR_RIEn(cp->idx));
258 case IMX_MU_TYPE_RXDB:
259 val &= IMX_MU_xSR_GIPn(cp->idx) &
260 (ctrl & IMX_MU_xCR_GIEn(cp->idx));
269 if (val == IMX_MU_xSR_TEn(cp->idx)) {
270 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
271 mbox_chan_txdone(chan, 0);
272 } else if (val == IMX_MU_xSR_RFn(cp->idx)) {
273 priv->dcfg->rx(priv, cp);
274 } else if (val == IMX_MU_xSR_GIPn(cp->idx)) {
275 imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR);
276 mbox_chan_received_data(chan, NULL);
278 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n");
288 static int imx_mu_send_data(struct mbox_chan *chan, void *data)
290 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
291 struct imx_mu_con_priv *cp = chan->con_priv;
293 return priv->dcfg->tx(priv, cp, data);
296 static int imx_mu_startup(struct mbox_chan *chan)
298 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
299 struct imx_mu_con_priv *cp = chan->con_priv;
300 unsigned long irq_flag = IRQF_SHARED;
303 pm_runtime_get_sync(priv->dev);
304 if (cp->type == IMX_MU_TYPE_TXDB) {
305 /* Tx doorbell don't have ACK support */
306 tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet,
311 /* IPC MU should be with IRQF_NO_SUSPEND set */
312 if (!priv->dev->pm_domain)
313 irq_flag |= IRQF_NO_SUSPEND;
315 ret = request_irq(priv->irq, imx_mu_isr, irq_flag,
319 "Unable to acquire IRQ %d\n", priv->irq);
325 imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(cp->idx), 0);
327 case IMX_MU_TYPE_RXDB:
328 imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIEn(cp->idx), 0);
334 priv->suspend = true;
339 static void imx_mu_shutdown(struct mbox_chan *chan)
341 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
342 struct imx_mu_con_priv *cp = chan->con_priv;
344 if (cp->type == IMX_MU_TYPE_TXDB) {
345 tasklet_kill(&cp->txdb_tasklet);
346 pm_runtime_put_sync(priv->dev);
352 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx));
355 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(cp->idx));
357 case IMX_MU_TYPE_RXDB:
358 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_GIEn(cp->idx));
364 free_irq(priv->irq, chan);
365 pm_runtime_put_sync(priv->dev);
368 static const struct mbox_chan_ops imx_mu_ops = {
369 .send_data = imx_mu_send_data,
370 .startup = imx_mu_startup,
371 .shutdown = imx_mu_shutdown,
374 static struct mbox_chan *imx_mu_scu_xlate(struct mbox_controller *mbox,
375 const struct of_phandle_args *sp)
379 if (sp->args_count != 2) {
380 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
381 return ERR_PTR(-EINVAL);
384 type = sp->args[0]; /* channel type */
385 idx = sp->args[1]; /* index */
391 dev_err(mbox->dev, "Invalid chan idx: %d\n", idx);
394 case IMX_MU_TYPE_RXDB:
398 dev_err(mbox->dev, "Invalid chan type: %d\n", type);
399 return ERR_PTR(-EINVAL);
402 if (chan >= mbox->num_chans) {
403 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
404 return ERR_PTR(-EINVAL);
407 return &mbox->chans[chan];
410 static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
411 const struct of_phandle_args *sp)
415 if (sp->args_count != 2) {
416 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count);
417 return ERR_PTR(-EINVAL);
420 type = sp->args[0]; /* channel type */
421 idx = sp->args[1]; /* index */
422 chan = type * 4 + idx;
424 if (chan >= mbox->num_chans) {
425 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx);
426 return ERR_PTR(-EINVAL);
429 return &mbox->chans[chan];
432 static void imx_mu_init_generic(struct imx_mu_priv *priv)
436 for (i = 0; i < IMX_MU_CHANS; i++) {
437 struct imx_mu_con_priv *cp = &priv->con_priv[i];
441 cp->chan = &priv->mbox_chans[i];
442 priv->mbox_chans[i].con_priv = cp;
443 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
444 "imx_mu_chan[%i-%i]", cp->type, cp->idx);
447 priv->mbox.num_chans = IMX_MU_CHANS;
448 priv->mbox.of_xlate = imx_mu_xlate;
453 /* Set default MU configuration */
454 imx_mu_write(priv, 0, priv->dcfg->xCR);
457 static void imx_mu_init_scu(struct imx_mu_priv *priv)
461 for (i = 0; i < IMX_MU_SCU_CHANS; i++) {
462 struct imx_mu_con_priv *cp = &priv->con_priv[i];
464 cp->idx = i < 2 ? 0 : i - 2;
465 cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB;
466 cp->chan = &priv->mbox_chans[i];
467 priv->mbox_chans[i].con_priv = cp;
468 snprintf(cp->irq_desc, sizeof(cp->irq_desc),
469 "imx_mu_chan[%i-%i]", cp->type, cp->idx);
472 priv->mbox.num_chans = IMX_MU_SCU_CHANS;
473 priv->mbox.of_xlate = imx_mu_scu_xlate;
475 /* Set default MU configuration */
476 imx_mu_write(priv, 0, priv->dcfg->xCR);
479 static int imx_mu_probe(struct platform_device *pdev)
481 struct device *dev = &pdev->dev;
482 struct device_node *np = dev->of_node;
483 struct imx_mu_priv *priv;
484 const struct imx_mu_dcfg *dcfg;
487 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
493 priv->base = devm_platform_ioremap_resource(pdev, 0);
494 if (IS_ERR(priv->base))
495 return PTR_ERR(priv->base);
497 priv->irq = platform_get_irq(pdev, 0);
501 dcfg = of_device_get_match_data(dev);
506 priv->clk = devm_clk_get(dev, NULL);
507 if (IS_ERR(priv->clk)) {
508 if (PTR_ERR(priv->clk) != -ENOENT)
509 return PTR_ERR(priv->clk);
514 ret = clk_prepare_enable(priv->clk);
516 dev_err(dev, "Failed to enable clock\n");
520 priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
522 priv->dcfg->init(priv);
524 spin_lock_init(&priv->xcr_lock);
526 priv->mbox.dev = dev;
527 priv->mbox.ops = &imx_mu_ops;
528 priv->mbox.chans = priv->mbox_chans;
529 priv->mbox.txdone_irq = true;
531 platform_set_drvdata(pdev, priv);
533 ret = devm_mbox_controller_register(dev, &priv->mbox);
535 clk_disable_unprepare(priv->clk);
539 pm_runtime_enable(dev);
541 ret = pm_runtime_get_sync(dev);
543 pm_runtime_put_noidle(dev);
544 goto disable_runtime_pm;
547 ret = pm_runtime_put_sync(dev);
549 goto disable_runtime_pm;
551 clk_disable_unprepare(priv->clk);
553 priv->suspend = false;
558 pm_runtime_disable(dev);
559 clk_disable_unprepare(priv->clk);
563 static int imx_mu_remove(struct platform_device *pdev)
565 struct imx_mu_priv *priv = platform_get_drvdata(pdev);
567 pm_runtime_disable(priv->dev);
572 static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
573 .tx = imx_mu_generic_tx,
574 .rx = imx_mu_generic_rx,
575 .init = imx_mu_init_generic,
576 .xTR = {0x0, 0x4, 0x8, 0xc},
577 .xRR = {0x10, 0x14, 0x18, 0x1c},
582 static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
583 .tx = imx_mu_generic_tx,
584 .rx = imx_mu_generic_rx,
585 .init = imx_mu_init_generic,
586 .xTR = {0x20, 0x24, 0x28, 0x2c},
587 .xRR = {0x40, 0x44, 0x48, 0x4c},
592 static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
595 .init = imx_mu_init_scu,
596 .xTR = {0x0, 0x4, 0x8, 0xc},
597 .xRR = {0x10, 0x14, 0x18, 0x1c},
602 static const struct of_device_id imx_mu_dt_ids[] = {
603 { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
604 { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
605 { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
608 MODULE_DEVICE_TABLE(of, imx_mu_dt_ids);
610 static int __maybe_unused imx_mu_suspend_noirq(struct device *dev)
612 struct imx_mu_priv *priv = dev_get_drvdata(dev);
615 priv->xcr = imx_mu_read(priv, priv->dcfg->xCR);
620 static int __maybe_unused imx_mu_resume_noirq(struct device *dev)
622 struct imx_mu_priv *priv = dev_get_drvdata(dev);
625 * ONLY restore MU when context lost, the TIE could
626 * be set during noirq resume as there is MU data
627 * communication going on, and restore the saved
628 * value will overwrite the TIE and cause MU data
629 * send failed, may lead to system freeze. This issue
630 * is observed by testing freeze mode suspend.
632 if (!imx_mu_read(priv, priv->dcfg->xCR) && !priv->clk)
633 imx_mu_write(priv, priv->xcr, priv->dcfg->xCR);
638 static int __maybe_unused imx_mu_runtime_suspend(struct device *dev)
640 struct imx_mu_priv *priv = dev_get_drvdata(dev);
642 clk_disable_unprepare(priv->clk);
647 static int __maybe_unused imx_mu_runtime_resume(struct device *dev)
649 struct imx_mu_priv *priv = dev_get_drvdata(dev);
652 ret = clk_prepare_enable(priv->clk);
654 dev_err(dev, "failed to enable clock\n");
659 static const struct dev_pm_ops imx_mu_pm_ops = {
660 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_mu_suspend_noirq,
662 SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend,
663 imx_mu_runtime_resume, NULL)
666 static struct platform_driver imx_mu_driver = {
667 .probe = imx_mu_probe,
668 .remove = imx_mu_remove,
671 .of_match_table = imx_mu_dt_ids,
672 .pm = &imx_mu_pm_ops,
675 module_platform_driver(imx_mu_driver);
677 MODULE_AUTHOR("Oleksij Rempel <o.rempel@pengutronix.de>");
678 MODULE_DESCRIPTION("Message Unit driver for i.MX");
679 MODULE_LICENSE("GPL v2");