1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2020 Intel Corporation */
7 static struct igc_reg_test reg_test[] = {
8 { IGC_FCAL, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
9 { IGC_FCAH, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
10 { IGC_FCT, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
11 { IGC_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
12 { IGC_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
13 { IGC_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
14 { IGC_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
15 { IGC_FCRTH, 1, PATTERN_TEST, 0x0003FFF0, 0x0003FFF0 },
16 { IGC_FCTTV, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
17 { IGC_TIPG, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
18 { IGC_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
19 { IGC_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
20 { IGC_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
21 { IGC_TDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
22 { IGC_RCTL, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
23 { IGC_RCTL, 1, SET_READ_TEST, 0x04CFB2FE, 0x003FFFFB },
24 { IGC_RCTL, 1, SET_READ_TEST, 0x04CFB2FE, 0xFFFFFFFF },
25 { IGC_TCTL, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
26 { IGC_RA, 16, TABLE64_TEST_LO,
27 0xFFFFFFFF, 0xFFFFFFFF },
28 { IGC_RA, 16, TABLE64_TEST_HI,
29 0x900FFFFF, 0xFFFFFFFF },
30 { IGC_MTA, 128, TABLE32_TEST,
31 0xFFFFFFFF, 0xFFFFFFFF },
35 static bool reg_pattern_test(struct igc_adapter *adapter, u64 *data, int reg,
38 struct igc_hw *hw = &adapter->hw;
40 static const u32 test_pattern[] = {
41 0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF
44 for (pat = 0; pat < ARRAY_SIZE(test_pattern); pat++) {
46 wr32(reg, test_pattern[pat] & write);
48 if (val != (test_pattern[pat] & write & mask)) {
49 netdev_err(adapter->netdev,
50 "pattern test reg %04X failed: got 0x%08X expected 0x%08X",
51 reg, val, test_pattern[pat] & write & mask);
61 static bool reg_set_and_check(struct igc_adapter *adapter, u64 *data, int reg,
64 struct igc_hw *hw = &adapter->hw;
68 wr32(reg, write & mask);
70 if ((write & mask) != (val & mask)) {
71 netdev_err(adapter->netdev,
72 "set/check reg %04X test failed: got 0x%08X expected 0x%08X",
73 reg, (val & mask), (write & mask));
82 bool igc_reg_test(struct igc_adapter *adapter, u64 *data)
84 struct igc_reg_test *test = reg_test;
85 struct igc_hw *hw = &adapter->hw;
86 u32 value, before, after;
87 u32 i, toggle, b = false;
89 /* Because the status register is such a special case,
90 * we handle it separately from the rest of the register
91 * tests. Some bits are read-only, some toggle, and some
95 before = rd32(IGC_STATUS);
96 value = before & toggle;
97 wr32(IGC_STATUS, toggle);
98 after = rd32(IGC_STATUS) & toggle;
100 netdev_err(adapter->netdev,
101 "failed STATUS register test got: 0x%08X expected: 0x%08X",
106 /* restore previous status */
107 wr32(IGC_STATUS, before);
109 /* Perform the remainder of the register test, looping through
110 * the test table until we either fail or reach the null entry.
113 for (i = 0; i < test->array_len; i++) {
114 switch (test->test_type) {
116 b = reg_pattern_test(adapter, data,
117 test->reg + (i * 0x40),
122 b = reg_set_and_check(adapter, data,
123 test->reg + (i * 0x40),
127 case TABLE64_TEST_LO:
128 b = reg_pattern_test(adapter, data,
133 case TABLE64_TEST_HI:
134 b = reg_pattern_test(adapter, data,
135 test->reg + 4 + (i * 8),
140 b = reg_pattern_test(adapter, data,
155 bool igc_eeprom_test(struct igc_adapter *adapter, u64 *data)
157 struct igc_hw *hw = &adapter->hw;
161 if (hw->nvm.ops.validate(hw) != IGC_SUCCESS) {
169 bool igc_link_test(struct igc_adapter *adapter, u64 *data)
175 /* add delay to give enough time for autonegotioation to finish */
176 if (adapter->hw.mac.autoneg)
179 link_up = igc_has_link(adapter);