2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <adf_os_types.h>
37 #include <adf_os_dma.h>
38 #include <adf_os_timer.h>
39 #include <adf_os_lock.h>
40 #include <adf_os_io.h>
41 #include <adf_os_mem.h>
42 #include <adf_os_util.h>
43 #include <adf_os_stdtypes.h>
44 #include <adf_os_defer.h>
45 #include <adf_os_atomic.h>
48 #include <adf_net_wcmd.h>
52 #ifdef USE_HEADERLEN_RESV
56 #include <ieee80211_var.h>
57 #include "if_athrate.h"
58 #include "if_athvar.h"
61 #define ath_tgt_free_skb adf_nbuf_free
63 #define OFDM_PLCP_BITS 22
64 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
65 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
71 #define HT_LTF(_ns) (4 * (_ns))
72 #define SYMBOL_TIME(_ns) ((_ns) << 2) // ns * 4 us
73 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) // ns * 3.6 us
75 static a_uint16_t bits_per_symbol[][2] = {
77 { 26, 54 }, // 0: BPSK
78 { 52, 108 }, // 1: QPSK 1/2
79 { 78, 162 }, // 2: QPSK 3/4
80 { 104, 216 }, // 3: 16-QAM 1/2
81 { 156, 324 }, // 4: 16-QAM 3/4
82 { 208, 432 }, // 5: 64-QAM 2/3
83 { 234, 486 }, // 6: 64-QAM 3/4
84 { 260, 540 }, // 7: 64-QAM 5/6
85 { 52, 108 }, // 8: BPSK
86 { 104, 216 }, // 9: QPSK 1/2
87 { 156, 324 }, // 10: QPSK 3/4
88 { 208, 432 }, // 11: 16-QAM 1/2
89 { 312, 648 }, // 12: 16-QAM 3/4
90 { 416, 864 }, // 13: 64-QAM 2/3
91 { 468, 972 }, // 14: 64-QAM 3/4
92 { 520, 1080 }, // 15: 64-QAM 5/6
95 void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,
96 owl_txq_state_t txqstate);
97 static void ath_tgt_txqaddbuf(struct ath_softc_tgt *sc, struct ath_txq *txq,
98 struct ath_tx_buf *bf, struct ath_tx_desc *lastds);
99 void ath_rate_findrate_11n_Hardcoded(struct ath_softc_tgt *sc,
100 struct ath_rc_series series[]);
101 void ath_buf_set_rate_Hardcoded(struct ath_softc_tgt *sc,
102 struct ath_tx_buf *bf) ;
103 static a_int32_t ath_tgt_txbuf_setup(struct ath_softc_tgt *sc,
104 struct ath_tx_buf *bf, ath_data_hdr_t *dh);
105 static void ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
106 static void ath_tx_uc_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
107 static void ath_update_stats(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
108 void adf_print_buf(adf_nbuf_t buf);
109 static void ath_tgt_tx_enqueue(struct ath_txq *txq, struct ath_atx_tid *tid);
111 void ath_tgt_tx_comp_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
112 struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb);
114 void ath_tgt_tx_send_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
116 static void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
117 static void ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
119 extern a_int32_t ath_chainmask_sel_logic(void *);
120 static a_int32_t ath_get_pktlen(struct ath_tx_buf *bf, a_int32_t hdrlen);
121 static void ath_tgt_txq_schedule(struct ath_softc_tgt *sc, struct ath_txq *txq);
123 typedef void (*ath_ft_set_atype_t)(struct ath_softc_tgt *sc, struct ath_buf *bf);
126 ath_tx_set_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
129 ath_bar_tx(struct ath_softc_tgt *sc, ath_atx_tid_t *tid, struct ath_tx_buf *bf);
131 ath_tx_update_baw(ath_atx_tid_t *tid, int seqno);
133 ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
134 ath_tx_bufhead *bf_q, struct ath_tx_buf **bar);
137 ath_tx_comp_aggr_error(struct ath_softc_tgt *sc, struct ath_tx_buf *bf, ath_atx_tid_t *tid);
139 void ath_tx_addto_baw(ath_atx_tid_t *tid, struct ath_tx_buf *bf);
140 static inline void ath_tx_retry_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
141 static void ath_tx_comp_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
142 static void ath_update_aggr_stats(struct ath_softc_tgt *sc, struct ath_tx_desc *ds,
143 int nframes, int nbad);
144 static inline void ath_aggr_resume_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
145 static void ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
147 int ath_tgt_tx_add_to_aggr(struct ath_softc_tgt *sc,
148 struct ath_buf *bf,int datatype,
149 ath_atx_tid_t *tid, int is_burst);
151 struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb)
156 adf_nbuf_peek_header(skb, &anbdata, &anblen);
158 return((struct ieee80211_frame *)anbdata);
161 #undef adf_os_cpu_to_le16
163 static a_uint16_t adf_os_cpu_to_le16(a_uint16_t x)
165 return ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8));
169 ath_aggr_resume_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
173 txq = TID_TO_ACTXQ(tid->tidno);
176 if (asf_tailq_empty(&tid->buf_q))
179 ath_tgt_tx_enqueue(txq, tid);
180 ath_tgt_txq_schedule(sc, txq);
184 ath_aggr_pause_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
189 static a_uint32_t ath_pkt_duration(struct ath_softc_tgt *sc,
190 a_uint8_t rix, struct ath_tx_buf *bf,
191 a_int32_t width, a_int32_t half_gi)
193 const HAL_RATE_TABLE *rt = sc->sc_currates;
194 a_uint32_t nbits, nsymbits, duration, nsymbols;
199 pktlen = bf->bf_isaggr ? bf->bf_al : bf->bf_pktlen;
200 rc = rt->info[rix].rateCode;
203 return ath_hal_computetxtime(sc->sc_ah, rt, pktlen, rix,
206 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
207 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
208 nsymbols = (nbits + nsymbits - 1) / nsymbits;
211 duration = SYMBOL_TIME(nsymbols);
213 duration = SYMBOL_TIME_HALFGI(nsymbols);
215 streams = HT_RC_2_STREAMS(rc);
216 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
221 static void ath_dma_map(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
223 adf_nbuf_t skb = bf->bf_skb;
225 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
226 adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, skb, ADF_OS_DMA_TO_DEVICE);
229 static void ath_dma_unmap(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
231 adf_nbuf_t skb = bf->bf_skb;
233 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
234 adf_nbuf_unmap( sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE);
237 static void ath_filltxdesc(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
239 struct ath_tx_desc *ds0, *ds = bf->bf_desc;
240 struct ath_hal *ah = sc->sc_ah;
244 adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info);
246 for (i = 0; i < bf->bf_dmamap_info.nsegs; i++, ds++) {
248 ds->ds_data = bf->bf_dmamap_info.dma_segs[i].paddr;
250 if (i == (bf->bf_dmamap_info.nsegs - 1)) {
254 ds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, i+1);
256 ah->ah_fillTxDesc(ah, ds
257 , bf->bf_dmamap_info.dma_segs[i].len
259 , i == (bf->bf_dmamap_info.nsegs - 1)
264 static void ath_tx_tgt_setds(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
266 struct ath_tx_desc *ds = bf->bf_desc;
267 struct ath_hal *ah = sc->sc_ah;
269 switch (bf->bf_protmode) {
270 case IEEE80211_PROT_RTSCTS:
271 bf->bf_flags |= HAL_TXDESC_RTSENA;
273 case IEEE80211_PROT_CTSONLY:
274 bf->bf_flags |= HAL_TXDESC_CTSENA;
280 ah->ah_set11nTxDesc(ah, ds
286 , bf->bf_flags | HAL_TXDESC_INTREQ);
288 ath_filltxdesc(sc, bf);
291 static struct ath_tx_buf *ath_buf_toggle(struct ath_softc_tgt *sc,
292 struct ath_tx_buf *bf,
295 struct ath_tx_buf *tmp = NULL;
296 adf_nbuf_t buf = NULL;
298 adf_os_assert(sc->sc_txbuf_held != NULL);
300 tmp = sc->sc_txbuf_held;
303 ath_dma_unmap(sc, bf);
304 adf_nbuf_queue_init(&tmp->bf_skbhead);
305 buf = adf_nbuf_queue_remove(&bf->bf_skbhead);
307 adf_nbuf_queue_add(&tmp->bf_skbhead, buf);
309 adf_os_assert(adf_nbuf_queue_len(&bf->bf_skbhead) == 0);
311 tmp->bf_next = bf->bf_next;
312 tmp->bf_endpt = bf->bf_endpt;
313 tmp->bf_tidno = bf->bf_tidno;
314 tmp->bf_skb = bf->bf_skb;
315 tmp->bf_node = bf->bf_node;
316 tmp->bf_isaggr = bf->bf_isaggr;
317 tmp->bf_flags = bf->bf_flags;
318 tmp->bf_state = bf->bf_state;
319 tmp->bf_retries = bf->bf_retries;
320 tmp->bf_comp = bf->bf_comp;
321 tmp->bf_nframes = bf->bf_nframes;
322 tmp->bf_cookie = bf->bf_cookie;
334 ath_dma_map(sc, tmp);
335 ath_tx_tgt_setds(sc, tmp);
338 sc->sc_txbuf_held = bf;
343 static void ath_tgt_skb_free(struct ath_softc_tgt *sc,
344 adf_nbuf_queue_t *head,
345 HTC_ENDPOINT_ID endpt)
349 while (adf_nbuf_queue_len(head) != 0) {
350 tskb = adf_nbuf_queue_remove(head);
351 ath_free_tx_skb(sc->tgt_htc_handle,endpt,tskb);
355 static void ath_buf_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
357 ath_dma_unmap(sc, bf);
358 ath_tgt_skb_free(sc, &bf->bf_skbhead,bf->bf_endpt);
361 bf = ath_buf_toggle(sc, bf, 0);
363 asf_tailq_insert_tail(&sc->sc_txbuf, bf, bf_list);
367 static void ath_buf_set_rate(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
369 struct ath_hal *ah = sc->sc_ah;
370 const HAL_RATE_TABLE *rt;
371 struct ath_tx_desc *ds = bf->bf_desc;
372 HAL_11N_RATE_SERIES series[4];
374 a_uint8_t rix, cix, rtsctsrate;
375 a_uint32_t ctsduration = 0;
376 a_int32_t prot_mode = AH_FALSE;
378 rt = sc->sc_currates;
379 rix = bf->bf_rcs[0].rix;
380 flags = (bf->bf_flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA));
381 cix = rt->info[sc->sc_protrix].controlRate;
383 if (bf->bf_protmode != IEEE80211_PROT_NONE &&
384 (rt->info[rix].phy == IEEE80211_T_OFDM ||
385 rt->info[rix].phy == IEEE80211_T_HT) &&
386 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
387 cix = rt->info[sc->sc_protrix].controlRate;
390 if (ath_hal_htsupported(ah) && (!bf->bf_ismcast))
391 flags = HAL_TXDESC_RTSENA;
394 if (bf->bf_rcs[i].tries) {
395 cix = rt->info[bf->bf_rcs[i].rix].controlRate;
402 adf_os_mem_set(series, 0, sizeof(HAL_11N_RATE_SERIES) * 4);
404 for (i = 0; i < 4; i++) {
405 if (!bf->bf_rcs[i].tries)
408 rix = bf->bf_rcs[i].rix;
410 series[i].Rate = rt->info[rix].rateCode |
411 (bf->bf_shpream ? rt->info[rix].shortPreamble : 0);
413 series[i].Tries = bf->bf_rcs[i].tries;
415 series[i].RateFlags = ((bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
416 HAL_RATESERIES_RTS_CTS : 0 ) |
417 ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
418 HAL_RATESERIES_2040 : 0 ) |
419 ((bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG) ?
420 HAL_RATESERIES_HALFGI : 0 ) |
421 ((bf->bf_rcs[i].flags & ATH_RC_TX_STBC_FLAG) ?
422 HAL_RATESERIES_STBC: 0);
424 series[i].RateFlags = ((bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
425 HAL_RATESERIES_RTS_CTS : 0 ) |
426 ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
427 HAL_RATESERIES_2040 : 0 ) |
428 ((bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG) ?
429 HAL_RATESERIES_HALFGI : 0 );
431 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
432 (bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) != 0,
433 (bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG));
435 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
438 series[i].RateFlags |= HAL_RATESERIES_RTS_CTS;
440 if (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG)
441 series[i].RateFlags |= HAL_RATESERIES_RTS_CTS;
444 rtsctsrate = rt->info[cix].rateCode |
445 (bf->bf_shpream ? rt->info[cix].shortPreamble : 0);
447 ah->ah_set11nRateScenario(ah, ds, 1,
448 rtsctsrate, ctsduration,
453 static void ath_tgt_rate_findrate(struct ath_softc_tgt *sc,
454 struct ath_node_target *an,
455 a_int32_t shortPreamble,
461 struct ath_rc_series series[],
464 ath_rate_findrate(sc, an, 1, frameLen, 10, 4, 1,
465 ATH_RC_PROBE_ALLOWED, series, isProbe);
468 static void owl_tgt_tid_init(struct ath_atx_tid *tid)
472 tid->seq_start = tid->seq_next = 0;
473 tid->baw_size = WME_MAX_BA;
474 tid->baw_head = tid->baw_tail = 0;
477 tid->sched = AH_FALSE;
479 asf_tailq_init(&tid->buf_q);
481 for (i = 0; i < ATH_TID_MAX_BUFS; i++) {
482 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, i);
486 static void owl_tgt_tid_cleanup(struct ath_softc_tgt *sc,
487 struct ath_atx_tid *tid)
494 tid->flag &= ~TID_CLEANUP_INPROGRES;
496 if (tid->flag & TID_REINITIALIZE) {
497 adf_os_print("TID REINIT DONE for tid %p\n", tid);
498 tid->flag &= ~TID_REINITIALIZE;
499 owl_tgt_tid_init(tid);
501 ath_aggr_resume_tid(sc, tid);
505 void owl_tgt_node_init(struct ath_node_target * an)
507 struct ath_atx_tid *tid;
510 for (tidno = 0, tid = &an->tid[tidno]; tidno < WME_NUM_TID;tidno++, tid++) {
514 if ( tid->flag & TID_CLEANUP_INPROGRES ) {
515 tid->flag |= TID_REINITIALIZE;
516 adf_os_print("tid[%p]->incomp is not 0: %d\n",
519 owl_tgt_tid_init(tid);
524 void ath_tx_status_clear(struct ath_softc_tgt *sc)
528 for (i = 0; i < 2; i++) {
529 sc->tx_status[i].cnt = 0;
533 static WMI_TXSTATUS_EVENT *ath_tx_status_get(struct ath_softc_tgt *sc)
535 WMI_TXSTATUS_EVENT *txs = NULL;
538 for (i = 0; i < 2; i++) {
539 if (sc->tx_status[i].cnt < HTC_MAX_TX_STATUS) {
540 txs = &sc->tx_status[i];
548 void ath_tx_status_update(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
550 struct ath_tx_desc *ds = bf->bf_lastds;
551 WMI_TXSTATUS_EVENT *txs;
553 if (sc->sc_tx_draining)
556 txs = ath_tx_status_get(sc);
560 txs->txstatus[txs->cnt].cookie = bf->bf_cookie;
561 txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID);
563 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
564 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_FILT;
566 if (!(ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) &&
567 !(ds->ds_txstat.ts_status & HAL_TXERR_FIFO) &&
568 !(ds->ds_txstat.ts_status & HAL_TXERR_TIMER_EXPIRED) &&
569 !(ds->ds_txstat.ts_status & HAL_TXERR_FILT))
570 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_ACK;
572 ath_tx_status_update_rate(sc, bf->bf_rcs, ds->ds_txstat.ts_rate, txs);
577 void ath_tx_status_update_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
578 struct ath_tx_desc *ds, struct ath_rc_series rcs[],
581 WMI_TXSTATUS_EVENT *txs;
583 if (sc->sc_tx_draining)
586 txs = ath_tx_status_get(sc);
590 txs->txstatus[txs->cnt].cookie = bf->bf_cookie;
591 txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID);
594 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_ACK;
597 ath_tx_status_update_rate(sc, rcs, ds->ds_txstat.ts_rate, txs);
602 void ath_tx_status_send(struct ath_softc_tgt *sc)
606 if (sc->sc_tx_draining)
609 for (i = 0; i < 2; i++) {
610 if (sc->tx_status[i].cnt) {
611 wmi_event(sc->tgt_wmi_handle, WMI_TXSTATUS_EVENTID,
612 &sc->tx_status[i], sizeof(WMI_TXSTATUS_EVENT));
613 /* FIXME: Handle failures. */
614 sc->tx_status[i].cnt = 0;
619 static void owltgt_tx_process_cabq(struct ath_softc_tgt *sc, struct ath_txq *txq)
621 struct ath_hal *ah = sc->sc_ah;
622 ah->ah_setInterrupts(ah, sc->sc_imask & ~HAL_INT_SWBA);
623 owltgt_tx_processq(sc, txq, OWL_TXQ_ACTIVE);
624 ah->ah_setInterrupts(ah, sc->sc_imask);
627 void owl_tgt_tx_tasklet(TQUEUE_ARG data)
629 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
633 ath_tx_status_clear(sc);
635 for (i = 0; i < (HAL_NUM_TX_QUEUES - 6); i++) {
636 txq = ATH_TXQ(sc, i);
638 if (ATH_TXQ_SETUP(sc, i)) {
639 if (txq == sc->sc_cabq)
640 owltgt_tx_process_cabq(sc, txq);
642 owltgt_tx_processq(sc, txq, OWL_TXQ_ACTIVE);
646 ath_tx_status_send(sc);
649 void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,
650 owl_txq_state_t txqstate)
652 struct ath_tx_buf *bf;
653 struct ath_tx_desc *ds;
654 struct ath_hal *ah = sc->sc_ah;
658 if (asf_tailq_empty(&txq->axq_q)) {
659 txq->axq_link = NULL;
660 txq->axq_linkbuf = NULL;
664 bf = asf_tailq_first(&txq->axq_q);
667 status = ah->ah_procTxDesc(ah, ds);
669 if (status == HAL_EINPROGRESS) {
670 if (txqstate == OWL_TXQ_ACTIVE)
672 else if (txqstate == OWL_TXQ_STOPPED) {
673 __stats(sc, tx_stopfiltered);
674 ds->ds_txstat.ts_flags = 0;
675 ds->ds_txstat.ts_status = HAL_OK;
677 ds->ds_txstat.ts_flags = HAL_TX_SW_FILTERED;
681 ATH_TXQ_REMOVE_HEAD(txq, bf, bf_list);
682 if ((asf_tailq_empty(&txq->axq_q))) {
683 __stats(sc, tx_qnull);
684 txq->axq_link = NULL;
685 txq->axq_linkbuf = NULL;
691 ath_tx_status_update(sc, bf);
692 ath_buf_comp(sc, bf);
695 if (txqstate == OWL_TXQ_ACTIVE) {
696 ath_tgt_txq_schedule(sc, txq);
701 static struct ieee80211_frame* ATH_SKB2_WH(adf_nbuf_t skb)
706 adf_nbuf_peek_header(skb, &anbdata, &anblen);
707 return((struct ieee80211_frame *)anbdata);
711 ath_tgt_tid_drain(struct ath_softc_tgt *sc, struct ath_atx_tid *tid)
713 struct ath_tx_buf *bf;
715 while (!asf_tailq_empty(&tid->buf_q)) {
716 TAILQ_DEQ(&tid->buf_q, bf, bf_list);
717 ath_tx_freebuf(sc, bf);
720 tid->seq_next = tid->seq_start;
721 tid->baw_tail = tid->baw_head;
724 static void ath_tgt_tx_comp_normal(struct ath_softc_tgt *sc,
725 struct ath_tx_buf *bf)
727 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
728 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
730 if (tid->flag & TID_CLEANUP_INPROGRES) {
731 owl_tgt_tid_cleanup(sc, tid);
735 ath_tx_uc_comp(sc, bf);
738 ath_tx_freebuf(sc, bf);
741 static struct ieee80211_node_target * ath_tgt_find_node(struct ath_softc_tgt *sc,
742 a_int32_t node_index)
744 struct ath_node_target *an;
745 struct ieee80211_node_target *ni;
747 if (node_index > TARGET_NODE_MAX)
750 an = &sc->sc_sta[node_index];
754 if (ni->ni_vap == NULL) {
763 static struct ath_tx_buf* ath_tx_buf_alloc(struct ath_softc_tgt *sc)
765 struct ath_tx_buf *bf = NULL;
767 bf = asf_tailq_first(&sc->sc_txbuf);
769 adf_os_mem_set(&bf->bf_state, 0, sizeof(struct ath_buf_state));
770 asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
778 struct ath_tx_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc,
779 adf_nbuf_t skb, ath_data_hdr_t *dh)
781 struct ath_tx_buf *bf;
782 struct ieee80211_node_target *ni;
783 struct ath_atx_tid *tid;
785 ni = ath_tgt_find_node(sc, dh->ni_index);
789 tid = ATH_AN_2_TID(ATH_NODE_TARGET(ni), dh->tidno);
790 if (tid->flag & TID_REINITIALIZE) {
791 adf_os_print("drop frame due to TID reinit\n");
795 bf = ath_tx_buf_alloc(sc);
797 __stats(sc, tx_nobufs);
801 bf->bf_tidno = dh->tidno;
802 bf->bf_txq = TID_TO_ACTXQ(bf->bf_tidno);
803 bf->bf_keytype = dh->keytype;
804 bf->bf_keyix = dh->keyix;
805 bf->bf_protmode = dh->flags & (IEEE80211_PROT_RTSCTS | IEEE80211_PROT_CTSONLY);
808 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
809 skb = adf_nbuf_queue_first(&(bf->bf_skbhead));
811 if (adf_nbuf_queue_len(&(bf->bf_skbhead)) == 0) {
812 __stats(sc, tx_noskbs);
820 ath_tgt_txbuf_setup(sc, bf, dh);
822 ath_tx_tgt_setds(sc, bf);
827 static void ath_tgt_tx_seqno_normal(struct ath_tx_buf *bf)
829 struct ieee80211_node_target *ni = bf->bf_node;
830 struct ath_node_target *an = ATH_NODE_TARGET(ni);
831 struct ieee80211_frame *wh = ATH_SKB_2_WH(bf->bf_skb);
832 struct ath_atx_tid *tid = ATH_AN_2_TID(an, bf->bf_tidno);
834 u_int8_t fragno = (wh->i_seq[0] & 0xf);
836 INCR(ni->ni_txseqmgmt, IEEE80211_SEQ_MAX);
838 bf->bf_seqno = (tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
840 *(u_int16_t *)wh->i_seq = adf_os_cpu_to_le16(bf->bf_seqno);
841 wh->i_seq[0] |= fragno;
843 if (!(wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG))
844 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
847 static a_int32_t ath_key_setup(struct ieee80211_node_target *ni,
848 struct ath_tx_buf *bf)
850 struct ieee80211_frame *wh = ATH_SKB_2_WH(bf->bf_skb);
852 if (!(wh->i_fc[1] & IEEE80211_FC1_WEP)) {
853 bf->bf_keytype = HAL_KEY_TYPE_CLEAR;
854 bf->bf_keyix = HAL_TXKEYIX_INVALID;
858 switch (bf->bf_keytype) {
859 case HAL_KEY_TYPE_WEP:
860 bf->bf_pktlen += IEEE80211_WEP_ICVLEN;
862 case HAL_KEY_TYPE_AES:
863 bf->bf_pktlen += IEEE80211_WEP_MICLEN;
865 case HAL_KEY_TYPE_TKIP:
866 bf->bf_pktlen += IEEE80211_WEP_ICVLEN;
872 if (bf->bf_keytype == HAL_KEY_TYPE_AES ||
873 bf->bf_keytype == HAL_KEY_TYPE_TKIP)
874 ieee80211_tgt_crypto_encap(wh, ni, bf->bf_keytype);
879 static void ath_tgt_txq_add_ucast(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
881 struct ath_hal *ah = sc->sc_ah;
884 volatile a_int32_t txe_val;
890 status = ah->ah_procTxDesc(ah, bf->bf_lastds);
892 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
894 if (txq->axq_link == NULL) {
895 ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
897 *txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
899 txe_val = OS_REG_READ(ah, 0x840);
900 if (!(txe_val & (1<< txq->axq_qnum)))
901 ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
904 txq->axq_link = &bf->bf_lastds->ds_link;
905 ah->ah_startTxDma(ah, txq->axq_qnum);
908 static a_int32_t ath_tgt_txbuf_setup(struct ath_softc_tgt *sc,
909 struct ath_tx_buf *bf,
913 struct ieee80211_frame *wh = ATH_SKB2_WH(bf->bf_skb);
915 a_uint32_t flags = adf_os_ntohl(dh->flags);
917 ath_tgt_tx_seqno_normal(bf);
919 bf->bf_txq_add = ath_tgt_txq_add_ucast;
920 bf->bf_hdrlen = ieee80211_anyhdrsize(wh);
921 bf->bf_pktlen = ath_get_pktlen(bf, bf->bf_hdrlen);
922 bf->bf_ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
924 if ((retval = ath_key_setup(bf->bf_node, bf)) < 0)
927 if (flags & ATH_SHORT_PREAMBLE)
928 bf->bf_shpream = AH_TRUE;
930 bf->bf_shpream = AH_FALSE;
932 bf->bf_flags = HAL_TXDESC_CLRDMASK;
933 bf->bf_atype = HAL_PKT_TYPE_NORMAL;
939 ath_get_pktlen(struct ath_tx_buf *bf, a_int32_t hdrlen)
941 adf_nbuf_t skb = bf->bf_skb;
944 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
945 pktlen = adf_nbuf_len(skb);
947 pktlen -= (hdrlen & 3);
948 pktlen += IEEE80211_CRC_LEN;
954 ath_tgt_tx_send_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
956 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
957 struct ath_rc_series rcs[4];
958 struct ath_rc_series mrcs[4];
959 a_int32_t shortPreamble = 0;
960 a_int32_t isProbe = 0;
962 adf_os_mem_set(rcs, 0, sizeof(struct ath_rc_series)*4 );
963 adf_os_mem_set(mrcs, 0, sizeof(struct ath_rc_series)*4 );
965 if (!bf->bf_ismcast) {
966 ath_tgt_rate_findrate(sc, an, shortPreamble,
969 ath_hal_memcpy(bf->bf_rcs, rcs, sizeof(rcs));
971 mrcs[1].tries = mrcs[2].tries = mrcs[3].tries = 0;
972 mrcs[1].rix = mrcs[2].rix = mrcs[3].rix = 0;
976 ath_hal_memcpy(bf->bf_rcs, mrcs, sizeof(mrcs));
979 ath_buf_set_rate(sc, bf);
980 bf->bf_txq_add(sc, bf);
984 ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
987 struct ath_tx_desc *bfd = NULL;
988 struct ath_hal *ah = sc->sc_ah;
990 for (bfd = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; bfd++, i++) {
991 ah->ah_clr11nAggr(ah, bfd);
992 ah->ah_set11nBurstDuration(ah, bfd, 0);
993 ah->ah_set11nVirtualMoreFrag(ah, bfd, 0);
996 ath_dma_unmap(sc, bf);
998 ath_tgt_skb_free(sc, &bf->bf_skbhead,bf->bf_endpt);
1004 bf = ath_buf_toggle(sc, bf, 0);
1006 bf->bf_isretried = 0;
1009 asf_tailq_insert_tail(&sc->sc_txbuf, bf, bf_list);
1013 ath_tx_uc_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1015 ath_tx_status_update(sc, bf);
1016 ath_update_stats(sc, bf);
1017 ath_rate_tx_complete(sc, ATH_NODE_TARGET(bf->bf_node),
1018 bf->bf_lastds, bf->bf_rcs, 1, 0);
1022 ath_update_stats(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1024 struct ath_tx_desc *ds = bf->bf_desc;
1027 if (ds->ds_txstat.ts_status == 0) {
1028 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE)
1029 sc->sc_tx_stats.ast_tx_altrate++;
1031 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY)
1032 sc->sc_tx_stats.ast_tx_xretries++;
1033 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO)
1034 sc->sc_tx_stats.ast_tx_fifoerr++;
1035 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
1036 sc->sc_tx_stats.ast_tx_filtered++;
1037 if (ds->ds_txstat.ts_status & HAL_TXERR_TIMER_EXPIRED)
1038 sc->sc_tx_stats.ast_tx_timer_exp++;
1040 sr = ds->ds_txstat.ts_shortretry;
1041 lr = ds->ds_txstat.ts_longretry;
1042 sc->sc_tx_stats.ast_tx_shortretry += sr;
1043 sc->sc_tx_stats.ast_tx_longretry += lr;
1047 ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t hdr_buf, adf_nbuf_t skb,
1048 HTC_ENDPOINT_ID endpt)
1050 struct ieee80211_node_target *ni;
1051 struct ieee80211vap_target *vap;
1052 struct ath_vap_target *avp;
1053 struct ath_hal *ah = sc->sc_ah;
1054 a_uint8_t rix, txrate, ctsrate, cix = 0xff, *data;
1055 a_uint32_t ivlen = 0, icvlen = 0, subtype, flags, ctsduration;
1056 a_int32_t i, iswep, ismcast, hdrlen, pktlen, try0, len;
1057 struct ath_tx_desc *ds=NULL;
1058 struct ath_txq *txq=NULL;
1059 struct ath_tx_buf *bf;
1061 const HAL_RATE_TABLE *rt;
1062 HAL_BOOL shortPreamble;
1063 struct ieee80211_frame *wh;
1064 struct ath_rc_series rcs[4];
1065 HAL_11N_RATE_SERIES series[4];
1070 adf_nbuf_peek_header(skb, &data, &len);
1071 adf_nbuf_pull_head(skb, sizeof(ath_mgt_hdr_t));
1073 adf_nbuf_peek_header(hdr_buf, &data, &len);
1076 adf_os_assert(len >= sizeof(ath_mgt_hdr_t));
1078 mh = (ath_mgt_hdr_t *)data;
1079 adf_nbuf_peek_header(skb, &data, &len);
1080 wh = (struct ieee80211_frame *)data;
1082 adf_os_mem_set(rcs, 0, sizeof(struct ath_rc_series)*4);
1083 adf_os_mem_set(series, 0, sizeof(HAL_11N_RATE_SERIES)*4);
1085 bf = asf_tailq_first(&sc->sc_txbuf);
1089 asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
1091 ni = ath_tgt_find_node(sc, mh->ni_index);
1095 bf->bf_endpt = endpt;
1096 bf->bf_cookie = mh->cookie;
1097 bf->bf_protmode = mh->flags & (IEEE80211_PROT_RTSCTS | IEEE80211_PROT_CTSONLY);
1098 txq = &sc->sc_txq[1];
1099 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
1100 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1101 hdrlen = ieee80211_anyhdrsize(wh);
1103 keyix = HAL_TXKEYIX_INVALID;
1104 pktlen -= (hdrlen & 3);
1105 pktlen += IEEE80211_CRC_LEN;
1110 adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, skb, ADF_OS_DMA_TO_DEVICE);
1113 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
1116 rt = sc->sc_currates;
1117 adf_os_assert(rt != NULL);
1119 if (mh->flags == ATH_SHORT_PREAMBLE)
1120 shortPreamble = AH_TRUE;
1122 shortPreamble = AH_FALSE;
1124 flags = HAL_TXDESC_CLRDMASK;
1126 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
1127 case IEEE80211_FC0_TYPE_MGT:
1128 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
1130 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
1131 atype = HAL_PKT_TYPE_PROBE_RESP;
1132 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
1133 atype = HAL_PKT_TYPE_ATIM;
1135 atype = HAL_PKT_TYPE_NORMAL;
1139 atype = HAL_PKT_TYPE_NORMAL;
1143 avp = &sc->sc_vap[mh->vap_index];
1145 rcs[0].rix = ath_get_minrateidx(sc, avp);
1146 rcs[0].tries = ATH_TXMAXTRY;
1149 adf_os_mem_copy(bf->bf_rcs, rcs, sizeof(rcs));
1151 try0 = rcs[0].tries;
1152 txrate = rt->info[rix].rateCode;
1155 txrate |= rt->info[rix].shortPreamble;
1162 flags |= HAL_TXDESC_NOACK;
1164 } else if (pktlen > vap->iv_rtsthreshold) {
1165 flags |= HAL_TXDESC_RTSENA;
1166 cix = rt->info[rix].controlRate;
1169 if ((bf->bf_protmode != IEEE80211_PROT_NONE) &&
1170 rt->info[rix].phy == IEEE80211_T_OFDM &&
1171 (flags & HAL_TXDESC_NOACK) == 0) {
1172 cix = rt->info[sc->sc_protrix].controlRate;
1173 sc->sc_tx_stats.ast_tx_protect++;
1176 *(a_uint16_t *)&wh->i_seq[0] = adf_os_cpu_to_le16(ni->ni_txseqmgmt <<
1177 IEEE80211_SEQ_SEQ_SHIFT);
1178 INCR(ni->ni_txseqmgmt, IEEE80211_SEQ_MAX);
1181 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) {
1182 adf_os_assert(cix != 0xff);
1183 ctsrate = rt->info[cix].rateCode;
1184 if (shortPreamble) {
1185 ctsrate |= rt->info[cix].shortPreamble;
1186 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
1187 ctsduration += rt->info[cix].spAckDuration;
1188 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
1189 ctsduration += rt->info[cix].spAckDuration;
1191 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
1192 ctsduration += rt->info[cix].lpAckDuration;
1193 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
1194 ctsduration += rt->info[cix].lpAckDuration;
1196 ctsduration += ath_hal_computetxtime(ah,
1197 rt, pktlen, rix, shortPreamble);
1202 flags |= HAL_TXDESC_INTREQ;
1204 ah->ah_setupTxDesc(ah, ds
1217 , ATH_COMP_PROC_NO_COMP_NO_CCS);
1219 bf->bf_flags = flags;
1222 * Set key type in tx desc while sending the encrypted challenge to AP
1223 * in Auth frame 3 of Shared Authentication, owl needs this.
1225 if (iswep && (keyix != HAL_TXKEYIX_INVALID) &&
1226 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == IEEE80211_FC0_SUBTYPE_AUTH)
1227 ah->ah_fillKeyTxDesc(ah, ds, mh->keytype);
1229 ath_filltxdesc(sc, bf);
1231 for (i=0; i<4; i++) {
1232 series[i].Tries = 2;
1233 series[i].Rate = txrate;
1234 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
1235 series[i].RateFlags = 0;
1237 ah->ah_set11nRateScenario(ah, ds, 0, ctsrate, ctsduration, series, 4, 0);
1238 ath_tgt_txqaddbuf(sc, txq, bf, bf->bf_lastds);
1242 HTC_ReturnBuffers(sc->tgt_htc_handle, endpt, skb);
1247 ath_tgt_txqaddbuf(struct ath_softc_tgt *sc,
1248 struct ath_txq *txq, struct ath_tx_buf *bf,
1249 struct ath_tx_desc *lastds)
1251 struct ath_hal *ah = sc->sc_ah;
1253 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
1255 if (txq->axq_link == NULL) {
1256 ah->ah_setTxDP(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
1258 *txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
1261 txq->axq_link = &lastds->ds_link;
1262 ah->ah_startTxDma(ah, txq->axq_qnum);
1265 void ath_tgt_handle_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1268 struct ath_node_target *an;
1270 an = (struct ath_node_target *)bf->bf_node;
1273 tid = &an->tid[bf->bf_tidno];
1276 bf->bf_comp = ath_tgt_tx_comp_normal;
1277 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1278 ath_tgt_tx_send_normal(sc, bf);
1282 ath_tgt_tx_enqueue(struct ath_txq *txq, struct ath_atx_tid *tid)
1290 tid->sched = AH_TRUE;
1291 asf_tailq_insert_tail(&txq->axq_tidq, tid, tid_qelem);
1295 ath_tgt_txq_schedule(struct ath_softc_tgt *sc, struct ath_txq *txq)
1297 struct ath_atx_tid *tid;
1303 TAILQ_DEQ(&txq->axq_tidq, tid, tid_qelem);
1308 tid->sched = AH_FALSE;
1313 if (!(tid->flag & TID_AGGR_ENABLED))
1314 ath_tgt_tx_sched_normal(sc,tid);
1316 ath_tgt_tx_sched_aggr(sc,tid);
1320 if (!asf_tailq_empty(&tid->buf_q)) {
1321 ath_tgt_tx_enqueue(txq, tid);
1324 } while (!asf_tailq_empty(&txq->axq_tidq) && !bdone);
1328 ath_tgt_handle_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1331 struct ath_node_target *an;
1332 struct ath_txq *txq = bf->bf_txq;
1333 a_bool_t queue_frame, within_baw;
1335 an = (struct ath_node_target *)bf->bf_node;
1338 tid = &an->tid[bf->bf_tidno];
1341 bf->bf_comp = ath_tgt_tx_comp_aggr;
1343 within_baw = BAW_WITHIN(tid->seq_start, tid->baw_size,
1344 SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1346 queue_frame = ( (txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) ||
1347 (!asf_tailq_empty(&tid->buf_q)) ||
1348 (tid->paused) || (!within_baw) );
1351 asf_tailq_insert_tail(&tid->buf_q, bf, bf_list);
1352 ath_tgt_tx_enqueue(txq, tid);
1354 ath_tx_addto_baw(tid, bf);
1355 __stats(sc, txaggr_nframes);
1356 ath_tgt_tx_send_normal(sc, bf);
1361 ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
1363 struct ath_tx_buf *bf;
1364 struct ath_txq *txq =TID_TO_ACTXQ(tid->tidno);;
1367 if (asf_tailq_empty(&tid->buf_q))
1370 bf = asf_tailq_first(&tid->buf_q);
1371 asf_tailq_remove(&tid->buf_q, bf, bf_list);
1372 ath_tgt_tx_send_normal(sc, bf);
1374 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH);
1378 ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
1380 struct ath_tx_buf *bf, *bf_last;
1381 ATH_AGGR_STATUS status;
1382 ath_tx_bufhead bf_q;
1383 struct ath_txq *txq = TID_TO_ACTXQ(tid->tidno);
1384 struct ath_tx_desc *ds = NULL;
1385 struct ath_hal *ah = sc->sc_ah;
1389 if (asf_tailq_empty(&tid->buf_q))
1393 if (asf_tailq_empty(&tid->buf_q))
1396 asf_tailq_init(&bf_q);
1398 status = ath_tgt_tx_form_aggr(sc, tid, &bf_q);
1400 if (asf_tailq_empty(&bf_q))
1403 bf = asf_tailq_first(&bf_q);
1404 bf_last = asf_tailq_last(&bf_q, ath_tx_bufhead_s);
1406 if (bf->bf_nframes == 1) {
1408 if(bf->bf_retries == 0)
1409 __stats(sc, txaggr_single);
1411 bf->bf_lastds = &(bf->bf_descarr[bf->bf_dmamap_info.nsegs -1]);
1412 bf->bf_lastds->ds_link = 0;
1415 for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
1416 ah->ah_clr11nAggr(ah, ds);
1418 ath_buf_set_rate(sc, bf);
1419 bf->bf_txq_add(sc, bf);
1424 bf_last->bf_next = NULL;
1425 bf_last->bf_lastds->ds_link = 0;
1426 bf_last->bf_ndelim = 0;
1429 ath_buf_set_rate(sc, bf);
1430 ah->ah_set11nAggrFirst(ah, bf->bf_desc, bf->bf_al,
1432 bf->bf_lastds = bf_last->bf_lastds;
1434 for (i = 0; i < bf_last->bf_dmamap_info.nsegs; i++)
1435 ah->ah_set11nAggrLast(ah, &bf_last->bf_descarr[i]);
1437 if (status == ATH_AGGR_8K_LIMITED) {
1442 bf->bf_txq_add(sc, bf);
1443 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
1444 status != ATH_TGT_AGGR_BAW_CLOSED);
1447 static u_int32_t ath_lookup_rate(struct ath_softc_tgt *sc,
1448 struct ath_node_target *an,
1449 struct ath_tx_buf *bf)
1452 u_int32_t max4msframelen, frame_length;
1453 u_int16_t aggr_limit, legacy=0;
1454 const HAL_RATE_TABLE *rt = sc->sc_currates;
1455 struct ieee80211_node_target *ieee_node = (struct ieee80211_node_target *)an;
1457 if (bf->bf_ismcast) {
1458 bf->bf_rcs[1].tries = bf->bf_rcs[2].tries = bf->bf_rcs[3].tries = 0;
1459 bf->bf_rcs[0].rix = 0xb;
1460 bf->bf_rcs[0].tries = ATH_TXMAXTRY - 1;
1461 bf->bf_rcs[0].flags = 0;
1463 ath_tgt_rate_findrate(sc, an, AH_TRUE, 0, ATH_TXMAXTRY-1, 4, 1,
1464 ATH_RC_PROBE_ALLOWED, bf->bf_rcs, &prate);
1467 max4msframelen = IEEE80211_AMPDU_LIMIT_MAX;
1469 for (i = 0; i < 4; i++) {
1470 if (bf->bf_rcs[i].tries) {
1471 frame_length = bf->bf_rcs[i].max4msframelen;
1473 if (rt->info[bf->bf_rcs[i].rix].phy != IEEE80211_T_HT) {
1478 max4msframelen = ATH_MIN(max4msframelen, frame_length);
1482 if (prate || legacy)
1485 if (sc->sc_ic.ic_enable_coex)
1486 aggr_limit = ATH_MIN((max4msframelen*3)/8, sc->sc_ic.ic_ampdu_limit);
1488 aggr_limit = ATH_MIN(max4msframelen, sc->sc_ic.ic_ampdu_limit);
1490 if (ieee_node->ni_maxampdu)
1491 aggr_limit = ATH_MIN(aggr_limit, ieee_node->ni_maxampdu);
1496 int ath_tgt_tx_form_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid,
1497 ath_tx_bufhead *bf_q)
1499 struct ath_tx_buf *bf_first ,*bf_prev = NULL;
1500 int nframes = 0, rl = 0;;
1501 struct ath_tx_desc *ds = NULL;
1502 struct ath_tx_buf *bf;
1503 struct ath_hal *ah = sc->sc_ah;
1504 u_int16_t aggr_limit = (64*1024 -1), al = 0, bpad = 0, al_delta;
1505 u_int16_t h_baw = tid->baw_size/2, prev_al = 0, prev_frames = 0;
1507 bf_first = asf_tailq_first(&tid->buf_q);
1510 bf = asf_tailq_first(&tid->buf_q);
1513 if (!BAW_WITHIN(tid->seq_start, tid->baw_size,
1514 SEQNO_FROM_BF_SEQNO(bf->bf_seqno))) {
1516 bf_first->bf_al= al;
1517 bf_first->bf_nframes = nframes;
1518 return ATH_TGT_AGGR_BAW_CLOSED;
1522 aggr_limit = ath_lookup_rate(sc, tid->an, bf);
1526 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_pktlen;
1528 if (nframes && (aggr_limit < (al + bpad + al_delta + prev_al))) {
1529 bf_first->bf_al= al;
1530 bf_first->bf_nframes = nframes;
1531 return ATH_TGT_AGGR_LIMITED;
1535 if ((nframes + prev_frames) >= ATH_MIN((h_baw), 17)) {
1537 if ((nframes + prev_frames) >= ATH_MIN((h_baw), 22)) {
1539 bf_first->bf_al= al;
1540 bf_first->bf_nframes = nframes;
1541 return ATH_TGT_AGGR_LIMITED;
1544 ath_tx_addto_baw(tid, bf);
1545 asf_tailq_remove(&tid->buf_q, bf, bf_list);
1546 asf_tailq_insert_tail(bf_q, bf, bf_list);
1551 adf_os_assert(bf->bf_comp == ath_tgt_tx_comp_aggr);
1553 al += bpad + al_delta;
1554 bf->bf_ndelim = ATH_AGGR_GET_NDELIM(bf->bf_pktlen);
1556 switch (bf->bf_keytype) {
1557 case HAL_KEY_TYPE_AES:
1558 bf->bf_ndelim += ATH_AGGR_ENCRYPTDELIM;
1560 case HAL_KEY_TYPE_WEP:
1561 case HAL_KEY_TYPE_TKIP:
1562 bf->bf_ndelim += 64;
1564 case HAL_KEY_TYPE_WAPI:
1565 bf->bf_ndelim += 12;
1571 bpad = PADBYTES(al_delta) + (bf->bf_ndelim << 2);
1574 bf_prev->bf_next = bf;
1575 bf_prev->bf_lastds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
1579 for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
1580 ah->ah_set11nAggrMiddle(ah, ds, bf->bf_ndelim);
1582 } while (!asf_tailq_empty(&tid->buf_q));
1584 bf_first->bf_al= al;
1585 bf_first->bf_nframes = nframes;
1587 return ATH_TGT_AGGR_DONE;
1590 void ath_tx_addto_baw(ath_atx_tid_t *tid, struct ath_tx_buf *bf)
1594 if (bf->bf_isretried) {
1598 index = ATH_BA_INDEX(tid->seq_start, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1599 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1601 TX_BUF_BITMAP_SET(tid->tx_buf_bitmap, cindex);
1603 if (index >= ((tid->baw_tail - tid->baw_head) & (ATH_TID_MAX_BUFS - 1))) {
1604 tid->baw_tail = cindex;
1605 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
1609 void ath_tgt_tx_comp_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1611 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1612 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1613 struct ath_tx_desc lastds;
1614 struct ath_tx_desc *ds = &lastds;
1615 struct ath_rc_series rcs[4];
1620 int nframes = bf->bf_nframes;
1621 struct ath_tx_buf *bf_next;
1622 ath_tx_bufhead bf_q;
1624 struct ath_tx_buf *bar = NULL;
1625 struct ath_txq *txq;
1629 if (tid->flag & TID_CLEANUP_INPROGRES) {
1630 ath_tx_comp_cleanup(sc, bf);
1634 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1635 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1637 if (ds->ds_txstat.ts_flags == HAL_TX_SW_FILTERED) {
1642 if (!bf->bf_isaggr) {
1643 ath_tx_comp_unaggr(sc, bf);
1647 __stats(sc, tx_compaggr);
1649 asf_tailq_init(&bf_q);
1651 seq_st = ATH_DS_BA_SEQ(ds);
1652 ba = ATH_DS_BA_BITMAP(ds);
1653 tx_ok = (ATH_DS_TX_STATUS(ds) == HAL_OK);
1655 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
1656 ath_tx_comp_aggr_error(sc, bf, tid);
1660 if (tx_ok && !ATH_DS_TX_BA(ds)) {
1661 __stats(sc, txaggr_babug);
1662 adf_os_print("BA Bug?\n");
1663 ath_tx_comp_aggr_error(sc, bf, tid);
1668 ba_index = ATH_BA_INDEX(seq_st, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1669 bf_next = bf->bf_next;
1671 if (tx_ok && ATH_BA_ISSET(ba, ba_index)) {
1672 __stats(sc, txaggr_compgood);
1673 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1674 ath_tx_status_update_aggr(sc, bf, ds, rcs, 1);
1675 ath_tx_freebuf(sc, bf);
1677 ath_tx_retry_subframe(sc, bf, &bf_q, &bar);
1683 ath_update_aggr_stats(sc, ds, nframes, nbad);
1684 ath_rate_tx_complete(sc, an, ds, rcs, nframes, nbad);
1687 ath_bar_tx(sc, tid, bar);
1690 if (!asf_tailq_empty(&bf_q)) {
1691 __stats(sc, txaggr_prepends);
1692 TAILQ_INSERTQ_HEAD(&tid->buf_q, &bf_q, bf_list);
1693 ath_tgt_tx_enqueue(txq, tid);
1698 ath_tx_comp_aggr_error(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
1703 struct ath_tx_desc lastds;
1704 struct ath_tx_desc *ds = &lastds;
1705 struct ath_rc_series rcs[4];
1706 struct ath_tx_buf *bar = NULL;
1707 struct ath_tx_buf *bf_next;
1708 int nframes = bf->bf_nframes;
1709 ath_tx_bufhead bf_q;
1710 struct ath_txq *txq;
1712 asf_tailq_init(&bf_q);
1715 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1716 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1719 bf_next = bf->bf_next;
1720 ath_tx_retry_subframe(sc, bf, &bf_q, &bar);
1724 ath_update_aggr_stats(sc, ds, nframes, nframes);
1725 ath_rate_tx_complete(sc, tid->an, ds, rcs, nframes, nframes);
1728 ath_bar_tx(sc, tid, bar);
1731 if (!asf_tailq_empty(&bf_q)) {
1732 __stats(sc, txaggr_prepends);
1733 TAILQ_INSERTQ_HEAD(&tid->buf_q, &bf_q, bf_list);
1734 ath_tgt_tx_enqueue(txq, tid);
1739 ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1742 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1743 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1744 struct ath_tx_desc lastds;
1745 struct ath_tx_desc *ds = &lastds;
1746 struct ath_rc_series rcs[4];
1751 int nframes = bf->bf_nframes;
1752 struct ath_tx_buf *bf_next;
1755 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1756 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1758 seq_st = ATH_DS_BA_SEQ(ds);
1759 ba = ATH_DS_BA_BITMAP(ds);
1760 tx_ok = (ATH_DS_TX_STATUS(ds) == HAL_OK);
1762 if (!bf->bf_isaggr) {
1763 ath_update_stats(sc, bf);
1765 __stats(sc, tx_compunaggr);
1767 ath_tx_status_update(sc, bf);
1769 ath_tx_freebuf(sc, bf);
1771 if (tid->flag & TID_CLEANUP_INPROGRES) {
1772 owl_tgt_tid_cleanup(sc, tid);
1780 ba_index = ATH_BA_INDEX(seq_st, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1781 bf_next = bf->bf_next;
1783 ath_tx_status_update_aggr(sc, bf, ds, rcs, 0);
1785 ath_tx_freebuf(sc, bf);
1789 tid->flag &= ~TID_CLEANUP_INPROGRES;
1790 ath_aggr_resume_tid(sc, tid);
1797 ath_update_aggr_stats(sc, ds, nframes, nbad);
1798 ath_rate_tx_complete(sc, an, ds, rcs, nframes, nbad);
1802 ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
1803 ath_tx_bufhead *bf_q, struct ath_tx_buf **bar)
1806 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1807 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1808 struct ath_tx_desc *ds = NULL;
1809 struct ath_hal *ah = sc->sc_ah;
1812 __stats(sc, txaggr_compretries);
1814 for(ds = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; ds++, i++) {
1815 ah->ah_clr11nAggr(ah, ds);
1816 ah->ah_set11nBurstDuration(ah, ds, 0);
1817 ah->ah_set11nVirtualMoreFrag(ah, ds, 0);
1820 if (bf->bf_retries >= OWLMAX_RETRIES) {
1821 __stats(sc, txaggr_xretries);
1822 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1823 ath_tx_status_update_aggr(sc, bf, bf->bf_lastds, NULL, 0);
1828 ath_tx_freebuf(sc, bf);
1833 __stats(sc, txaggr_errlast);
1834 bf = ath_buf_toggle(sc, bf, 1);
1836 bf->bf_lastds = &(bf->bf_descarr[bf->bf_dmamap_info.nsegs - 1]);
1838 ath_tx_set_retry(sc, bf);
1839 asf_tailq_insert_tail(bf_q, bf, bf_list);
1843 ath_update_aggr_stats(struct ath_softc_tgt *sc,
1844 struct ath_tx_desc *ds, int nframes,
1848 u_int8_t status = ATH_DS_TX_STATUS(ds);
1849 u_int8_t txflags = ATH_DS_TX_FLAGS(ds);
1851 __statsn(sc, txaggr_longretries, ds->ds_txstat.ts_longretry);
1852 __statsn(sc, txaggr_shortretries, ds->ds_txstat.ts_shortretry);
1854 if (txflags & HAL_TX_DESC_CFG_ERR)
1855 __stats(sc, txaggr_desc_cfgerr);
1857 if (txflags & HAL_TX_DATA_UNDERRUN)
1858 __stats(sc, txaggr_data_urun);
1860 if (txflags & HAL_TX_DELIM_UNDERRUN)
1861 __stats(sc, txaggr_delim_urun);
1867 if (status & HAL_TXERR_XRETRY)
1868 __stats(sc, txaggr_compxretry);
1870 if (status & HAL_TXERR_FILT)
1871 __stats(sc, txaggr_filtered);
1873 if (status & HAL_TXERR_FIFO)
1874 __stats(sc, txaggr_fifo);
1876 if (status & HAL_TXERR_XTXOP)
1877 __stats(sc, txaggr_xtxop);
1879 if (status & HAL_TXERR_TIMER_EXPIRED)
1880 __stats(sc, txaggr_timer_exp);
1884 ath_tx_comp_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1886 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1887 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1888 struct ath_tx_desc *ds = bf->bf_lastds;
1890 ath_update_stats(sc, bf);
1891 ath_rate_tx_complete(sc, an, ds, bf->bf_rcs, 1, 0);
1893 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
1894 ath_tx_retry_unaggr(sc, bf);
1897 __stats(sc, tx_compunaggr);
1899 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1900 ath_tx_status_update(sc, bf);
1901 ath_tx_freebuf(sc, bf);
1905 ath_tx_retry_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1907 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1908 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1909 struct ath_txq *txq;
1913 if (bf->bf_retries >= OWLMAX_RETRIES) {
1914 __stats(sc, txunaggr_xretry);
1915 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1916 ath_tx_status_update(sc, bf);
1917 ath_bar_tx(sc, tid, bf);
1921 __stats(sc, txunaggr_compretries);
1922 if (!bf->bf_lastds->ds_link) {
1923 __stats(sc, txunaggr_errlast);
1924 bf = ath_buf_toggle(sc, bf, 1);
1927 ath_tx_set_retry(sc, bf);
1928 asf_tailq_insert_head(&tid->buf_q, bf, bf_list);
1929 ath_tgt_tx_enqueue(txq, tid);
1933 ath_tx_update_baw(ath_atx_tid_t *tid, int seqno)
1938 index = ATH_BA_INDEX(tid->seq_start, seqno);
1939 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1941 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, cindex);
1943 while (tid->baw_head != tid->baw_tail &&
1944 (!TX_BUF_BITMAP_IS_SET(tid->tx_buf_bitmap, tid->baw_head))) {
1945 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1946 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
1950 static void ath_tx_set_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1952 struct ieee80211_frame *wh;
1954 __stats(sc, txaggr_retries);
1956 bf->bf_isretried = 1;
1958 wh = ATH_SKB_2_WH(bf->bf_skb);
1959 wh->i_fc[1] |= IEEE80211_FC1_RETRY;
1962 void ath_tgt_tx_cleanup(struct ath_softc_tgt *sc, struct ath_node_target *an,
1963 ath_atx_tid_t *tid, a_uint8_t discard_all)
1965 struct ath_tx_buf *bf;
1966 struct ath_tx_buf *bf_next;
1967 struct ath_txq *txq;
1969 txq = TID_TO_ACTXQ(tid->tidno);
1971 bf = asf_tailq_first(&tid->buf_q);
1974 if (discard_all || bf->bf_isretried) {
1975 bf_next = asf_tailq_next(bf, bf_list);
1976 TAILQ_DEQ(&tid->buf_q, bf, bf_list);
1977 if (bf->bf_isretried)
1978 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1979 ath_tx_freebuf(sc, bf);
1983 bf->bf_comp = ath_tgt_tx_comp_normal;
1984 bf = asf_tailq_next(bf, bf_list);
1987 ath_aggr_pause_tid(sc, tid);
1989 while (tid->baw_head != tid->baw_tail) {
1990 if (TX_BUF_BITMAP_IS_SET(tid->tx_buf_bitmap, tid->baw_head)) {
1992 tid->flag |= TID_CLEANUP_INPROGRES;
1993 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, tid->baw_head);
1995 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
1996 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1999 if (!(tid->flag & TID_CLEANUP_INPROGRES)) {
2000 ath_aggr_resume_tid(sc, tid);
2004 /******************/
2005 /* BAR Management */
2006 /******************/
2008 static void ath_tgt_delba_send(struct ath_softc_tgt *sc,
2009 struct ieee80211_node_target *ni,
2010 a_uint8_t tidno, a_uint8_t initiator,
2011 a_uint16_t reasoncode)
2013 struct ath_node_target *an = ATH_NODE_TARGET(ni);
2014 ath_atx_tid_t *tid = ATH_AN_2_TID(an, tidno);
2015 struct wmi_data_delba wmi_delba;
2017 tid->flag &= ~TID_AGGR_ENABLED;
2019 ath_tgt_tx_cleanup(sc, an, tid, 1);
2021 wmi_delba.ni_nodeindex = ni->ni_nodeindex;
2022 wmi_delba.tidno = tid->tidno;
2023 wmi_delba.initiator = 1;
2024 wmi_delba.reasoncode = IEEE80211_REASON_UNSPECIFIED;
2026 __stats(sc, txbar_xretry);
2027 wmi_event(sc->tgt_wmi_handle,
2033 static void ath_bar_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
2035 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
2036 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
2038 if (bf->bf_retries >= OWLMAX_BAR_RETRIES) {
2039 ath_tgt_delba_send(sc, bf->bf_node, tid->tidno, 1,
2040 IEEE80211_REASON_UNSPECIFIED);
2041 ath_tgt_tid_drain(sc, tid);
2044 ath_buf_comp(sc, bf);
2048 __stats(sc, txbar_compretries);
2050 if (!bf->bf_lastds->ds_link) {
2051 __stats(sc, txbar_errlast);
2052 bf = ath_buf_toggle(sc, bf, 1);
2055 bf->bf_lastds->ds_link = 0;
2057 ath_tx_set_retry(sc, bf);
2058 ath_tgt_txq_add_ucast(sc, bf);
2061 static void ath_bar_tx_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
2063 struct ath_tx_desc *ds = bf->bf_lastds;
2064 struct ath_node_target *an;
2066 struct ath_txq *txq;
2068 an = (struct ath_node_target *)bf->bf_node;
2069 tid = &an->tid[bf->bf_tidno];
2070 txq = TID_TO_ACTXQ(tid->tidno);
2072 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
2073 ath_bar_retry(sc, bf);
2077 ath_aggr_resume_tid(sc, tid);
2080 ath_buf_comp(sc, bf);
2083 static void ath_bar_tx(struct ath_softc_tgt *sc,
2084 ath_atx_tid_t *tid, struct ath_tx_buf *bf)
2087 struct ieee80211_frame_bar *bar;
2089 struct ath_tx_desc *ds, *ds0;
2090 struct ath_hal *ah = sc->sc_ah;
2091 HAL_11N_RATE_SERIES series[4];
2093 adf_nbuf_queue_t skbhead;
2097 __stats(sc, tx_bars);
2099 adf_os_mem_set(&series, 0, sizeof(series));
2101 ath_aggr_pause_tid(sc, tid);
2103 skb = adf_nbuf_queue_remove(&bf->bf_skbhead);
2104 adf_nbuf_peek_header(skb, &anbdata, &anblen);
2105 adf_nbuf_trim_tail(skb, anblen);
2106 bar = (struct ieee80211_frame_bar *) anbdata;
2110 ath_dma_unmap(sc, bf);
2111 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
2113 bar->i_fc[1] = IEEE80211_FC1_DIR_NODS;
2114 bar->i_fc[0] = IEEE80211_FC0_VERSION_0 |
2115 IEEE80211_FC0_TYPE_CTL |
2116 IEEE80211_FC0_SUBTYPE_BAR;
2117 bar->i_ctl = tid->tidno << IEEE80211_BAR_CTL_TID_S |
2118 IEEE80211_BAR_CTL_COMBA;
2119 bar->i_seq = adf_os_cpu_to_le16(tid->seq_start << IEEE80211_SEQ_SEQ_SHIFT);
2121 bf->bf_seqno = tid->seq_start << IEEE80211_SEQ_SEQ_SHIFT;
2123 adf_nbuf_put_tail(skb, sizeof(struct ieee80211_frame_bar));
2125 bf->bf_comp = ath_bar_tx_comp;
2126 bf->bf_tidno = tid->tidno;
2127 bf->bf_node = &tid->an->ni;
2128 ath_dma_map(sc, bf);
2129 adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info);
2132 ah->ah_setupTxDesc(ah, ds
2133 , adf_nbuf_len(skb) + IEEE80211_CRC_LEN
2135 , HAL_PKT_TYPE_NORMAL
2142 | HAL_TXDESC_CLRDMASK
2144 , ATH_COMP_PROC_NO_COMP_NO_CCS);
2146 skbhead = bf->bf_skbhead;
2150 for (ds0 = ds, i=0; i < bf->bf_dmamap_info.nsegs; ds0++, i++) {
2151 ah->ah_clr11nAggr(ah, ds0);
2154 ath_filltxdesc(sc, bf);
2156 for (i = 0 ; i < 4; i++) {
2157 series[i].Tries = ATH_TXMAXTRY;
2158 series[i].Rate = min_rate;
2159 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
2162 ah->ah_set11nRateScenario(ah, bf->bf_desc, 0, 0, 0, series, 4, 4);
2163 ath_tgt_txq_add_ucast(sc, bf);