2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <adf_os_types.h>
37 #include <adf_os_dma.h>
38 #include <adf_os_timer.h>
39 #include <adf_os_lock.h>
40 #include <adf_os_io.h>
41 #include <adf_os_mem.h>
42 #include <adf_os_util.h>
43 #include <adf_os_stdtypes.h>
44 #include <adf_os_defer.h>
45 #include <adf_os_atomic.h>
48 #include <adf_net_wcmd.h>
50 #include "if_ethersubr.h"
53 #ifdef USE_HEADERLEN_RESV
57 #include <ieee80211_var.h>
58 #include "if_athrate.h"
59 #include "if_athvar.h"
61 #include "if_ath_pci.h"
63 #define ath_tgt_free_skb adf_nbuf_free
65 #define OFDM_PLCP_BITS 22
66 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
67 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
73 #define HT_LTF(_ns) (4 * (_ns))
74 #define SYMBOL_TIME(_ns) ((_ns) << 2) // ns * 4 us
75 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) // ns * 3.6 us
77 static a_uint16_t bits_per_symbol[][2] = {
79 { 26, 54 }, // 0: BPSK
80 { 52, 108 }, // 1: QPSK 1/2
81 { 78, 162 }, // 2: QPSK 3/4
82 { 104, 216 }, // 3: 16-QAM 1/2
83 { 156, 324 }, // 4: 16-QAM 3/4
84 { 208, 432 }, // 5: 64-QAM 2/3
85 { 234, 486 }, // 6: 64-QAM 3/4
86 { 260, 540 }, // 7: 64-QAM 5/6
87 { 52, 108 }, // 8: BPSK
88 { 104, 216 }, // 9: QPSK 1/2
89 { 156, 324 }, // 10: QPSK 3/4
90 { 208, 432 }, // 11: 16-QAM 1/2
91 { 312, 648 }, // 12: 16-QAM 3/4
92 { 416, 864 }, // 13: 64-QAM 2/3
93 { 468, 972 }, // 14: 64-QAM 3/4
94 { 520, 1080 }, // 15: 64-QAM 5/6
97 void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,
98 owl_txq_state_t txqstate);
99 static void ath_tgt_txqaddbuf(struct ath_softc_tgt *sc, struct ath_txq *txq,
100 struct ath_buf *bf, struct ath_desc *lastds);
101 void ath_rate_findrate_11n_Hardcoded(struct ath_softc_tgt *sc,
102 struct ath_rc_series series[]);
103 void ath_buf_set_rate_Hardcoded(struct ath_softc_tgt *sc,
104 struct ath_tx_buf *bf) ;
105 static a_int32_t ath_tgt_txbuf_setup(struct ath_softc_tgt *sc,
106 struct ath_tx_buf *bf, ath_data_hdr_t *dh);
107 static void ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
108 static void ath_tx_uc_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
109 static void ath_update_stats(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
110 void adf_print_buf(adf_nbuf_t buf);
111 static void ath_tgt_tx_enqueue(struct ath_txq *txq, struct ath_atx_tid *tid);
113 void ath_tgt_tx_comp_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
114 struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb);
116 void ath_tgt_tx_send_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
118 static void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
119 static void ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
121 extern a_int32_t ath_chainmask_sel_logic(void *);
122 static a_int32_t ath_get_pktlen(struct ath_tx_buf *bf, a_int32_t hdrlen);
123 static void ath_tgt_txq_schedule(struct ath_softc_tgt *sc, struct ath_txq *txq);
125 typedef void (*ath_ft_set_atype_t)(struct ath_softc_tgt *sc, struct ath_buf *bf);
128 ath_tx_set_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
131 ath_bar_tx(struct ath_softc_tgt *sc, ath_atx_tid_t *tid, struct ath_tx_buf *bf);
133 ath_tx_update_baw(ath_atx_tid_t *tid, int seqno);
135 ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
136 ath_bufhead *bf_q, struct ath_tx_buf **bar);
139 ath_tx_comp_aggr_error(struct ath_softc_tgt *sc, struct ath_tx_buf *bf, ath_atx_tid_t *tid);
141 void ath_tx_addto_baw(ath_atx_tid_t *tid, struct ath_tx_buf *bf);
142 static inline void ath_tx_retry_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
143 static void ath_tx_comp_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
144 static void ath_update_aggr_stats(struct ath_softc_tgt *sc, struct ath_tx_desc *ds,
145 int nframes, int nbad);
146 static inline void ath_aggr_resume_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid);
147 static void ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf);
149 int ath_tgt_tx_add_to_aggr(struct ath_softc_tgt *sc,
150 struct ath_buf *bf,int datatype,
151 ath_atx_tid_t *tid, int is_burst);
153 struct ieee80211_frame *ATH_SKB_2_WH(adf_nbuf_t skb)
158 adf_nbuf_peek_header(skb, &anbdata, &anblen);
160 return((struct ieee80211_frame *)anbdata);
163 #undef adf_os_cpu_to_le16
165 static a_uint16_t adf_os_cpu_to_le16(a_uint16_t x)
167 return ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8));
171 ath_aggr_resume_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
175 txq = TID_TO_ACTXQ(tid->tidno);
178 if (asf_tailq_empty(&tid->buf_q))
181 ath_tgt_tx_enqueue(txq, tid);
182 ath_tgt_txq_schedule(sc, txq);
186 ath_aggr_pause_tid(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
191 static a_uint32_t ath_pkt_duration(struct ath_softc_tgt *sc,
192 a_uint8_t rix, struct ath_tx_buf *bf,
193 a_int32_t width, a_int32_t half_gi)
195 const HAL_RATE_TABLE *rt = sc->sc_currates;
196 a_uint32_t nbits, nsymbits, duration, nsymbols;
201 pktlen = bf->bf_isaggr ? bf->bf_al : bf->bf_pktlen;
202 rc = rt->info[rix].rateCode;
205 return ath_hal_computetxtime(sc->sc_ah, rt, pktlen, rix,
208 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
209 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
210 nsymbols = (nbits + nsymbits - 1) / nsymbits;
213 duration = SYMBOL_TIME(nsymbols);
215 duration = SYMBOL_TIME_HALFGI(nsymbols);
217 streams = HT_RC_2_STREAMS(rc);
218 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
223 static void ath_dma_map(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
225 adf_nbuf_t skb = bf->bf_skb;
227 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
228 adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, skb, ADF_OS_DMA_TO_DEVICE);
231 static void ath_dma_unmap(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
233 adf_nbuf_t skb = bf->bf_skb;
235 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
236 adf_nbuf_unmap( sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE);
239 static void ath_filltxdesc(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
241 struct ath_tx_desc *ds0, *ds = bf->bf_desc;
245 adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info);
247 for (i = 0; i < bf->bf_dmamap_info.nsegs; i++, ds++) {
249 ds->ds_data = bf->bf_dmamap_info.dma_segs[i].paddr;
251 if (i == (bf->bf_dmamap_info.nsegs - 1)) {
255 ds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, i+1);
257 ath_hal_filltxdesc(sc->sc_ah, ds
258 , bf->bf_dmamap_info.dma_segs[i].len
260 , i == (bf->bf_dmamap_info.nsegs - 1)
265 static void ath_tx_tgt_setds(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
267 struct ath_desc *ds = bf->bf_desc;
269 switch (bf->bf_protmode) {
270 case IEEE80211_PROT_RTSCTS:
271 bf->bf_flags |= HAL_TXDESC_RTSENA;
273 case IEEE80211_PROT_CTSONLY:
274 bf->bf_flags |= HAL_TXDESC_CTSENA;
280 ath_hal_set11n_txdesc(sc->sc_ah, ds
286 , bf->bf_flags | HAL_TXDESC_INTREQ);
288 ath_filltxdesc(sc, bf);
291 static struct ath_tx_buf *ath_buf_toggle(struct ath_softc_tgt *sc,
292 struct ath_tx_buf *bf,
295 struct ath_tx_buf *tmp = NULL;
296 adf_nbuf_t buf = NULL;
298 adf_os_assert(sc->sc_txbuf_held != NULL);
300 tmp = sc->sc_txbuf_held;
303 ath_dma_unmap(sc, bf);
304 adf_nbuf_queue_init(&tmp->bf_skbhead);
305 buf = adf_nbuf_queue_remove(&bf->bf_skbhead);
307 adf_nbuf_queue_add(&tmp->bf_skbhead, buf);
309 adf_os_assert(adf_nbuf_queue_len(&bf->bf_skbhead) == 0);
311 tmp->bf_next = bf->bf_next;
312 tmp->bf_endpt = bf->bf_endpt;
313 tmp->bf_tidno = bf->bf_tidno;
314 tmp->bf_skb = bf->bf_skb;
315 tmp->bf_node = bf->bf_node;
316 tmp->bf_isaggr = bf->bf_isaggr;
317 tmp->bf_flags = bf->bf_flags;
318 tmp->bf_state = bf->bf_state;
319 tmp->bf_retries = bf->bf_retries;
320 tmp->bf_comp = bf->bf_comp;
321 tmp->bf_nframes = bf->bf_nframes;
322 tmp->bf_cookie = bf->bf_cookie;
334 ath_dma_map(sc, tmp);
335 ath_tx_tgt_setds(sc, tmp);
338 sc->sc_txbuf_held = bf;
343 static void ath_tgt_skb_free(struct ath_softc_tgt *sc,
344 adf_nbuf_queue_t *head,
345 HTC_ENDPOINT_ID endpt)
349 while (adf_nbuf_queue_len(head) != 0) {
350 tskb = adf_nbuf_queue_remove(head);
351 ath_free_tx_skb(sc->tgt_htc_handle,endpt,tskb);
355 static void ath_buf_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
357 ath_dma_unmap(sc, bf);
358 ath_tgt_skb_free(sc, &bf->bf_skbhead,bf->bf_endpt);
361 bf = ath_buf_toggle(sc, bf, 0);
363 asf_tailq_insert_tail(&sc->sc_txbuf, bf, bf_list);
367 static void ath_buf_set_rate(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
369 struct ath_hal *ah = sc->sc_ah;
370 const HAL_RATE_TABLE *rt;
371 struct ath_desc *ds = bf->bf_desc;
372 HAL_11N_RATE_SERIES series[4];
374 a_uint8_t rix, cix, rtsctsrate;
375 a_uint32_t ctsduration = 0;
376 a_int32_t prot_mode = AH_FALSE;
378 rt = sc->sc_currates;
379 rix = bf->bf_rcs[0].rix;
380 flags = (bf->bf_flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA));
381 cix = rt->info[sc->sc_protrix].controlRate;
383 if (bf->bf_protmode != IEEE80211_PROT_NONE &&
384 (rt->info[rix].phy == IEEE80211_T_OFDM ||
385 rt->info[rix].phy == IEEE80211_T_HT) &&
386 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) {
387 cix = rt->info[sc->sc_protrix].controlRate;
390 if (ath_hal_htsupported(ah) && (!bf->bf_ismcast))
391 flags = HAL_TXDESC_RTSENA;
394 if (bf->bf_rcs[i].tries) {
395 cix = rt->info[bf->bf_rcs[i].rix].controlRate;
402 adf_os_mem_set(series, 0, sizeof(HAL_11N_RATE_SERIES) * 4);
404 for (i = 0; i < 4; i++) {
405 if (!bf->bf_rcs[i].tries)
408 rix = bf->bf_rcs[i].rix;
410 series[i].Rate = rt->info[rix].rateCode |
411 (bf->bf_shpream ? rt->info[rix].shortPreamble : 0);
413 series[i].Tries = bf->bf_rcs[i].tries;
415 series[i].RateFlags = ((bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
416 HAL_RATESERIES_RTS_CTS : 0 ) |
417 ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
418 HAL_RATESERIES_2040 : 0 ) |
419 ((bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG) ?
420 HAL_RATESERIES_HALFGI : 0 ) |
421 ((bf->bf_rcs[i].flags & ATH_RC_TX_STBC_FLAG) ?
422 HAL_RATESERIES_STBC: 0);
424 series[i].RateFlags = ((bf->bf_rcs[i].flags & ATH_RC_RTSCTS_FLAG) ?
425 HAL_RATESERIES_RTS_CTS : 0 ) |
426 ((bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) ?
427 HAL_RATESERIES_2040 : 0 ) |
428 ((bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG) ?
429 HAL_RATESERIES_HALFGI : 0 );
431 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
432 (bf->bf_rcs[i].flags & ATH_RC_CW40_FLAG) != 0,
433 (bf->bf_rcs[i].flags & ATH_RC_HT40_SGI_FLAG));
435 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
438 series[i].RateFlags |= HAL_RATESERIES_RTS_CTS;
440 if (bf->bf_rcs[i].flags & ATH_RC_DS_FLAG)
441 series[i].RateFlags |= HAL_RATESERIES_RTS_CTS;
444 rtsctsrate = rt->info[cix].rateCode |
445 (bf->bf_shpream ? rt->info[cix].shortPreamble : 0);
447 ath_hal_set11n_ratescenario(ah, ds, 1,
448 rtsctsrate, ctsduration,
453 static void ath_tgt_rate_findrate(struct ath_softc_tgt *sc,
454 struct ath_node_target *an,
455 a_int32_t shortPreamble,
461 struct ath_rc_series series[],
464 ath_rate_findrate(sc, an, 1, frameLen, 10, 4, 1,
465 ATH_RC_PROBE_ALLOWED, series, isProbe);
468 static void owl_tgt_tid_init(struct ath_atx_tid *tid)
472 tid->seq_start = tid->seq_next = 0;
473 tid->baw_size = WME_MAX_BA;
474 tid->baw_head = tid->baw_tail = 0;
477 tid->sched = AH_FALSE;
479 asf_tailq_init(&tid->buf_q);
481 for (i = 0; i < ATH_TID_MAX_BUFS; i++) {
482 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, i);
486 static void owl_tgt_tid_cleanup(struct ath_softc_tgt *sc,
487 struct ath_atx_tid *tid)
494 tid->flag &= ~TID_CLEANUP_INPROGRES;
496 if (tid->flag & TID_REINITIALIZE) {
497 adf_os_print("TID REINIT DONE for tid %p\n", tid);
498 tid->flag &= ~TID_REINITIALIZE;
499 owl_tgt_tid_init(tid);
501 ath_aggr_resume_tid(sc, tid);
505 void owl_tgt_node_init(struct ath_node_target * an)
507 struct ath_atx_tid *tid;
510 for (tidno = 0, tid = &an->tid[tidno]; tidno < WME_NUM_TID;tidno++, tid++) {
514 if ( tid->flag & TID_CLEANUP_INPROGRES ) {
515 tid->flag |= TID_REINITIALIZE;
516 adf_os_print("tid[%p]->incomp is not 0: %d\n",
519 owl_tgt_tid_init(tid);
524 void ath_tx_status_clear(struct ath_softc_tgt *sc)
528 for (i = 0; i < 2; i++) {
529 sc->tx_status[i].cnt = 0;
533 static WMI_TXSTATUS_EVENT *ath_tx_status_get(struct ath_softc_tgt *sc)
535 WMI_TXSTATUS_EVENT *txs = NULL;
538 for (i = 0; i < 2; i++) {
539 if (sc->tx_status[i].cnt < HTC_MAX_TX_STATUS) {
540 txs = &sc->tx_status[i];
548 void ath_tx_status_update(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
550 struct ath_tx_desc *ds = bf->bf_lastds;
551 WMI_TXSTATUS_EVENT *txs;
553 if (sc->sc_tx_draining)
556 txs = ath_tx_status_get(sc);
560 txs->txstatus[txs->cnt].cookie = bf->bf_cookie;
561 txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID);
563 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
564 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_FILT;
566 if (!(ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) &&
567 !(ds->ds_txstat.ts_status & HAL_TXERR_FIFO) &&
568 !(ds->ds_txstat.ts_status & HAL_TXERR_TIMER_EXPIRED) &&
569 !(ds->ds_txstat.ts_status & HAL_TXERR_FILT))
570 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_ACK;
572 ath_tx_status_update_rate(sc, bf->bf_rcs, ds->ds_txstat.ts_rate, txs);
577 void ath_tx_status_update_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
578 struct ath_tx_desc *ds, struct ath_rc_series rcs[],
581 WMI_TXSTATUS_EVENT *txs;
583 if (sc->sc_tx_draining)
586 txs = ath_tx_status_get(sc);
590 txs->txstatus[txs->cnt].cookie = bf->bf_cookie;
591 txs->txstatus[txs->cnt].ts_rate = SM(bf->bf_endpt, ATH9K_HTC_TXSTAT_EPID);
594 txs->txstatus[txs->cnt].ts_flags |= ATH9K_HTC_TXSTAT_ACK;
597 ath_tx_status_update_rate(sc, rcs, ds->ds_txstat.ts_rate, txs);
602 void ath_tx_status_send(struct ath_softc_tgt *sc)
606 if (sc->sc_tx_draining)
609 for (i = 0; i < 2; i++) {
610 if (sc->tx_status[i].cnt) {
611 wmi_event(sc->tgt_wmi_handle, WMI_TXSTATUS_EVENTID,
612 &sc->tx_status[i], sizeof(WMI_TXSTATUS_EVENT));
613 /* FIXME: Handle failures. */
614 sc->tx_status[i].cnt = 0;
619 static void owltgt_tx_process_cabq(struct ath_softc_tgt *sc, struct ath_txq *txq)
621 ath_hal_intrset(sc->sc_ah, sc->sc_imask & ~HAL_INT_SWBA);
622 owltgt_tx_processq(sc, txq, OWL_TXQ_ACTIVE);
623 ath_hal_intrset(sc->sc_ah, sc->sc_imask);
626 void owl_tgt_tx_tasklet(TQUEUE_ARG data)
628 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
632 ath_tx_status_clear(sc);
634 for (i = 0; i < (HAL_NUM_TX_QUEUES - 6); i++) {
635 txq = ATH_TXQ(sc, i);
637 if (ATH_TXQ_SETUP(sc, i)) {
638 if (txq == sc->sc_cabq)
639 owltgt_tx_process_cabq(sc, txq);
641 owltgt_tx_processq(sc, txq, OWL_TXQ_ACTIVE);
645 ath_tx_status_send(sc);
648 void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq,
649 owl_txq_state_t txqstate)
651 struct ath_tx_buf *bf;
652 struct ath_tx_desc *ds;
656 if (asf_tailq_empty(&txq->axq_q)) {
657 txq->axq_link = NULL;
658 txq->axq_linkbuf = NULL;
662 bf = asf_tailq_first(&txq->axq_q);
665 status = ath_hal_txprocdesc(sc->sc_ah, ds);
667 if (status == HAL_EINPROGRESS) {
668 if (txqstate == OWL_TXQ_ACTIVE)
670 else if (txqstate == OWL_TXQ_STOPPED) {
671 __stats(sc, tx_stopfiltered);
672 ds->ds_txstat.ts_flags = 0;
673 ds->ds_txstat.ts_status = HAL_OK;
675 ds->ds_txstat.ts_flags = HAL_TX_SW_FILTERED;
679 ATH_TXQ_REMOVE_HEAD(txq, bf, bf_list);
680 if ((asf_tailq_empty(&txq->axq_q))) {
681 __stats(sc, tx_qnull);
682 txq->axq_link = NULL;
683 txq->axq_linkbuf = NULL;
689 ath_tx_status_update(sc, bf);
690 ath_buf_comp(sc, bf);
693 if (txqstate == OWL_TXQ_ACTIVE) {
694 ath_tgt_txq_schedule(sc, txq);
699 static struct ieee80211_frame* ATH_SKB2_WH(adf_nbuf_t skb)
704 adf_nbuf_peek_header(skb, &anbdata, &anblen);
705 return((struct ieee80211_frame *)anbdata);
709 ath_tgt_tid_drain(struct ath_softc_tgt *sc, struct ath_atx_tid *tid)
711 struct ath_tx_buf *bf;
713 while (!asf_tailq_empty(&tid->buf_q)) {
714 TAILQ_DEQ(&tid->buf_q, bf, bf_list);
715 ath_tx_freebuf(sc, bf);
718 tid->seq_next = tid->seq_start;
719 tid->baw_tail = tid->baw_head;
722 static void ath_tgt_tx_comp_normal(struct ath_softc_tgt *sc,
723 struct ath_tx_buf *bf)
725 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
726 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
728 if (tid->flag & TID_CLEANUP_INPROGRES) {
729 owl_tgt_tid_cleanup(sc, tid);
733 ath_tx_uc_comp(sc, bf);
736 ath_tx_freebuf(sc, bf);
739 static struct ieee80211_node_target * ath_tgt_find_node(struct ath_softc_tgt *sc,
740 a_int32_t node_index)
742 struct ath_node_target *an;
743 struct ieee80211_node_target *ni;
745 if (node_index > TARGET_NODE_MAX)
748 an = &sc->sc_sta[node_index];
752 if (ni->ni_vap == NULL) {
761 static struct ath_tx_buf* ath_tx_buf_alloc(struct ath_softc_tgt *sc)
763 struct ath_tx_buf *bf = NULL;
765 bf = asf_tailq_first(&sc->sc_txbuf);
767 adf_os_mem_set(&bf->bf_state, 0, sizeof(struct ath_buf_state));
768 asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
776 struct ath_tx_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc,
777 adf_nbuf_t skb, ath_data_hdr_t *dh)
779 struct ath_tx_buf *bf;
780 struct ieee80211_node_target *ni;
781 struct ath_atx_tid *tid;
783 ni = ath_tgt_find_node(sc, dh->ni_index);
787 tid = ATH_AN_2_TID(ATH_NODE_TARGET(ni), dh->tidno);
788 if (tid->flag & TID_REINITIALIZE) {
789 adf_os_print("drop frame due to TID reinit\n");
793 bf = ath_tx_buf_alloc(sc);
795 __stats(sc, tx_nobufs);
799 bf->bf_tidno = dh->tidno;
800 bf->bf_txq = TID_TO_ACTXQ(bf->bf_tidno);
801 bf->bf_keytype = dh->keytype;
802 bf->bf_keyix = dh->keyix;
803 bf->bf_protmode = dh->flags & (IEEE80211_PROT_RTSCTS | IEEE80211_PROT_CTSONLY);
806 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
807 skb = adf_nbuf_queue_first(&(bf->bf_skbhead));
809 if (adf_nbuf_queue_len(&(bf->bf_skbhead)) == 0) {
810 __stats(sc, tx_noskbs);
818 ath_tgt_txbuf_setup(sc, bf, dh);
820 ath_tx_tgt_setds(sc, bf);
825 static void ath_tgt_tx_seqno_normal(struct ath_tx_buf *bf)
827 struct ieee80211_node_target *ni = bf->bf_node;
828 struct ath_node_target *an = ATH_NODE_TARGET(ni);
829 struct ieee80211_frame *wh = ATH_SKB_2_WH(bf->bf_skb);
830 struct ath_atx_tid *tid = ATH_AN_2_TID(an, bf->bf_tidno);
832 u_int8_t fragno = (wh->i_seq[0] & 0xf);
834 INCR(ni->ni_txseqmgmt, IEEE80211_SEQ_MAX);
836 bf->bf_seqno = (tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
838 *(u_int16_t *)wh->i_seq = adf_os_cpu_to_le16(bf->bf_seqno);
839 wh->i_seq[0] |= fragno;
841 if (!(wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG))
842 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
845 static a_int32_t ath_key_setup(struct ieee80211_node_target *ni,
846 struct ath_tx_buf *bf)
848 struct ieee80211_frame *wh = ATH_SKB_2_WH(bf->bf_skb);
850 if (!(wh->i_fc[1] & IEEE80211_FC1_WEP)) {
851 bf->bf_keytype = HAL_KEY_TYPE_CLEAR;
852 bf->bf_keyix = HAL_TXKEYIX_INVALID;
856 switch (bf->bf_keytype) {
857 case HAL_KEY_TYPE_WEP:
858 bf->bf_pktlen += IEEE80211_WEP_ICVLEN;
860 case HAL_KEY_TYPE_AES:
861 bf->bf_pktlen += IEEE80211_WEP_MICLEN;
863 case HAL_KEY_TYPE_TKIP:
864 bf->bf_pktlen += IEEE80211_WEP_ICVLEN;
870 if (bf->bf_keytype == HAL_KEY_TYPE_AES ||
871 bf->bf_keytype == HAL_KEY_TYPE_TKIP)
872 ieee80211_tgt_crypto_encap(wh, ni, bf->bf_keytype);
877 static void ath_tgt_txq_add_ucast(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
879 struct ath_hal *ah = sc->sc_ah;
882 volatile a_int32_t txe_val;
888 status = ath_hal_txprocdesc(sc->sc_ah, bf->bf_lastds);
890 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
892 if (txq->axq_link == NULL) {
893 ath_hal_puttxbuf(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
895 *txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
897 txe_val = OS_REG_READ(ah, 0x840);
898 if (!(txe_val & (1<< txq->axq_qnum)))
899 ath_hal_puttxbuf(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
902 txq->axq_link = &bf->bf_lastds->ds_link;
903 ath_hal_txstart(ah, txq->axq_qnum);
906 static a_int32_t ath_tgt_txbuf_setup(struct ath_softc_tgt *sc,
907 struct ath_tx_buf *bf,
911 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
912 struct ieee80211_frame *wh = ATH_SKB2_WH(bf->bf_skb);
913 struct ieee80211_node_target *ni = (struct ieee80211_node_target *)an;
914 struct ieee80211vap_target *vap = ni->ni_vap;
915 struct ieee80211com_target *ic = &sc->sc_ic;
916 a_int32_t retval, fragno = 0;
917 a_uint32_t flags = adf_os_ntohl(dh->flags);
919 ath_tgt_tx_seqno_normal(bf);
921 bf->bf_txq_add = ath_tgt_txq_add_ucast;
922 bf->bf_hdrlen = ieee80211_anyhdrsize(wh);
923 bf->bf_pktlen = ath_get_pktlen(bf, bf->bf_hdrlen);
924 bf->bf_ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
926 if ((retval = ath_key_setup(bf->bf_node, bf)) < 0)
929 if (flags & ATH_SHORT_PREAMBLE)
930 bf->bf_shpream = AH_TRUE;
932 bf->bf_shpream = AH_FALSE;
934 bf->bf_flags = HAL_TXDESC_CLRDMASK;
935 bf->bf_atype = HAL_PKT_TYPE_NORMAL;
941 ath_get_pktlen(struct ath_tx_buf *bf, a_int32_t hdrlen)
943 adf_nbuf_t skb = bf->bf_skb;
946 skb = adf_nbuf_queue_first(&bf->bf_skbhead);
947 pktlen = adf_nbuf_len(skb);
949 pktlen -= (hdrlen & 3);
950 pktlen += IEEE80211_CRC_LEN;
956 ath_tgt_tx_send_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
958 struct ath_node_target *an = bf->bf_node;
959 struct ath_rc_series rcs[4];
960 struct ath_rc_series mrcs[4];
961 a_int32_t shortPreamble = 0;
962 a_int32_t isProbe = 0;
964 adf_os_mem_set(rcs, 0, sizeof(struct ath_rc_series)*4 );
965 adf_os_mem_set(mrcs, 0, sizeof(struct ath_rc_series)*4 );
967 if (!bf->bf_ismcast) {
968 ath_tgt_rate_findrate(sc, an, shortPreamble,
971 ath_hal_memcpy(bf->bf_rcs, rcs, sizeof(rcs));
973 mrcs[1].tries = mrcs[2].tries = mrcs[3].tries = 0;
974 mrcs[1].rix = mrcs[2].rix = mrcs[3].rix = 0;
978 ath_hal_memcpy(bf->bf_rcs, mrcs, sizeof(mrcs));
981 ath_buf_set_rate(sc, bf);
982 bf->bf_txq_add(sc, bf);
986 ath_tx_freebuf(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
989 struct ath_desc *bfd = NULL;
991 for (bfd = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; bfd++, i++) {
992 ath_hal_clr11n_aggr(sc->sc_ah, bfd);
993 ath_hal_set11n_burstduration(sc->sc_ah, bfd, 0);
994 ath_hal_set11n_virtualmorefrag(sc->sc_ah, bfd, 0);
997 ath_dma_unmap(sc, bf);
999 ath_tgt_skb_free(sc, &bf->bf_skbhead,bf->bf_endpt);
1005 bf = ath_buf_toggle(sc, bf, 0);
1007 bf->bf_isretried = 0;
1010 asf_tailq_insert_tail(&sc->sc_txbuf, bf, bf_list);
1014 ath_tx_uc_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1016 ath_tx_status_update(sc, bf);
1017 ath_update_stats(sc, bf);
1018 ath_rate_tx_complete(sc, ATH_NODE_TARGET(bf->bf_node),
1019 bf->bf_lastds, bf->bf_rcs, 1, 0);
1023 ath_update_stats(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1025 struct ath_tx_desc *ds = bf->bf_desc;
1028 if (ds->ds_txstat.ts_status == 0) {
1029 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE)
1030 sc->sc_tx_stats.ast_tx_altrate++;
1032 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY)
1033 sc->sc_tx_stats.ast_tx_xretries++;
1034 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO)
1035 sc->sc_tx_stats.ast_tx_fifoerr++;
1036 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT)
1037 sc->sc_tx_stats.ast_tx_filtered++;
1038 if (ds->ds_txstat.ts_status & HAL_TXERR_TIMER_EXPIRED)
1039 sc->sc_tx_stats.ast_tx_timer_exp++;
1041 sr = ds->ds_txstat.ts_shortretry;
1042 lr = ds->ds_txstat.ts_longretry;
1043 sc->sc_tx_stats.ast_tx_shortretry += sr;
1044 sc->sc_tx_stats.ast_tx_longretry += lr;
1048 ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t hdr_buf, adf_nbuf_t skb,
1049 HTC_ENDPOINT_ID endpt)
1051 struct ieee80211_node_target *ni;
1052 struct ieee80211vap_target *vap;
1053 struct ath_vap_target *avp;
1054 struct ath_hal *ah = sc->sc_ah;
1055 a_uint8_t rix, txrate, ctsrate, cix = 0xff, *data;
1056 a_uint32_t ivlen = 0, icvlen = 0, subtype, flags, ctsduration;
1057 a_int32_t i, iswep, ismcast, hdrlen, pktlen, try0, len;
1058 struct ath_desc *ds=NULL;
1059 struct ath_txq *txq=NULL;
1060 struct ath_tx_buf *bf;
1062 const HAL_RATE_TABLE *rt;
1063 HAL_BOOL shortPreamble;
1064 struct ieee80211_frame *wh;
1065 struct ath_rc_series rcs[4];
1066 HAL_11N_RATE_SERIES series[4];
1071 adf_nbuf_peek_header(skb, &data, &len);
1072 adf_nbuf_pull_head(skb, sizeof(ath_mgt_hdr_t));
1074 adf_nbuf_peek_header(hdr_buf, &data, &len);
1077 adf_os_assert(len >= sizeof(ath_mgt_hdr_t));
1079 mh = (ath_mgt_hdr_t *)data;
1080 adf_nbuf_peek_header(skb, &data, &len);
1081 wh = (struct ieee80211_frame *)data;
1083 adf_os_mem_set(rcs, 0, sizeof(struct ath_rc_series)*4);
1084 adf_os_mem_set(series, 0, sizeof(HAL_11N_RATE_SERIES)*4);
1086 bf = asf_tailq_first(&sc->sc_txbuf);
1090 asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
1092 ni = ath_tgt_find_node(sc, mh->ni_index);
1096 bf->bf_endpt = endpt;
1097 bf->bf_cookie = mh->cookie;
1098 bf->bf_protmode = mh->flags & (IEEE80211_PROT_RTSCTS | IEEE80211_PROT_CTSONLY);
1099 txq = &sc->sc_txq[1];
1100 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP;
1101 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
1102 hdrlen = ieee80211_anyhdrsize(wh);
1104 keyix = HAL_TXKEYIX_INVALID;
1105 pktlen -= (hdrlen & 3);
1106 pktlen += IEEE80211_CRC_LEN;
1111 adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, skb, ADF_OS_DMA_TO_DEVICE);
1114 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
1117 rt = sc->sc_currates;
1118 adf_os_assert(rt != NULL);
1120 if (mh->flags == ATH_SHORT_PREAMBLE)
1121 shortPreamble = AH_TRUE;
1123 shortPreamble = AH_FALSE;
1125 flags = HAL_TXDESC_CLRDMASK;
1127 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
1128 case IEEE80211_FC0_TYPE_MGT:
1129 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK;
1131 if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP)
1132 atype = HAL_PKT_TYPE_PROBE_RESP;
1133 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM)
1134 atype = HAL_PKT_TYPE_ATIM;
1136 atype = HAL_PKT_TYPE_NORMAL;
1140 atype = HAL_PKT_TYPE_NORMAL;
1144 avp = &sc->sc_vap[mh->vap_index];
1146 rcs[0].rix = ath_get_minrateidx(sc, avp);
1147 rcs[0].tries = ATH_TXMAXTRY;
1150 adf_os_mem_copy(bf->bf_rcs, rcs, sizeof(rcs));
1152 try0 = rcs[0].tries;
1153 txrate = rt->info[rix].rateCode;
1156 txrate |= rt->info[rix].shortPreamble;
1163 flags |= HAL_TXDESC_NOACK;
1165 } else if (pktlen > vap->iv_rtsthreshold) {
1166 flags |= HAL_TXDESC_RTSENA;
1167 cix = rt->info[rix].controlRate;
1170 if ((bf->bf_protmode != IEEE80211_PROT_NONE) &&
1171 rt->info[rix].phy == IEEE80211_T_OFDM &&
1172 (flags & HAL_TXDESC_NOACK) == 0) {
1173 cix = rt->info[sc->sc_protrix].controlRate;
1174 sc->sc_tx_stats.ast_tx_protect++;
1177 *(a_uint16_t *)&wh->i_seq[0] = adf_os_cpu_to_le16(ni->ni_txseqmgmt <<
1178 IEEE80211_SEQ_SEQ_SHIFT);
1179 INCR(ni->ni_txseqmgmt, IEEE80211_SEQ_MAX);
1182 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) {
1183 adf_os_assert(cix != 0xff);
1184 ctsrate = rt->info[cix].rateCode;
1185 if (shortPreamble) {
1186 ctsrate |= rt->info[cix].shortPreamble;
1187 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
1188 ctsduration += rt->info[cix].spAckDuration;
1189 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
1190 ctsduration += rt->info[cix].spAckDuration;
1192 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */
1193 ctsduration += rt->info[cix].lpAckDuration;
1194 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */
1195 ctsduration += rt->info[cix].lpAckDuration;
1197 ctsduration += ath_hal_computetxtime(ah,
1198 rt, pktlen, rix, shortPreamble);
1203 flags |= HAL_TXDESC_INTREQ;
1205 ath_hal_setuptxdesc(ah, ds
1218 , ATH_COMP_PROC_NO_COMP_NO_CCS);
1220 bf->bf_flags = flags;
1223 * Set key type in tx desc while sending the encrypted challenge to AP
1224 * in Auth frame 3 of Shared Authentication, owl needs this.
1226 if (iswep && (keyix != HAL_TXKEYIX_INVALID) &&
1227 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == IEEE80211_FC0_SUBTYPE_AUTH)
1228 ath_hal_fillkeytxdesc(ah, ds, mh->keytype);
1230 ath_filltxdesc(sc, bf);
1232 for (i=0; i<4; i++) {
1233 series[i].Tries = 2;
1234 series[i].Rate = txrate;
1235 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
1236 series[i].RateFlags = 0;
1238 ath_hal_set11n_ratescenario(ah, ds, 0, ctsrate, ctsduration, series, 4, 0);
1239 ath_tgt_txqaddbuf(sc, txq, bf, bf->bf_lastds);
1243 HTC_ReturnBuffers(sc->tgt_htc_handle, endpt, skb);
1248 ath_tgt_txqaddbuf(struct ath_softc_tgt *sc,
1249 struct ath_txq *txq, struct ath_buf *bf,
1250 struct ath_desc *lastds)
1252 struct ath_hal *ah = sc->sc_ah;
1254 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
1256 if (txq->axq_link == NULL) {
1257 ath_hal_puttxbuf(ah, txq->axq_qnum, ATH_BUF_GET_DESC_PHY_ADDR(bf));
1259 *txq->axq_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
1262 txq->axq_link = &lastds->ds_link;
1263 ath_hal_txstart(ah, txq->axq_qnum);
1266 void ath_tgt_handle_normal(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1269 struct ath_node_target *an;
1271 an = (struct ath_node_target *)bf->bf_node;
1274 tid = &an->tid[bf->bf_tidno];
1277 bf->bf_comp = ath_tgt_tx_comp_normal;
1278 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1279 ath_tgt_tx_send_normal(sc, bf);
1283 ath_tgt_tx_enqueue(struct ath_txq *txq, struct ath_atx_tid *tid)
1291 tid->sched = AH_TRUE;
1292 asf_tailq_insert_tail(&txq->axq_tidq, tid, tid_qelem);
1296 ath_tgt_txq_schedule(struct ath_softc_tgt *sc, struct ath_txq *txq)
1298 struct ath_atx_tid *tid;
1304 TAILQ_DEQ(&txq->axq_tidq, tid, tid_qelem);
1309 tid->sched = AH_FALSE;
1314 if (!(tid->flag & TID_AGGR_ENABLED))
1315 ath_tgt_tx_sched_normal(sc,tid);
1317 ath_tgt_tx_sched_aggr(sc,tid);
1321 if (!asf_tailq_empty(&tid->buf_q)) {
1322 ath_tgt_tx_enqueue(txq, tid);
1325 } while (!asf_tailq_empty(&txq->axq_tidq) && !bdone);
1329 ath_tgt_handle_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1332 struct ath_node_target *an;
1333 struct ath_txq *txq = bf->bf_txq;
1334 a_bool_t queue_frame, within_baw;
1336 an = (struct ath_node_target *)bf->bf_node;
1339 tid = &an->tid[bf->bf_tidno];
1342 bf->bf_comp = ath_tgt_tx_comp_aggr;
1344 within_baw = BAW_WITHIN(tid->seq_start, tid->baw_size,
1345 SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1347 queue_frame = ( (txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) ||
1348 (!asf_tailq_empty(&tid->buf_q)) ||
1349 (tid->paused) || (!within_baw) );
1352 asf_tailq_insert_tail(&tid->buf_q, bf, bf_list);
1353 ath_tgt_tx_enqueue(txq, tid);
1355 ath_tx_addto_baw(tid, bf);
1356 __stats(sc, txaggr_nframes);
1357 ath_tgt_tx_send_normal(sc, bf);
1362 ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
1365 struct ath_txq *txq =TID_TO_ACTXQ(tid->tidno);;
1368 if (asf_tailq_empty(&tid->buf_q))
1371 bf = asf_tailq_first(&tid->buf_q);
1372 asf_tailq_remove(&tid->buf_q, bf, bf_list);
1373 ath_tgt_tx_send_normal(sc, bf);
1375 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH);
1379 ath_tgt_tx_sched_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid)
1381 struct ath_tx_buf *bf, *bf_last;
1382 ATH_AGGR_STATUS status;
1384 struct ath_txq *txq = TID_TO_ACTXQ(tid->tidno);
1385 struct ath_desc *ds = NULL;
1389 if (asf_tailq_empty(&tid->buf_q))
1393 if (asf_tailq_empty(&tid->buf_q))
1396 asf_tailq_init(&bf_q);
1398 status = ath_tgt_tx_form_aggr(sc, tid, &bf_q);
1400 if (asf_tailq_empty(&bf_q))
1403 bf = asf_tailq_first(&bf_q);
1404 bf_last = asf_tailq_last(&bf_q, ath_bufhead_s);
1406 if (bf->bf_nframes == 1) {
1408 if(bf->bf_retries == 0)
1409 __stats(sc, txaggr_single);
1411 bf->bf_lastds = &(bf->bf_descarr[bf->bf_dmamap_info.nsegs -1]);
1412 bf->bf_lastds->ds_link = 0;
1415 for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
1416 ath_hal_clr11n_aggr(sc->sc_ah, ds);
1418 ath_buf_set_rate(sc, bf);
1419 bf->bf_txq_add(sc, bf);
1424 bf_last->bf_next = NULL;
1425 bf_last->bf_lastds->ds_link = 0;
1426 bf_last->bf_ndelim = 0;
1429 ath_buf_set_rate(sc, bf);
1430 ath_hal_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al,
1432 bf->bf_lastds = bf_last->bf_lastds;
1434 for (i = 0; i < bf_last->bf_dmamap_info.nsegs; i++)
1435 ath_hal_set11n_aggr_last(sc->sc_ah, &bf_last->bf_descarr[i]);
1437 if (status == ATH_AGGR_8K_LIMITED) {
1442 bf->bf_txq_add(sc, bf);
1443 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
1444 status != ATH_TGT_AGGR_BAW_CLOSED);
1447 static u_int32_t ath_lookup_rate(struct ath_softc_tgt *sc,
1448 struct ath_node_target *an,
1449 struct ath_tx_buf *bf)
1452 u_int32_t max4msframelen, frame_length;
1453 u_int16_t aggr_limit, legacy=0;
1454 const HAL_RATE_TABLE *rt = sc->sc_currates;
1455 struct ieee80211_node_target *ieee_node = (struct ieee80211_node_target *)an;
1457 if (bf->bf_ismcast) {
1458 bf->bf_rcs[1].tries = bf->bf_rcs[2].tries = bf->bf_rcs[3].tries = 0;
1459 bf->bf_rcs[0].rix = 0xb;
1460 bf->bf_rcs[0].tries = ATH_TXMAXTRY - 1;
1461 bf->bf_rcs[0].flags = 0;
1463 ath_tgt_rate_findrate(sc, an, AH_TRUE, 0, ATH_TXMAXTRY-1, 4, 1,
1464 ATH_RC_PROBE_ALLOWED, bf->bf_rcs, &prate);
1467 max4msframelen = IEEE80211_AMPDU_LIMIT_MAX;
1469 for (i = 0; i < 4; i++) {
1470 if (bf->bf_rcs[i].tries) {
1471 frame_length = bf->bf_rcs[i].max4msframelen;
1473 if (rt->info[bf->bf_rcs[i].rix].phy != IEEE80211_T_HT) {
1478 max4msframelen = ATH_MIN(max4msframelen, frame_length);
1482 if (prate || legacy)
1485 if (sc->sc_ic.ic_enable_coex)
1486 aggr_limit = ATH_MIN((max4msframelen*3)/8, sc->sc_ic.ic_ampdu_limit);
1488 aggr_limit = ATH_MIN(max4msframelen, sc->sc_ic.ic_ampdu_limit);
1490 if (ieee_node->ni_maxampdu)
1491 aggr_limit = ATH_MIN(aggr_limit, ieee_node->ni_maxampdu);
1496 int ath_tgt_tx_form_aggr(struct ath_softc_tgt *sc, ath_atx_tid_t *tid,
1499 struct ath_tx_buf *bf_first ,*bf_prev = NULL;
1500 int nframes = 0, rl = 0;;
1501 struct ath_desc *ds = NULL;
1502 struct ath_tx_buf *bf;
1503 u_int16_t aggr_limit = (64*1024 -1), al = 0, bpad = 0, al_delta;
1504 u_int16_t h_baw = tid->baw_size/2, prev_al = 0, prev_frames = 0;
1506 bf_first = asf_tailq_first(&tid->buf_q);
1509 bf = asf_tailq_first(&tid->buf_q);
1512 if (!BAW_WITHIN(tid->seq_start, tid->baw_size,
1513 SEQNO_FROM_BF_SEQNO(bf->bf_seqno))) {
1515 bf_first->bf_al= al;
1516 bf_first->bf_nframes = nframes;
1517 return ATH_TGT_AGGR_BAW_CLOSED;
1521 aggr_limit = ath_lookup_rate(sc, tid->an, bf);
1525 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_pktlen;
1527 if (nframes && (aggr_limit < (al + bpad + al_delta + prev_al))) {
1528 bf_first->bf_al= al;
1529 bf_first->bf_nframes = nframes;
1530 return ATH_TGT_AGGR_LIMITED;
1534 if ((nframes + prev_frames) >= ATH_MIN((h_baw), 17)) {
1536 if ((nframes + prev_frames) >= ATH_MIN((h_baw), 22)) {
1538 bf_first->bf_al= al;
1539 bf_first->bf_nframes = nframes;
1540 return ATH_TGT_AGGR_LIMITED;
1543 ath_tx_addto_baw(tid, bf);
1544 asf_tailq_remove(&tid->buf_q, bf, bf_list);
1545 asf_tailq_insert_tail(bf_q, bf, bf_list);
1550 adf_os_assert(bf->bf_comp == ath_tgt_tx_comp_aggr);
1552 al += bpad + al_delta;
1553 bf->bf_ndelim = ATH_AGGR_GET_NDELIM(bf->bf_pktlen);
1555 switch (bf->bf_keytype) {
1556 case HAL_KEY_TYPE_AES:
1557 bf->bf_ndelim += ATH_AGGR_ENCRYPTDELIM;
1559 case HAL_KEY_TYPE_WEP:
1560 case HAL_KEY_TYPE_TKIP:
1561 bf->bf_ndelim += 64;
1563 case HAL_KEY_TYPE_WAPI:
1564 bf->bf_ndelim += 12;
1570 bpad = PADBYTES(al_delta) + (bf->bf_ndelim << 2);
1573 bf_prev->bf_next = bf;
1574 bf_prev->bf_lastds->ds_link = ATH_BUF_GET_DESC_PHY_ADDR(bf);
1578 for(ds = bf->bf_desc; ds <= bf->bf_lastds; ds++)
1579 ath_hal_set11n_aggr_middle(sc->sc_ah, ds, bf->bf_ndelim);
1581 } while (!asf_tailq_empty(&tid->buf_q));
1583 bf_first->bf_al= al;
1584 bf_first->bf_nframes = nframes;
1586 return ATH_TGT_AGGR_DONE;
1589 void ath_tx_addto_baw(ath_atx_tid_t *tid, struct ath_tx_buf *bf)
1593 if (bf->bf_isretried) {
1597 index = ATH_BA_INDEX(tid->seq_start, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1598 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1600 TX_BUF_BITMAP_SET(tid->tx_buf_bitmap, cindex);
1602 if (index >= ((tid->baw_tail - tid->baw_head) & (ATH_TID_MAX_BUFS - 1))) {
1603 tid->baw_tail = cindex;
1604 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
1608 void ath_tgt_tx_comp_aggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1610 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1611 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1612 struct ath_tx_desc lastds;
1613 struct ath_tx_desc *ds = &lastds;
1614 struct ath_rc_series rcs[4];
1619 int nframes = bf->bf_nframes;
1620 struct ath_buf *bf_next;
1623 struct ath_buf *bar = NULL;
1624 struct ath_txq *txq;
1628 if (tid->flag & TID_CLEANUP_INPROGRES) {
1629 ath_tx_comp_cleanup(sc, bf);
1633 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1634 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1636 if (ds->ds_txstat.ts_flags == HAL_TX_SW_FILTERED) {
1641 if (!bf->bf_isaggr) {
1642 ath_tx_comp_unaggr(sc, bf);
1646 __stats(sc, tx_compaggr);
1648 asf_tailq_init(&bf_q);
1650 seq_st = ATH_DS_BA_SEQ(ds);
1651 ba = ATH_DS_BA_BITMAP(ds);
1652 tx_ok = (ATH_DS_TX_STATUS(ds) == HAL_OK);
1654 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
1655 ath_tx_comp_aggr_error(sc, bf, tid);
1659 if (tx_ok && !ATH_DS_TX_BA(ds)) {
1660 __stats(sc, txaggr_babug);
1661 adf_os_print("BA Bug?\n");
1662 ath_tx_comp_aggr_error(sc, bf, tid);
1667 ba_index = ATH_BA_INDEX(seq_st, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1668 bf_next = bf->bf_next;
1670 if (tx_ok && ATH_BA_ISSET(ba, ba_index)) {
1671 __stats(sc, txaggr_compgood);
1672 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1673 ath_tx_status_update_aggr(sc, bf, ds, rcs, 1);
1674 ath_tx_freebuf(sc, bf);
1676 ath_tx_retry_subframe(sc, bf, &bf_q, &bar);
1682 ath_update_aggr_stats(sc, ds, nframes, nbad);
1683 ath_rate_tx_complete(sc, an, ds, rcs, nframes, nbad);
1686 ath_bar_tx(sc, tid, bar);
1689 if (!asf_tailq_empty(&bf_q)) {
1690 __stats(sc, txaggr_prepends);
1691 TAILQ_INSERTQ_HEAD(&tid->buf_q, &bf_q, bf_list);
1692 ath_tgt_tx_enqueue(txq, tid);
1697 ath_tx_comp_aggr_error(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
1702 struct ath_tx_desc lastds;
1703 struct ath_desc *ds = &lastds;
1704 struct ath_rc_series rcs[4];
1705 struct ath_buf *bar = NULL;
1706 struct ath_buf *bf_next;
1707 int nframes = bf->bf_nframes;
1709 struct ath_txq *txq;
1711 asf_tailq_init(&bf_q);
1714 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1715 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1718 bf_next = bf->bf_next;
1719 ath_tx_retry_subframe(sc, bf, &bf_q, &bar);
1723 ath_update_aggr_stats(sc, ds, nframes, nframes);
1724 ath_rate_tx_complete(sc, tid->an, ds, rcs, nframes, nframes);
1727 ath_bar_tx(sc, tid, bar);
1730 if (!asf_tailq_empty(&bf_q)) {
1731 __stats(sc, txaggr_prepends);
1732 TAILQ_INSERTQ_HEAD(&tid->buf_q, &bf_q, bf_list);
1733 ath_tgt_tx_enqueue(txq, tid);
1738 ath_tx_comp_cleanup(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1741 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1742 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1743 struct ath_tx_desc lastds;
1744 struct ath_tx_desc *ds = &lastds;
1745 struct ath_rc_series rcs[4];
1750 int nframes = bf->bf_nframes;
1751 struct ath_buf *bf_next;
1754 adf_os_mem_copy(ds, bf->bf_lastds, sizeof (struct ath_tx_desc));
1755 adf_os_mem_copy(rcs, bf->bf_rcs, sizeof(rcs));
1757 seq_st = ATH_DS_BA_SEQ(ds);
1758 ba = ATH_DS_BA_BITMAP(ds);
1759 tx_ok = (ATH_DS_TX_STATUS(ds) == HAL_OK);
1761 if (!bf->bf_isaggr) {
1762 ath_update_stats(sc, bf);
1764 __stats(sc, tx_compunaggr);
1766 ath_tx_status_update(sc, bf);
1768 ath_tx_freebuf(sc, bf);
1770 if (tid->flag & TID_CLEANUP_INPROGRES) {
1771 owl_tgt_tid_cleanup(sc, tid);
1779 ba_index = ATH_BA_INDEX(seq_st, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1780 bf_next = bf->bf_next;
1782 ath_tx_status_update_aggr(sc, bf, ds, rcs, 0);
1784 ath_tx_freebuf(sc, bf);
1788 tid->flag &= ~TID_CLEANUP_INPROGRES;
1789 ath_aggr_resume_tid(sc, tid);
1796 ath_update_aggr_stats(sc, ds, nframes, nbad);
1797 ath_rate_tx_complete(sc, an, ds, rcs, nframes, nbad);
1801 ath_tx_retry_subframe(struct ath_softc_tgt *sc, struct ath_tx_buf *bf,
1802 ath_bufhead *bf_q, struct ath_tx_buf **bar)
1805 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1806 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1807 struct ath_desc *ds = NULL;
1810 __stats(sc, txaggr_compretries);
1812 for(ds = bf->bf_desc, i = 0; i < bf->bf_dmamap_info.nsegs; ds++, i++) {
1813 ath_hal_clr11n_aggr(sc->sc_ah, ds);
1814 ath_hal_set11n_burstduration(sc->sc_ah, ds, 0);
1815 ath_hal_set11n_virtualmorefrag(sc->sc_ah, ds, 0);
1818 if (bf->bf_retries >= OWLMAX_RETRIES) {
1819 __stats(sc, txaggr_xretries);
1820 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1821 ath_tx_status_update_aggr(sc, bf, bf->bf_lastds, NULL, 0);
1826 ath_tx_freebuf(sc, bf);
1831 __stats(sc, txaggr_errlast);
1832 bf = ath_buf_toggle(sc, bf, 1);
1834 bf->bf_lastds = &(bf->bf_descarr[bf->bf_dmamap_info.nsegs - 1]);
1836 ath_tx_set_retry(sc, bf);
1837 asf_tailq_insert_tail(bf_q, bf, bf_list);
1841 ath_update_aggr_stats(struct ath_softc_tgt *sc,
1842 struct ath_tx_desc *ds, int nframes,
1846 u_int8_t status = ATH_DS_TX_STATUS(ds);
1847 u_int8_t txflags = ATH_DS_TX_FLAGS(ds);
1849 __statsn(sc, txaggr_longretries, ds->ds_txstat.ts_longretry);
1850 __statsn(sc, txaggr_shortretries, ds->ds_txstat.ts_shortretry);
1852 if (txflags & HAL_TX_DESC_CFG_ERR)
1853 __stats(sc, txaggr_desc_cfgerr);
1855 if (txflags & HAL_TX_DATA_UNDERRUN)
1856 __stats(sc, txaggr_data_urun);
1858 if (txflags & HAL_TX_DELIM_UNDERRUN)
1859 __stats(sc, txaggr_delim_urun);
1865 if (status & HAL_TXERR_XRETRY)
1866 __stats(sc, txaggr_compxretry);
1868 if (status & HAL_TXERR_FILT)
1869 __stats(sc, txaggr_filtered);
1871 if (status & HAL_TXERR_FIFO)
1872 __stats(sc, txaggr_fifo);
1874 if (status & HAL_TXERR_XTXOP)
1875 __stats(sc, txaggr_xtxop);
1877 if (status & HAL_TXERR_TIMER_EXPIRED)
1878 __stats(sc, txaggr_timer_exp);
1882 ath_tx_comp_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1884 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1885 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1886 struct ath_desc *ds = bf->bf_lastds;
1888 ath_update_stats(sc, bf);
1889 ath_rate_tx_complete(sc, an, ds, bf->bf_rcs, 1, 0);
1891 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
1892 ath_tx_retry_unaggr(sc, bf);
1895 __stats(sc, tx_compunaggr);
1897 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1898 ath_tx_status_update(sc, bf);
1899 ath_tx_freebuf(sc, bf);
1903 ath_tx_retry_unaggr(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1905 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
1906 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
1907 struct ath_txq *txq;
1911 if (bf->bf_retries >= OWLMAX_RETRIES) {
1912 __stats(sc, txunaggr_xretry);
1913 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1914 ath_tx_status_update(sc, bf);
1915 ath_bar_tx(sc, tid, bf);
1919 __stats(sc, txunaggr_compretries);
1920 if (!bf->bf_lastds->ds_link) {
1921 __stats(sc, txunaggr_errlast);
1922 bf = ath_buf_toggle(sc, bf, 1);
1925 ath_tx_set_retry(sc, bf);
1926 asf_tailq_insert_head(&tid->buf_q, bf, bf_list);
1927 ath_tgt_tx_enqueue(txq, tid);
1931 ath_tx_update_baw(ath_atx_tid_t *tid, int seqno)
1936 index = ATH_BA_INDEX(tid->seq_start, seqno);
1937 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1939 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, cindex);
1941 while (tid->baw_head != tid->baw_tail &&
1942 (!TX_BUF_BITMAP_IS_SET(tid->tx_buf_bitmap, tid->baw_head))) {
1943 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1944 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
1948 static void ath_tx_set_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
1950 struct ieee80211_frame *wh;
1952 __stats(sc, txaggr_retries);
1954 bf->bf_isretried = 1;
1956 wh = ATH_SKB_2_WH(bf->bf_skb);
1957 wh->i_fc[1] |= IEEE80211_FC1_RETRY;
1960 void ath_tgt_tx_cleanup(struct ath_softc_tgt *sc, struct ath_node_target *an,
1961 ath_atx_tid_t *tid, a_uint8_t discard_all)
1963 struct ath_tx_buf *bf;
1964 struct ath_tx_buf *bf_next;
1965 struct ath_txq *txq;
1967 txq = TID_TO_ACTXQ(tid->tidno);
1969 bf = asf_tailq_first(&tid->buf_q);
1972 if (discard_all || bf->bf_isretried) {
1973 bf_next = asf_tailq_next(bf, bf_list);
1974 TAILQ_DEQ(&tid->buf_q, bf, bf_list);
1975 if (bf->bf_isretried)
1976 ath_tx_update_baw(tid, SEQNO_FROM_BF_SEQNO(bf->bf_seqno));
1977 ath_tx_freebuf(sc, bf);
1981 bf->bf_comp = ath_tgt_tx_comp_normal;
1982 bf = asf_tailq_next(bf, bf_list);
1985 ath_aggr_pause_tid(sc, tid);
1987 while (tid->baw_head != tid->baw_tail) {
1988 if (TX_BUF_BITMAP_IS_SET(tid->tx_buf_bitmap, tid->baw_head)) {
1990 tid->flag |= TID_CLEANUP_INPROGRES;
1991 TX_BUF_BITMAP_CLR(tid->tx_buf_bitmap, tid->baw_head);
1993 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
1994 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1997 if (!(tid->flag & TID_CLEANUP_INPROGRES)) {
1998 ath_aggr_resume_tid(sc, tid);
2002 /******************/
2003 /* BAR Management */
2004 /******************/
2006 static void ath_tgt_delba_send(struct ath_softc_tgt *sc,
2007 struct ieee80211_node_target *ni,
2008 a_uint8_t tidno, a_uint8_t initiator,
2009 a_uint16_t reasoncode)
2011 struct ath_node_target *an = ATH_NODE_TARGET(ni);
2012 ath_atx_tid_t *tid = ATH_AN_2_TID(an, tidno);
2013 struct wmi_data_delba wmi_delba;
2015 tid->flag &= ~TID_AGGR_ENABLED;
2017 ath_tgt_tx_cleanup(sc, an, tid, 1);
2019 wmi_delba.ni_nodeindex = ni->ni_nodeindex;
2020 wmi_delba.tidno = tid->tidno;
2021 wmi_delba.initiator = 1;
2022 wmi_delba.reasoncode = IEEE80211_REASON_UNSPECIFIED;
2024 __stats(sc, txbar_xretry);
2025 wmi_event(sc->tgt_wmi_handle,
2031 static void ath_bar_retry(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
2033 struct ath_node_target *an = ATH_NODE_TARGET(bf->bf_node);
2034 ath_atx_tid_t *tid = ATH_AN_2_TID(an, bf->bf_tidno);
2036 if (bf->bf_retries >= OWLMAX_BAR_RETRIES) {
2037 ath_tgt_delba_send(sc, bf->bf_node, tid->tidno, 1,
2038 IEEE80211_REASON_UNSPECIFIED);
2039 ath_tgt_tid_drain(sc, tid);
2042 ath_buf_comp(sc, bf);
2046 __stats(sc, txbar_compretries);
2048 if (!bf->bf_lastds->ds_link) {
2049 __stats(sc, txbar_errlast);
2050 bf = ath_buf_toggle(sc, bf, 1);
2053 bf->bf_lastds->ds_link = 0;
2055 ath_tx_set_retry(sc, bf);
2056 ath_tgt_txq_add_ucast(sc, bf);
2059 static void ath_bar_tx_comp(struct ath_softc_tgt *sc, struct ath_tx_buf *bf)
2061 struct ath_desc *ds = bf->bf_lastds;
2062 struct ath_node_target *an;
2064 struct ath_txq *txq;
2066 an = (struct ath_node_target *)bf->bf_node;
2067 tid = &an->tid[bf->bf_tidno];
2068 txq = TID_TO_ACTXQ(tid->tidno);
2070 if (ATH_DS_TX_STATUS(ds) & HAL_TXERR_XRETRY) {
2071 ath_bar_retry(sc, bf);
2075 ath_aggr_resume_tid(sc, tid);
2078 ath_buf_comp(sc, bf);
2081 static void ath_bar_tx(struct ath_softc_tgt *sc,
2082 ath_atx_tid_t *tid, struct ath_tx_buf *bf)
2085 struct ieee80211_frame_bar *bar;
2087 struct ath_desc *ds, *ds0;
2088 HAL_11N_RATE_SERIES series[4];
2090 adf_nbuf_queue_t skbhead;
2094 __stats(sc, tx_bars);
2096 memset(&series, 0, sizeof(series));
2098 ath_aggr_pause_tid(sc, tid);
2100 skb = adf_nbuf_queue_remove(&bf->bf_skbhead);
2101 adf_nbuf_peek_header(skb, &anbdata, &anblen);
2102 adf_nbuf_trim_tail(skb, anblen);
2103 bar = (struct ieee80211_frame_bar *) anbdata;
2107 ath_dma_unmap(sc, bf);
2108 adf_nbuf_queue_add(&bf->bf_skbhead, skb);
2110 bar->i_fc[1] = IEEE80211_FC1_DIR_NODS;
2111 bar->i_fc[0] = IEEE80211_FC0_VERSION_0 |
2112 IEEE80211_FC0_TYPE_CTL |
2113 IEEE80211_FC0_SUBTYPE_BAR;
2114 bar->i_ctl = tid->tidno << IEEE80211_BAR_CTL_TID_S |
2115 IEEE80211_BAR_CTL_COMBA;
2116 bar->i_seq = adf_os_cpu_to_le16(tid->seq_start << IEEE80211_SEQ_SEQ_SHIFT);
2118 bf->bf_seqno = tid->seq_start << IEEE80211_SEQ_SEQ_SHIFT;
2120 adf_nbuf_put_tail(skb, sizeof(struct ieee80211_frame_bar));
2122 bf->bf_comp = ath_bar_tx_comp;
2123 bf->bf_tidno = tid->tidno;
2124 bf->bf_node = &tid->an->ni;
2125 ath_dma_map(sc, bf);
2126 adf_nbuf_dmamap_info(bf->bf_dmamap, &bf->bf_dmamap_info);
2129 ath_hal_setuptxdesc(sc->sc_ah, ds
2130 , adf_nbuf_len(skb) + IEEE80211_CRC_LEN
2132 , HAL_PKT_TYPE_NORMAL
2139 | HAL_TXDESC_CLRDMASK
2141 , ATH_COMP_PROC_NO_COMP_NO_CCS);
2143 skbhead = bf->bf_skbhead;
2147 for (ds0 = ds, i=0; i < bf->bf_dmamap_info.nsegs; ds0++, i++) {
2148 ath_hal_clr11n_aggr(sc->sc_ah, ds0);
2151 ath_filltxdesc(sc, bf);
2153 for (i = 0 ; i < 4; i++) {
2154 series[i].Tries = ATH_TXMAXTRY;
2155 series[i].Rate = min_rate;
2156 series[i].ChSel = sc->sc_ic.ic_tx_chainmask;
2159 ath_hal_set11n_ratescenario(sc->sc_ah, bf->bf_desc, 0, 0, 0, series, 4, 4);
2160 ath_tgt_txq_add_ucast(sc, bf);