2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <adf_os_types.h>
37 #include <adf_os_pci.h>
38 #include <adf_os_dma.h>
39 #include <adf_os_timer.h>
40 #include <adf_os_lock.h>
41 #include <adf_os_io.h>
42 #include <adf_os_mem.h>
43 #include <adf_os_util.h>
44 #include <adf_os_stdtypes.h>
45 #include <adf_os_defer.h>
46 #include <adf_os_atomic.h>
49 #include <adf_net_wcmd.h>
50 #include <adf_os_irq.h>
52 #include <if_ath_pci.h>
54 #include "ieee80211_var.h"
55 #include "if_athrate.h"
56 #include "if_athvar.h"
60 static a_int32_t ath_numrxbufs = -1;
61 static a_int32_t ath_numrxdescs = -1;
63 #if defined(PROJECT_MAGPIE)
64 uint32_t *init_htc_handle = 0;
67 #define RX_ENDPOINT_ID 3
68 #define ATH_CABQ_HANDLING_THRESHOLD 9000
72 void owl_tgt_tx_tasklet(TQUEUE_ARG data);
73 static void ath_tgt_send_beacon(struct ath_softc_tgt *sc,adf_nbuf_t bc_hdr,adf_nbuf_t nbuf,HTC_ENDPOINT_ID EndPt);
74 static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen);
75 extern struct ath_tx_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc, adf_nbuf_t skb, ath_data_hdr_t *dh);
76 extern void ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t mgt_hdr, adf_nbuf_t skb,HTC_ENDPOINT_ID EndPt);
77 extern HAL_BOOL ath_hal_wait(struct ath_hal *ah, a_uint32_t reg, a_uint32_t mask, a_uint32_t val);
78 extern void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq, owl_txq_state_t txqstate);
79 void owl_tgt_node_init(struct ath_node_target * an);
80 void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, struct ath_buf *bf);
81 void ath_tgt_tx_sched_nonaggr(struct ath_softc_tgt *sc,struct ath_buf * bf_host);
84 * Extend a 32 bit TSF to 64 bit, taking wrapping into account.
86 static u_int64_t ath_extend_tsf(struct ath_softc_tgt *sc, u_int32_t rstamp)
88 struct ath_hal *ah = sc->sc_ah;
93 tsf = ah->ah_getTsf64(ah);
94 tsf_low = tsf & 0xffffffff;
95 tsf64 = (tsf & ~0xffffffffULL) | rstamp;
97 if (rstamp > tsf_low && (rstamp - tsf_low > 0x10000000))
98 tsf64 -= 0x100000000ULL;
100 if (rstamp < tsf_low && (tsf_low - rstamp > 0x10000000))
101 tsf64 += 0x100000000ULL;
106 static a_int32_t ath_rate_setup(struct ath_softc_tgt *sc, a_uint32_t mode)
108 struct ath_hal *ah = sc->sc_ah;
109 const HAL_RATE_TABLE *rt;
112 case IEEE80211_MODE_11NA:
113 sc->sc_rates[mode] = ah->ah_getRateTable(ah, HAL_MODE_11NA);
115 case IEEE80211_MODE_11NG:
116 sc->sc_rates[mode] = ah->ah_getRateTable(ah, HAL_MODE_11NG);
121 rt = sc->sc_rates[mode];
128 static void ath_setcurmode(struct ath_softc_tgt *sc,
129 enum ieee80211_phymode mode)
131 const HAL_RATE_TABLE *rt;
134 adf_os_mem_set(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
136 rt = sc->sc_rates[mode];
137 adf_os_assert(rt != NULL);
139 for (i = 0; i < rt->rateCount; i++) {
140 sc->sc_rixmap[rt->info[i].rateCode] = i;
143 sc->sc_currates = rt;
144 sc->sc_curmode = mode;
145 sc->sc_protrix = ((mode == IEEE80211_MODE_11NG) ? 3 : 0);
149 void wmi_event(wmi_handle_t handle, WMI_EVENT_ID evt_id,
150 void *buffer, a_int32_t Length)
152 adf_nbuf_t netbuf = ADF_NBUF_NULL;
155 netbuf = WMI_AllocEvent(handle, WMI_EVT_CLASS_CMD_EVENT,
156 sizeof(WMI_CMD_HDR) + Length);
158 if (netbuf == ADF_NBUF_NULL) {
159 adf_os_print("Buf null\n");
163 if (buffer != NULL && Length != 0 && Length < WMI_SVC_MAX_BUFFERED_EVENT_SIZE) {
164 pData = adf_nbuf_put_tail(netbuf, Length);
165 adf_os_mem_copy(pData, buffer, Length);
168 WMI_SendEvent(handle, netbuf, evt_id, 0, Length);
171 void wmi_cmd_rsp(void *pContext, WMI_COMMAND_ID cmd_id, A_UINT16 SeqNo,
172 void *buffer, a_int32_t Length)
174 adf_nbuf_t netbuf = ADF_NBUF_NULL;
177 netbuf = WMI_AllocEvent(pContext, WMI_EVT_CLASS_CMD_REPLY,
178 sizeof(WMI_CMD_HDR) + Length);
180 if (netbuf == ADF_NBUF_NULL) {
185 if (Length != 0 && buffer != NULL) {
186 pData = (A_UINT8 *)adf_nbuf_put_tail(netbuf, Length);
187 adf_os_mem_copy(pData, buffer, Length);
190 WMI_SendEvent(pContext, netbuf, cmd_id, SeqNo, Length);
193 static void ath_node_vdelete_tgt(struct ath_softc_tgt *sc, a_uint8_t vap_index)
197 for (i = 0; i < TARGET_NODE_MAX; i++) {
198 if(sc->sc_sta[i].ni.ni_vapindex == vap_index)
199 sc->sc_sta[i].an_valid = 0;
203 a_uint8_t ath_get_minrateidx(struct ath_softc_tgt *sc, struct ath_vap_target *avp)
205 if (sc->sc_curmode == IEEE80211_MODE_11NG)
206 return avp->av_minrateidx[0];
207 else if (sc->sc_curmode == IEEE80211_MODE_11NA)
208 return avp->av_minrateidx[1];
217 static adf_nbuf_t ath_alloc_skb_align(struct ath_softc_tgt *sc,
218 a_uint32_t size, a_uint32_t align)
222 skb = BUF_Pool_alloc_buf_align(sc->pool_handle, POOL_ID_WLAN_RX_BUF,
223 RX_HEADER_SPACE, align);
227 static a_int32_t ath_rxdesc_init(struct ath_softc_tgt *sc, struct ath_rx_desc *ds)
229 struct ath_hal *ah = sc->sc_ah;
230 struct ath_rx_desc *ds_held;
234 if (!sc->sc_rxdesc_held) {
235 sc->sc_rxdesc_held = ds;
239 ds_held = sc->sc_rxdesc_held;
240 sc->sc_rxdesc_held = ds;
243 if (ds->ds_nbuf == ADF_NBUF_NULL) {
244 ds->ds_nbuf = ath_alloc_skb_align(sc, sc->sc_rxbufsize, sc->sc_cachelsz);
245 if (ds->ds_nbuf == ADF_NBUF_NULL) {
246 sc->sc_rxdesc_held = ds;
247 sc->sc_rx_stats.ast_rx_nobuf++;
250 adf_nbuf_map(sc->sc_dev, ds->ds_dmap, ds->ds_nbuf, ADF_OS_DMA_FROM_DEVICE);
251 adf_nbuf_dmamap_info(ds->ds_dmap, &ds->ds_dmap_info);
252 ds->ds_data = ds->ds_dmap_info.dma_segs[0].paddr;
256 adf_nbuf_peek_header(ds->ds_nbuf, &anbdata, &anblen);
258 ah->ah_setupRxDesc(ds, adf_nbuf_tailroom(ds->ds_nbuf), 0);
260 if (sc->sc_rxlink == NULL) {
261 ah->ah_setRxDP(ah, ds->ds_daddr);
264 *sc->sc_rxlink = ds->ds_daddr;
266 sc->sc_rxlink = &ds->ds_link;
267 ah->ah_enableReceive(ah);
272 static void ath_rx_complete(struct ath_softc_tgt *sc, adf_nbuf_t buf)
274 struct ath_rx_desc *ds;
276 adf_nbuf_queue_t nbuf_head;
278 adf_nbuf_split_to_frag(buf, &nbuf_head);
279 ds = asf_tailq_first(&sc->sc_rxdesc_idle);
282 struct ath_rx_desc *ds_tmp;
283 buf_tmp = adf_nbuf_queue_remove(&nbuf_head);
285 if (buf_tmp == NULL) {
289 BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, buf_tmp);
292 ds = asf_tailq_next(ds, ds_list);
294 ath_rxdesc_init(sc, ds_tmp);
296 asf_tailq_remove(&sc->sc_rxdesc_idle, ds_tmp, ds_list);
297 asf_tailq_insert_tail(&sc->sc_rxdesc, ds_tmp, ds_list);
301 static void tgt_HTCSendCompleteHandler(HTC_ENDPOINT_ID Endpt, adf_nbuf_t buf, void *ServiceCtx)
303 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
305 if (Endpt == RX_ENDPOINT_ID) {
306 sc->sc_rx_stats.ast_rx_done++;
307 ath_rx_complete(sc, buf);
311 static void ath_uapsd_processtriggers(struct ath_softc_tgt *sc)
313 struct ath_hal *ah = sc->sc_ah;
314 struct ath_rx_buf *bf = NULL;
315 struct ath_rx_desc *ds, *ds_head, *ds_tail, *ds_tmp;
318 a_uint16_t frame_len = 0;
321 #define PA2DESC(_sc, _pa) \
322 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
323 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
325 tsf = ah->ah_getTsf64(ah);
326 bf = asf_tailq_first(&sc->sc_rxbuf);
328 ds = asf_tailq_first(&sc->sc_rxdesc);
334 if (cnt == ath_numrxbufs - 1) {
335 adf_os_print("VERY LONG PACKET!!!!!\n");
339 struct ath_rx_desc *ds_rmv;
340 adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE);
342 ds_tmp = asf_tailq_next(ds_tmp, ds_list);
344 if (ds_tmp == NULL) {
345 adf_os_print("ds_tmp is NULL\n");
349 BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ds_rmv->ds_nbuf);
350 ds_rmv->ds_nbuf = ADF_NBUF_NULL;
352 if (ath_rxdesc_init(sc, ds_rmv) == 0) {
353 asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
354 asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list);
357 asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
358 asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list);
361 if (ds_rmv == ds_tail) {
368 if (ds->ds_link == 0) {
372 if (bf->bf_status & ATH_BUFSTATUS_DONE) {
376 retval = ah->ah_procRxDescFast(ah, ds, ds->ds_daddr,
377 PA2DESC(sc, ds->ds_link), &bf->bf_rx_status);
378 if (HAL_EINPROGRESS == retval) {
382 if (adf_nbuf_len(ds->ds_nbuf) == 0) {
383 adf_nbuf_put_tail(ds->ds_nbuf, bf->bf_rx_status.rs_datalen);
386 frame_len += bf->bf_rx_status.rs_datalen;
388 if (bf->bf_rx_status.rs_more == 0) {
389 adf_nbuf_queue_t nbuf_head;
390 adf_nbuf_queue_init(&nbuf_head);
395 ds = asf_tailq_next(ds, ds_list);
398 ds_head = asf_tailq_next(ds_tail, ds_list);
401 struct ath_rx_desc *ds_rmv;
403 adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE);
404 adf_nbuf_queue_add(&nbuf_head, ds_tmp->ds_nbuf);
405 ds_tmp->ds_nbuf = ADF_NBUF_NULL;
408 ds_tmp = asf_tailq_next(ds_tmp, ds_list);
409 if (ds_tmp == NULL) {
413 if (ath_rxdesc_init(sc, ds_rmv) == 0) {
414 asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
415 asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list);
417 asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
418 asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list);
421 if (ds_rmv == ds_tail) {
427 bf->bf_rx_status.rs_datalen = frame_len;
430 bf->bf_skb = adf_nbuf_create_frm_frag(&nbuf_head);
432 bf->bf_status |= ATH_BUFSTATUS_DONE;
434 bf = (struct ath_rx_buf *)asf_tailq_next(bf, bf_list);
437 ds = asf_tailq_next(ds, ds_list);
444 static a_int32_t ath_startrecv(struct ath_softc_tgt *sc)
446 struct ath_hal *ah = sc->sc_ah;
447 struct ath_rx_desc *ds;
449 sc->sc_rxbufsize = 1024+512+128;
450 sc->sc_rxlink = NULL;
452 sc->sc_rxdesc_held = NULL;
454 asf_tailq_foreach(ds, &sc->sc_rxdesc, ds_list) {
455 a_int32_t error = ath_rxdesc_init(sc, ds);
461 ds = asf_tailq_first(&sc->sc_rxdesc);
462 ah->ah_setRxDP(ah, ds->ds_daddr);
467 static void ath_tgt_rx_tasklet(TQUEUE_ARG data)
469 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
470 struct ath_rx_buf *bf = NULL;
471 struct ath_hal *ah = sc->sc_ah;
472 struct rx_frame_header *rxhdr;
473 struct ath_rx_status *rxstats;
474 adf_nbuf_t skb = ADF_NBUF_NULL;
477 bf = asf_tailq_first(&sc->sc_rxbuf);
482 if (!(bf->bf_status & ATH_BUFSTATUS_DONE)) {
491 asf_tailq_remove(&sc->sc_rxbuf, bf, bf_list);
495 rxhdr = (struct rx_frame_header *)adf_nbuf_push_head(skb,
496 sizeof(struct rx_frame_header));
497 rxstats = (struct ath_rx_status *)(&rxhdr->rx_stats[0]);
498 adf_os_mem_copy(rxstats, &(bf->bf_rx_status),
499 sizeof(struct ath_rx_status));
501 rxstats->rs_tstamp = ath_extend_tsf(sc, (u_int32_t)rxstats->rs_tstamp);
503 HTC_SendMsg(sc->tgt_htc_handle, RX_ENDPOINT_ID, skb);
504 sc->sc_rx_stats.ast_rx_send++;
506 bf->bf_status &= ~ATH_BUFSTATUS_DONE;
507 asf_tailq_insert_tail(&sc->sc_rxbuf, bf, bf_list);
511 sc->sc_imask |= HAL_INT_RX;
512 ah->ah_setInterrupts(ah, sc->sc_imask);
515 /*******************/
516 /* Beacon Handling */
517 /*******************/
520 * Setup the beacon frame for transmit.
521 * FIXME: Short Preamble.
523 static void ath_beacon_setup(struct ath_softc_tgt *sc,
524 struct ath_tx_buf *bf,
525 struct ath_vap_target *avp)
527 adf_nbuf_t skb = bf->bf_skb;
528 struct ath_hal *ah = sc->sc_ah;
529 struct ath_tx_desc *ds;
531 const HAL_RATE_TABLE *rt;
533 HAL_11N_RATE_SERIES series[4] = {{ 0 }};
535 flags = HAL_TXDESC_NOACK;
539 ds->ds_data = bf->bf_dmamap_info.dma_segs[0].paddr;
541 rix = ath_get_minrateidx(sc, avp);
542 rt = sc->sc_currates;
543 rate = rt->info[rix].rateCode;
545 ah->ah_setupTxDesc(ds
546 , adf_nbuf_len(skb) + IEEE80211_CRC_LEN
547 , sizeof(struct ieee80211_frame)
548 , HAL_PKT_TYPE_BEACON
551 , HAL_TXKEYIX_INVALID
557 , asf_roundup(adf_nbuf_len(skb), 4)
563 series[0].Rate = rate;
564 series[0].ChSel = sc->sc_ic.ic_tx_chainmask;
565 series[0].RateFlags = 0;
566 ah->ah_set11nRateScenario(ds, 0, 0, series, 4, 0);
569 static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr,
570 adf_nbuf_t nbuf, HTC_ENDPOINT_ID EndPt)
572 struct ath_hal *ah = sc->sc_ah;
573 struct ath_tx_buf *bf;
574 a_uint8_t vap_index, *anbdata;
575 ath_beacon_hdr_t *bhdr;
576 struct ieee80211vap_target *vap;
578 struct ieee80211_frame *wh;
581 adf_nbuf_peek_header(nbuf, &anbdata, &anblen);
582 bhdr = (ath_beacon_hdr_t *)anbdata;
584 adf_os_print("found bc_hdr! 0x%x\n", bc_hdr);
587 vap_index = bhdr->vap_index;
588 adf_os_assert(vap_index < TARGET_VAP_MAX);
589 vap = &sc->sc_vap[vap_index].av_vap;
591 wh = (struct ieee80211_frame *)adf_nbuf_pull_head(nbuf,
592 sizeof(ath_beacon_hdr_t));
594 bf = sc->sc_vap[vap_index].av_bcbuf;
596 bf->bf_endpt = EndPt;
599 adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE);
600 adf_nbuf_push_head(bf->bf_skb, sizeof(ath_beacon_hdr_t));
601 ath_free_tx_skb(sc->tgt_htc_handle, bf->bf_endpt, bf->bf_skb);
606 adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, nbuf, ADF_OS_DMA_TO_DEVICE);
607 adf_nbuf_dmamap_info(bf->bf_dmamap,&bf->bf_dmamap_info);
609 ath_beacon_setup(sc, bf, &sc->sc_vap[vap_index]);
610 ah->ah_stopTxDma(ah, sc->sc_bhalq);
611 ah->ah_setTxDP(ah, sc->sc_bhalq, ATH_BUF_GET_DESC_PHY_ADDR(bf));
612 ah->ah_startTxDma(ah, sc->sc_bhalq);
619 static void ath_tx_stopdma(struct ath_softc_tgt *sc, struct ath_txq *txq)
621 struct ath_hal *ah = sc->sc_ah;
623 ah->ah_stopTxDma(ah, txq->axq_qnum);
626 static void owltgt_txq_drain(struct ath_softc_tgt *sc, struct ath_txq *txq)
628 owltgt_tx_processq(sc, txq, OWL_TXQ_STOPPED);
631 static void ath_tx_draintxq(struct ath_softc_tgt *sc, struct ath_txq *txq)
633 owltgt_txq_drain(sc, txq);
636 static void ath_draintxq(struct ath_softc_tgt *sc, HAL_BOOL drain_softq)
638 struct ath_hal *ah = sc->sc_ah;
640 struct ath_txq *txq = NULL;
641 struct ath_atx_tid *tid = NULL;
643 ath_tx_status_clear(sc);
644 sc->sc_tx_draining = 1;
646 ah->ah_stopTxDma(ah, sc->sc_bhalq);
648 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
649 if (ATH_TXQ_SETUP(sc, i))
650 ath_tx_stopdma(sc, ATH_TXQ(sc, i));
652 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
653 if (ATH_TXQ_SETUP(sc, i)) {
654 owltgt_tx_processq(sc, ATH_TXQ(sc,i), OWL_TXQ_STOPPED);
657 while (!asf_tailq_empty(&txq->axq_tidq)){
658 TAILQ_DEQ(&txq->axq_tidq, tid, tid_qelem);
661 tid->sched = AH_FALSE;
662 ath_tgt_tid_drain(sc,tid);
666 sc->sc_tx_draining = 0;
669 static void ath_tgt_txq_setup(struct ath_softc_tgt *sc)
676 for (qnum=0;qnum<HAL_NUM_TX_QUEUES;qnum++) {
677 txq= &sc->sc_txq[qnum];
678 txq->axq_qnum = qnum;
679 txq->axq_link = NULL;
680 asf_tailq_init(&txq->axq_q);
682 txq->axq_linkbuf = NULL;
683 asf_tailq_init(&txq->axq_tidq);
684 sc->sc_txqsetup |= 1<<qnum;
687 sc->sc_uapsdq = &sc->sc_txq[UAPSDQ_NUM];
688 sc->sc_cabq = &sc->sc_txq[CABQ_NUM];
690 sc->sc_ac2q[WME_AC_BE] = &sc->sc_txq[0];
691 sc->sc_ac2q[WME_AC_BK] = &sc->sc_txq[1];
692 sc->sc_ac2q[WME_AC_VI] = &sc->sc_txq[2];
693 sc->sc_ac2q[WME_AC_VO] = &sc->sc_txq[3];
699 static void tgt_HTCRecv_beaconhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
700 adf_nbuf_t buf, void *ServiceCtx)
702 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
704 ath_tgt_send_beacon(sc, hdr_buf, buf, EndPt);
707 static void tgt_HTCRecv_uapsdhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
708 adf_nbuf_t buf, void *ServiceCtx)
712 static void tgt_HTCRecv_mgmthandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
713 adf_nbuf_t buf, void *ServiceCtx)
715 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
717 ath_tgt_send_mgt(sc,hdr_buf,buf,EndPt);
720 static void tgt_HTCRecvMessageHandler(HTC_ENDPOINT_ID EndPt,
721 adf_nbuf_t hdr_buf, adf_nbuf_t buf,
724 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
725 struct ath_tx_buf *bf;
729 struct ath_node_target *an;
730 struct ath_atx_tid *tid;
733 adf_nbuf_peek_header(buf, &data, &len);
734 adf_nbuf_pull_head(buf, sizeof(ath_data_hdr_t));
736 adf_nbuf_peek_header(hdr_buf, &data, &len);
739 adf_os_assert(len >= sizeof(ath_data_hdr_t));
740 dh = (ath_data_hdr_t *)data;
742 an = &sc->sc_sta[dh->ni_index];
743 tid = ATH_AN_2_TID(an, dh->tidno);
745 sc->sc_tx_stats.tx_tgt++;
747 bf = ath_tgt_tx_prepare(sc, buf, dh);
749 ath_free_tx_skb(sc->tgt_htc_handle,EndPt,buf);
753 bf->bf_endpt = EndPt;
754 bf->bf_cookie = dh->cookie;
756 if (tid->flag & TID_AGGR_ENABLED)
757 ath_tgt_handle_aggr(sc, bf);
759 ath_tgt_handle_normal(sc, bf);
762 static void tgt_HTCRecv_cabhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
763 adf_nbuf_t buf, void *ServiceCtx)
765 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
766 struct ath_hal *ah = sc->sc_ah;
770 #ifdef ATH_ENABLE_CABQ
771 tsf = ah->ah_getTsf64(ah);
772 tmp = tsf - sc->sc_swba_tsf;
774 if ( tmp > ATH_CABQ_HANDLING_THRESHOLD ) {
775 HTC_ReturnBuffers(sc->tgt_htc_handle, EndPt, buf);
779 tgt_HTCRecvMessageHandler(EndPt, hdr_buf, buf, ServiceCtx);
783 /***********************/
784 /* Descriptor Handling */
785 /***********************/
787 static a_int32_t ath_descdma_setup(struct ath_softc_tgt *sc,
788 struct ath_descdma *dd, ath_bufhead *head,
789 const char *name, a_int32_t nbuf, a_int32_t ndesc,
790 a_uint32_t bfSize, a_uint32_t descSize)
792 #define DS2PHYS(_dd, _ds) \
793 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
797 a_int32_t i, bsize, error;
802 dd->dd_desc_len = descSize * nbuf * ndesc;
804 dd->dd_desc = adf_os_dmamem_alloc(sc->sc_dev,
805 dd->dd_desc_len, 1, &dd->dd_desc_dmamap);
806 dd->dd_desc_paddr = adf_os_dmamem_map2addr(dd->dd_desc_dmamap);
807 if (dd->dd_desc == NULL) {
813 bsize = bfSize * nbuf;
814 bf = adf_os_mem_alloc(bsize);
819 adf_os_mem_set(bf, 0, bsize);
822 bf_addr = (a_uint8_t *)bf;
823 ds_addr = (a_uint8_t *)ds;
825 asf_tailq_init(head);
827 for (i = 0; i < nbuf; i++) {
830 if (adf_nbuf_dmamap_create( sc->sc_dev, &bf->bf_dmamap) != A_STATUS_OK) {
834 bf->bf_desc = bf->bf_descarr = bf->bf_lastds = ds;
835 for (j = 0; j < ndesc; j++)
836 ATH_BUF_SET_DESC_PHY_ADDR_WITH_IDX(bf, j, (ds_addr + (j*descSize)));
838 ATH_BUF_SET_DESC_PHY_ADDR(bf, ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, 0));
840 adf_nbuf_queue_init(&bf->bf_skbhead);
841 asf_tailq_insert_tail(head, bf, bf_list);
844 ds_addr += (ndesc * descSize);
845 bf = (struct ath_buf *)bf_addr;
846 ds = (struct ath_desc *)ds_addr;
851 adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len,
852 1, dd->dd_desc, dd->dd_desc_dmamap);
854 adf_os_mem_set(dd, 0, sizeof(*dd));
861 static void ath_descdma_cleanup(struct ath_softc_tgt *sc,
862 struct ath_descdma *dd,
863 ath_bufhead *head, a_int32_t dir)
866 struct ieee80211_node_target *ni;
868 asf_tailq_foreach(bf, head, bf_list) {
869 if (adf_nbuf_queue_len(&bf->bf_skbhead) != 0) {
870 adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, dir);
871 while(adf_nbuf_queue_len(&bf->bf_skbhead) != 0) {
873 adf_nbuf_queue_remove(&bf->bf_skbhead));
876 } else if (bf->bf_skb != NULL) {
877 adf_nbuf_unmap(sc->sc_dev,bf->bf_dmamap, dir);
878 ath_free_rx_skb(sc, bf->bf_skb);
882 adf_nbuf_dmamap_destroy(sc->sc_dev, bf->bf_dmamap);
888 adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len,
889 1, dd->dd_desc, dd->dd_desc_dmamap);
891 asf_tailq_init(head);
892 adf_os_mem_free(dd->dd_bufptr);
893 adf_os_mem_set(dd, 0, sizeof(*dd));
896 static a_int32_t ath_desc_alloc(struct ath_softc_tgt *sc)
898 #define DS2PHYS(_dd, _ds) \
899 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
902 struct ath_tx_buf *bf;
904 if(ath_numrxbufs == -1)
905 ath_numrxbufs = ATH_RXBUF;
907 if (ath_numrxdescs == -1)
908 ath_numrxdescs = ATH_RXDESC;
910 error = ath_descdma_setup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
911 "rx", ath_numrxdescs, 1,
912 sizeof(struct ath_rx_buf),
913 sizeof(struct ath_rx_desc));
918 struct ath_descdma *dd = &sc->sc_rxdma;
919 struct ath_rx_desc *ds = (struct ath_rx_desc *)dd->dd_desc;
920 struct ath_rx_desc *ds_prev = NULL;
922 asf_tailq_init(&sc->sc_rxdesc);
923 asf_tailq_init(&sc->sc_rxdesc_idle);
925 for (i = 0; i < ath_numrxdescs; i++, ds++) {
927 if (ds->ds_nbuf != ADF_NBUF_NULL) {
928 ds->ds_nbuf = ADF_NBUF_NULL;
931 if (adf_nbuf_dmamap_create(sc->sc_dev, &ds->ds_dmap) != A_STATUS_OK) {
935 ds->ds_daddr = DS2PHYS(&sc->sc_rxdma, ds);
938 ds_prev->ds_link = ds->ds_daddr;
944 asf_tailq_insert_tail(&sc->sc_rxdesc, ds, ds_list);
947 error = ath_descdma_setup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
948 "tx", ATH_TXBUF + 1, ATH_TXDESC,
949 sizeof(struct ath_tx_buf),
950 sizeof(struct ath_tx_desc));
952 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
953 ADF_OS_DMA_FROM_DEVICE);
957 error = ath_descdma_setup(sc, &sc->sc_bdma, (ath_bufhead *)&sc->sc_bbuf,
958 "beacon", ATH_BCBUF, 1,
959 sizeof(struct ath_tx_buf),
960 sizeof(struct ath_tx_desc));
962 ath_descdma_cleanup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
963 ADF_OS_DMA_TO_DEVICE);
964 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
965 ADF_OS_DMA_FROM_DEVICE);
969 bf = asf_tailq_first(&sc->sc_txbuf);
970 bf->bf_isaggr = bf->bf_isretried = bf->bf_retries = 0;
971 asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
973 sc->sc_txbuf_held = bf;
980 static void ath_desc_free(struct ath_softc_tgt *sc)
982 asf_tailq_insert_tail(&sc->sc_txbuf, sc->sc_txbuf_held, bf_list);
984 sc->sc_txbuf_held = NULL;
986 if (sc->sc_txdma.dd_desc_len != 0)
987 ath_descdma_cleanup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
988 ADF_OS_DMA_TO_DEVICE);
989 if (sc->sc_rxdma.dd_desc_len != 0)
990 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
991 ADF_OS_DMA_FROM_DEVICE);
994 /**********************/
995 /* Interrupt Handling */
996 /**********************/
998 adf_os_irq_resp_t ath_intr(adf_drv_handle_t hdl)
1000 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)hdl;
1001 struct ath_hal *ah = sc->sc_ah;
1005 return ADF_OS_IRQ_NONE;
1007 if (!ah->ah_isInterruptPending(ah))
1008 return ADF_OS_IRQ_NONE;
1010 ah->ah_getPendingInterrupts(ah, &status);
1012 status &= sc->sc_imask;
1014 if (status & HAL_INT_FATAL) {
1015 ah->ah_setInterrupts(ah, 0);
1016 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_fataltq);
1018 if (status & HAL_INT_SWBA) {
1019 WMI_SWBA_EVENT swbaEvt;
1020 struct ath_txq *txq = ATH_TXQ(sc, 8);
1022 swbaEvt.tsf = ah->ah_getTsf64(ah);
1023 swbaEvt.beaconPendingCount = ah->ah_numTxPending(ah, sc->sc_bhalq);
1024 sc->sc_swba_tsf = ah->ah_getTsf64(ah);
1026 wmi_event(sc->tgt_wmi_handle,
1029 sizeof(WMI_SWBA_EVENT));
1031 ath_tx_draintxq(sc, txq);
1034 if (status & HAL_INT_RXORN)
1035 sc->sc_int_stats.ast_rxorn++;
1037 if (status & HAL_INT_RXEOL)
1038 sc->sc_int_stats.ast_rxeol++;
1040 if (status & (HAL_INT_RX | HAL_INT_RXEOL | HAL_INT_RXORN)) {
1041 if (status & HAL_INT_RX)
1042 sc->sc_int_stats.ast_rx++;
1044 ath_uapsd_processtriggers(sc);
1046 sc->sc_imask &= ~HAL_INT_RX;
1047 ah->ah_setInterrupts(ah, sc->sc_imask);
1049 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_rxtq);
1052 if (status & HAL_INT_TXURN) {
1053 sc->sc_int_stats.ast_txurn++;
1054 ah->ah_updateTxTrigLevel(ah, AH_TRUE);
1057 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_txtq);
1059 if (status & HAL_INT_BMISS) {
1060 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_bmisstq);
1063 if (status & HAL_INT_GTT)
1064 sc->sc_int_stats.ast_txto++;
1066 if (status & HAL_INT_CST)
1067 sc->sc_int_stats.ast_cst++;
1070 return ADF_OS_IRQ_HANDLED;
1073 static void ath_fatal_tasklet(TQUEUE_ARG data )
1075 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
1077 wmi_event(sc->tgt_wmi_handle, WMI_FATAL_EVENTID, NULL, 0);
1080 static void ath_bmiss_tasklet(TQUEUE_ARG data)
1082 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
1084 wmi_event(sc->tgt_wmi_handle, WMI_BMISS_EVENTID, NULL, 0);
1091 static void ath_enable_intr_tgt(void *Context, A_UINT16 Command,
1092 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1094 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1095 struct ath_hal *ah = sc->sc_ah;
1099 intr = (*(a_uint32_t *)data);
1101 intr = adf_os_ntohl(intr);
1103 if (intr & HAL_INT_SWBA) {
1104 sc->sc_imask |= HAL_INT_SWBA;
1106 sc->sc_imask &= ~HAL_INT_SWBA;
1109 if (intr & HAL_INT_BMISS) {
1110 sc->sc_imask |= HAL_INT_BMISS;
1113 ah->ah_setInterrupts(ah, sc->sc_imask);
1114 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
1117 static void ath_init_tgt(void *Context, A_UINT16 Command,
1118 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1120 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1121 struct ath_hal *ah = sc->sc_ah;
1123 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
1124 | HAL_INT_RXEOL | HAL_INT_RXORN
1125 | HAL_INT_FATAL | HAL_INT_GLOBAL;
1127 sc->sc_imask |= HAL_INT_GTT;
1129 if (ath_hal_getcapability(ah, HAL_CAP_HT))
1130 sc->sc_imask |= HAL_INT_CST;
1132 adf_os_setup_intr(sc->sc_dev, ath_intr);
1133 ah->ah_setInterrupts(ah, sc->sc_imask);
1135 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1138 static void ath_int_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1139 A_UINT8 *data, a_int32_t datalen)
1141 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1143 struct fusion_stats {
1145 a_uint32_t ast_rxorn;
1146 a_uint32_t ast_rxeol;
1147 a_uint32_t ast_txurn;
1148 a_uint32_t ast_txto;
1152 struct fusion_stats stats;
1154 stats.ast_rx = sc->sc_int_stats.ast_rx;
1155 stats.ast_rxorn = sc->sc_int_stats.ast_rxorn;
1156 stats.ast_rxeol = sc->sc_int_stats.ast_rxeol;
1157 stats.ast_txurn = sc->sc_int_stats.ast_txurn;
1158 stats.ast_txto = sc->sc_int_stats.ast_txto;
1159 stats.ast_cst = sc->sc_int_stats.ast_cst;
1161 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1164 static void ath_tx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1165 A_UINT8 *data, a_int32_t datalen)
1167 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1169 struct fusion_stats {
1170 a_uint32_t ast_tx_xretries;
1171 a_uint32_t ast_tx_fifoerr;
1172 a_uint32_t ast_tx_filtered;
1173 a_uint32_t ast_tx_timer_exp;
1174 a_uint32_t ast_tx_shortretry;
1175 a_uint32_t ast_tx_longretry;
1177 a_uint32_t tx_qnull;
1178 a_uint32_t tx_noskbs;
1179 a_uint32_t tx_nobufs;
1182 struct fusion_stats stats;
1184 stats.ast_tx_xretries = sc->sc_tx_stats.ast_tx_xretries;
1185 stats.ast_tx_fifoerr = sc->sc_tx_stats.ast_tx_fifoerr;
1186 stats.ast_tx_filtered = sc->sc_tx_stats.ast_tx_filtered;
1187 stats.ast_tx_timer_exp = sc->sc_tx_stats.ast_tx_timer_exp;
1188 stats.ast_tx_shortretry = sc->sc_tx_stats.ast_tx_shortretry;
1189 stats.ast_tx_longretry = sc->sc_tx_stats.ast_tx_longretry;
1190 stats.tx_qnull = sc->sc_tx_stats.tx_qnull;
1191 stats.tx_noskbs = sc->sc_tx_stats.tx_noskbs;
1192 stats.tx_nobufs = sc->sc_tx_stats.tx_nobufs;
1194 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1197 static void ath_rx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1198 A_UINT8 *data, a_int32_t datalen)
1200 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1202 struct fusion_stats {
1203 a_uint32_t ast_rx_nobuf;
1204 a_uint32_t ast_rx_send;
1205 a_uint32_t ast_rx_done;
1208 struct fusion_stats stats;
1210 stats.ast_rx_nobuf = sc->sc_rx_stats.ast_rx_nobuf;
1211 stats.ast_rx_send = sc->sc_rx_stats.ast_rx_send;
1212 stats.ast_rx_done = sc->sc_rx_stats.ast_rx_done;
1214 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1217 static void ath_get_tgt_version(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1218 A_UINT8 *data, a_int32_t datalen)
1220 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1221 struct wmi_fw_version ver;
1223 ver.major = ATH_VERSION_MAJOR;
1224 ver.minor = ATH_VERSION_MINOR;
1226 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &ver, sizeof(ver));
1229 static void ath_enable_aggr_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1230 A_UINT8 *data, a_int32_t datalen)
1232 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1233 struct ath_aggr_info *aggr = (struct ath_aggr_info *)data;
1234 a_uint8_t nodeindex = aggr->nodeindex;
1235 a_uint8_t tidno = aggr->tidno;
1236 struct ath_node_target *an = NULL ;
1237 struct ath_atx_tid *tid = NULL;
1239 if (nodeindex >= TARGET_NODE_MAX) {
1243 an = &sc->sc_sta[nodeindex];
1244 if (!an->an_valid) {
1248 if (tidno >= WME_NUM_TID) {
1249 adf_os_print("[%s] enable_aggr with invalid tid %d(node = %d)\n",
1250 __FUNCTION__, tidno, nodeindex);
1254 tid = ATH_AN_2_TID(an, tidno);
1256 if (aggr->aggr_enable) {
1257 tid->flag |= TID_AGGR_ENABLED;
1258 } else if ( tid->flag & TID_AGGR_ENABLED ) {
1259 tid->flag &= ~TID_AGGR_ENABLED;
1260 ath_tgt_tx_cleanup(sc, an, tid, 1);
1263 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1266 static void ath_ic_update_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1267 A_UINT8 *data, a_int32_t datalen)
1269 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1270 struct ieee80211com_target *ic = (struct ieee80211com_target * )data;
1271 struct ieee80211com_target *ictgt = &sc->sc_ic ;
1273 adf_os_mem_copy(ictgt, ic, sizeof(struct ieee80211com_target));
1275 ictgt->ic_ampdu_limit = adf_os_ntohl(ic->ic_ampdu_limit);
1277 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1280 static void ath_vap_create_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1281 A_UINT8 *data, a_int32_t datalen)
1283 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1284 struct ieee80211vap_target *vap;
1285 a_uint8_t vap_index;
1287 vap = (struct ieee80211vap_target *)data;
1289 vap->iv_rtsthreshold = adf_os_ntohs(vap->iv_rtsthreshold);
1290 vap->iv_opmode = adf_os_ntohl(vap->iv_opmode);
1292 vap_index = vap->iv_vapindex;
1294 adf_os_assert(sc->sc_vap[vap_index].av_valid == 0);
1296 adf_os_mem_copy(&(sc->sc_vap[vap_index].av_vap), vap,
1299 sc->sc_vap[vap_index].av_bcbuf = asf_tailq_first(&(sc->sc_bbuf));
1300 sc->sc_vap[vap_index].av_valid = 1;
1302 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1305 static void ath_node_create_tgt(void *Context, A_UINT16 Command,
1306 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1308 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1309 struct ieee80211_node_target *node;
1310 a_uint8_t vap_index;
1311 a_uint8_t node_index;
1313 node = (struct ieee80211_node_target *)data;
1315 node_index = node->ni_nodeindex;
1317 node->ni_htcap = adf_os_ntohs(node->ni_htcap);
1318 node->ni_flags = adf_os_ntohs(node->ni_flags);
1319 node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu);
1321 adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node,
1324 vap_index = sc->sc_sta[node_index].ni.ni_vapindex;
1325 sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap);
1326 if(sc->sc_sta[node_index].ni.ni_is_vapnode == 1)
1327 sc->sc_vap[vap_index].av_vap.iv_nodeindex = node_index;
1329 sc->sc_sta[node_index].an_valid = 1;
1330 sc->sc_sta[node_index].ni.ni_txseqmgmt = 0;
1331 sc->sc_sta[node_index].ni.ni_iv16 = 0;
1332 sc->sc_sta[node_index].ni.ni_iv32 = 0;
1334 owl_tgt_node_init(&sc->sc_sta[node_index]);
1336 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1339 static void ath_node_cleanup_tgt(void *Context, A_UINT16 Command,
1340 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1342 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1343 a_uint8_t node_index;
1344 a_uint8_t *nodedata;
1346 nodedata = (a_uint8_t *)data;
1347 node_index = *nodedata;
1348 sc->sc_sta[node_index].an_valid = 0;
1350 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1353 static void ath_node_update_tgt(void *Context, A_UINT16 Command,
1354 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1356 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1357 struct ieee80211_node_target *node;
1358 a_uint8_t vap_index;
1359 a_uint8_t node_index;
1361 node = (struct ieee80211_node_target *)data;
1363 node_index = node->ni_nodeindex;
1365 node->ni_htcap = adf_os_ntohs(node->ni_htcap);
1366 node->ni_flags = adf_os_ntohs(node->ni_flags);
1367 node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu);
1369 adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node,
1372 vap_index = sc->sc_sta[node_index].ni.ni_vapindex;
1373 sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap);
1375 sc->sc_sta[node_index].ni.ni_txseqmgmt = 0;
1376 sc->sc_sta[node_index].ni.ni_iv16 = 0;
1377 sc->sc_sta[node_index].ni.ni_iv32 = 0;
1379 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1382 static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command,
1383 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1385 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1386 struct ath_hal *ah = sc->sc_ah;
1391 for (i = 0; i < datalen; i += sizeof(a_int32_t)) {
1392 addr = *(a_uint32_t *)(data + i);
1393 addr = adf_os_ntohl(addr);
1395 if ((addr & 0xffffe000) == 0x2000) {
1397 ath_hal_reg_read_target(ah, addr);
1398 if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0)) {
1399 adf_os_print("SEEPROM Read fail: 0x%08x\n", addr);
1401 val[i/sizeof(a_int32_t)] = (ath_hal_reg_read_target(ah, 0x407c) & 0x0000ffff);
1402 } else if (addr > 0xffff) {
1403 val[i/sizeof(a_int32_t)] = *(a_uint32_t *)addr;
1405 val[i/sizeof(a_int32_t)] = ath_hal_reg_read_target(ah, addr);
1407 val[i/sizeof(a_int32_t)] = adf_os_ntohl(val[i/sizeof(a_int32_t)]);
1410 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &val[0], datalen);
1413 static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command,
1414 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1416 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1417 struct ath_hal *ah = sc->sc_ah;
1419 struct registerWrite {
1424 for (i = 0; i < datalen; i += sizeof(struct registerWrite)) {
1425 t = (struct registerWrite *)(data+i);
1427 if( t->reg > 0xffff ) {
1428 HAL_WORD_REG_WRITE(t->reg, t->val);
1429 #if defined(PROJECT_K2)
1430 if( t->reg == 0x50040 ) {
1431 static uint8_t flg=0;
1435 A_UART_HWINIT(117*1000*1000, 19200);
1441 #if defined(PROJECT_K2)
1442 if( t->reg == 0x7014 ) {
1443 static uint8_t resetPLL = 0;
1445 if( resetPLL == 0 ) {
1446 /* here we write to core register */
1447 HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
1448 /* and here to mac register */
1449 ath_hal_reg_write_target(ah, 0x786c,
1450 ath_hal_reg_read_target(ah,0x786c) | 0x6000000);
1451 ath_hal_reg_write_target(ah, 0x786c,
1452 ath_hal_reg_read_target(ah,0x786c) & (~0x6000000));
1454 HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20);
1458 #elif defined(PROJECT_MAGPIE) && !defined (FPGA)
1459 if( t->reg == 0x7014 ){
1460 static uint8_t resetPLL = 0;
1462 if( resetPLL == 0 ) {
1463 ath_hal_reg_write_target(ah, 0x7890,
1464 ath_hal_reg_read_target(ah,0x7890) | 0x1800000);
1465 ath_hal_reg_write_target(ah, 0x7890,
1466 ath_hal_reg_read_target(ah,0x7890) & (~0x1800000));
1471 ath_hal_reg_write_target(ah,t->reg,t->val);
1475 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1478 static void ath_vap_delete_tgt(void *Context, A_UINT16 Command,
1479 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1481 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1482 a_uint8_t vap_index;
1484 vap_index = *(a_uint8_t *)data;
1486 sc->sc_vap[vap_index].av_valid = 0;
1487 sc->sc_vap[vap_index].av_bcbuf = NULL;
1488 ath_node_vdelete_tgt(sc, vap_index);
1489 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1492 static void ath_disable_intr_tgt(void *Context, A_UINT16 Command,
1493 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1495 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1496 struct ath_hal *ah = sc->sc_ah;
1498 ah->ah_setInterrupts(ah, 0);
1499 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
1502 static void ath_flushrecv_tgt(void *Context, A_UINT16 Command,
1503 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1505 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1506 struct ath_rx_buf *bf;
1508 asf_tailq_foreach(bf, &sc->sc_rxbuf, bf_list)
1509 if (bf->bf_skb != NULL) {
1510 adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap,
1511 ADF_OS_DMA_FROM_DEVICE);
1512 ath_free_rx_skb(sc, adf_nbuf_queue_remove(&bf->bf_skbhead));
1516 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1519 static void ath_tx_draintxq_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1520 A_UINT8 *data, a_int32_t datalen)
1522 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1523 a_uint32_t q = *(a_uint32_t *)data;
1524 struct ath_txq *txq = NULL;
1526 q = adf_os_ntohl(q);
1527 txq = ATH_TXQ(sc, q);
1529 ath_tx_draintxq(sc, txq);
1530 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1533 static void ath_draintxq_tgt(void *Context, A_UINT16 Command,
1534 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1536 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1537 HAL_BOOL b = (HAL_BOOL) *(a_int32_t *)data;
1539 ath_draintxq(Context, b);
1540 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1543 static void ath_aborttx_dma_tgt(void *Context, A_UINT16 Command,
1544 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1546 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1547 struct ath_hal *ah = sc->sc_ah;
1549 ah->ah_abortTxDma(sc->sc_ah);
1550 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1553 static void ath_aborttxq_tgt(void *Context, A_UINT16 Command,
1554 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1557 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1560 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
1561 if (ATH_TXQ_SETUP(sc, i))
1562 ath_tx_draintxq(sc, ATH_TXQ(sc,i));
1565 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1568 static void ath_stop_tx_dma_tgt(void *Context, A_UINT16 Command,
1569 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1571 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1572 struct ath_hal *ah = sc->sc_ah;
1576 q = *(a_uint32_t *)data;
1578 q = adf_os_ntohl(q);
1579 ah->ah_stopTxDma(ah, q);
1580 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1583 static void ath_startrecv_tgt(void *Context, A_UINT16 Command,
1584 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1587 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1590 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1593 static void ath_stoprecv_tgt(void *Context, A_UINT16 Command,
1594 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1596 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1597 struct ath_hal *ah = sc->sc_ah;
1599 ah->ah_stopPcuReceive(ah);
1600 ah->ah_setRxFilter(ah, 0);
1601 ah->ah_stopDmaReceive(ah);
1603 sc->sc_rxlink = NULL;
1604 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1607 static void ath_setcurmode_tgt(void *Context, A_UINT16 Command,
1608 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1610 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1613 mode= *((a_uint16_t *)data);
1614 mode = adf_os_ntohs(mode);
1616 ath_setcurmode(sc, mode);
1618 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1621 static void ath_detach_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1622 A_UINT8 *data, a_int32_t datalen)
1624 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1625 struct ath_hal *ah = sc->sc_ah;
1629 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1630 adf_os_mem_free(sc);
1633 static void handle_echo_command(void *pContext, A_UINT16 Command,
1634 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1636 wmi_cmd_rsp(pContext, WMI_ECHO_CMDID, SeqNo, buffer, Length);
1639 static void handle_rc_state_change_cmd(void *Context, A_UINT16 Command,
1640 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1643 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1644 struct wmi_rc_state_change_cmd *wmi_data = (struct wmi_rc_state_change_cmd *)buffer;
1646 a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag);
1648 ath_rate_newstate(sc, &sc->sc_vap[wmi_data->vap_index].av_vap,
1649 wmi_data->vap_state,
1653 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1656 static void handle_rc_rate_update_cmd(void *Context, A_UINT16 Command,
1657 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1659 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1660 struct wmi_rc_rate_update_cmd *wmi_data = (struct wmi_rc_rate_update_cmd *)buffer;
1662 a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag);
1664 ath_rate_node_update(sc, &sc->sc_sta[wmi_data->node_index],
1669 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1672 static void dispatch_magpie_sys_cmds(void *pContext, A_UINT16 Command,
1673 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1678 static void ath_rc_mask_tgt(void *Context, A_UINT16 Command,
1679 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1681 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1682 struct wmi_rc_rate_mask_cmd *wmi_data = (struct wmi_rc_rate_mask_cmd *)buffer;
1685 idx = wmi_data->vap_index;
1686 band = wmi_data->band;
1688 sc->sc_vap[idx].av_rate_mask[band] = adf_os_ntohl(wmi_data->mask);
1690 if (sc->sc_vap[idx].av_rate_mask[band]) {
1691 for (i = 0; i < RATE_TABLE_SIZE; i++) {
1692 if ((1 << i) & sc->sc_vap[idx].av_rate_mask[band]) {
1693 sc->sc_vap[idx].av_minrateidx[band] = i;
1698 sc->sc_vap[idx].av_minrateidx[band] = 0;
1701 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1704 static WMI_DISPATCH_ENTRY Magpie_Sys_DispatchEntries[] =
1706 {handle_echo_command, WMI_ECHO_CMDID, 0},
1707 {dispatch_magpie_sys_cmds, WMI_ACCESS_MEMORY_CMDID, 0},
1708 {ath_get_tgt_version, WMI_GET_FW_VERSION, 0},
1709 {ath_disable_intr_tgt, WMI_DISABLE_INTR_CMDID, 0},
1710 {ath_enable_intr_tgt, WMI_ENABLE_INTR_CMDID, 0},
1711 {ath_init_tgt, WMI_ATH_INIT_CMDID, 0},
1712 {ath_aborttxq_tgt, WMI_ABORT_TXQ_CMDID, 0},
1713 {ath_stop_tx_dma_tgt, WMI_STOP_TX_DMA_CMDID, 0},
1714 {ath_aborttx_dma_tgt, WMI_ABORT_TX_DMA_CMDID, 0},
1715 {ath_tx_draintxq_tgt, WMI_DRAIN_TXQ_CMDID, 0},
1716 {ath_draintxq_tgt, WMI_DRAIN_TXQ_ALL_CMDID, 0},
1717 {ath_startrecv_tgt, WMI_START_RECV_CMDID, 0},
1718 {ath_stoprecv_tgt, WMI_STOP_RECV_CMDID, 0},
1719 {ath_flushrecv_tgt, WMI_FLUSH_RECV_CMDID, 0},
1720 {ath_setcurmode_tgt, WMI_SET_MODE_CMDID, 0},
1721 {ath_node_create_tgt, WMI_NODE_CREATE_CMDID, 0},
1722 {ath_node_cleanup_tgt, WMI_NODE_REMOVE_CMDID, 0},
1723 {ath_vap_delete_tgt, WMI_VAP_REMOVE_CMDID, 0},
1724 {ath_vap_create_tgt, WMI_VAP_CREATE_CMDID, 0},
1725 {ath_hal_reg_read_tgt, WMI_REG_READ_CMDID, 0},
1726 {ath_hal_reg_write_tgt, WMI_REG_WRITE_CMDID, 0},
1727 {handle_rc_state_change_cmd, WMI_RC_STATE_CHANGE_CMDID, 0},
1728 {handle_rc_rate_update_cmd, WMI_RC_RATE_UPDATE_CMDID, 0},
1729 {ath_ic_update_tgt, WMI_TARGET_IC_UPDATE_CMDID, 0},
1730 {ath_enable_aggr_tgt, WMI_TX_AGGR_ENABLE_CMDID, 0},
1731 {ath_detach_tgt, WMI_TGT_DETACH_CMDID, 0},
1732 {ath_node_update_tgt, WMI_NODE_UPDATE_CMDID, 0},
1733 {ath_int_stats_tgt, WMI_INT_STATS_CMDID, 0},
1734 {ath_tx_stats_tgt, WMI_TX_STATS_CMDID, 0},
1735 {ath_rx_stats_tgt, WMI_RX_STATS_CMDID, 0},
1736 {ath_rc_mask_tgt, WMI_BITRATE_MASK_CMDID, 0},
1743 static void htc_setup_comp(void)
1747 static A_UINT8 tgt_ServiceConnect(HTC_SERVICE *pService,
1748 HTC_ENDPOINT_ID eid,
1752 a_int32_t *pLengthOut)
1754 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)pService->ServiceCtx;
1756 switch(pService->ServiceID) {
1757 case WMI_CONTROL_SVC:
1758 sc->wmi_command_ep= eid;
1760 case WMI_BEACON_SVC:
1772 case WMI_DATA_VO_SVC:
1773 sc->data_VO_ep = eid;
1775 case WMI_DATA_VI_SVC:
1776 sc->data_VI_ep = eid;
1778 case WMI_DATA_BE_SVC:
1779 sc->data_BE_ep = eid;
1781 case WMI_DATA_BK_SVC:
1782 sc->data_BK_ep = eid;
1788 return HTC_SERVICE_SUCCESS;
1791 static void tgt_reg_service(struct ath_softc_tgt *sc, HTC_SERVICE *svc,
1792 int svcId, HTC_SERVICE_ProcessRecvMsg recvMsg)
1794 svc->ProcessRecvMsg = recvMsg;
1795 svc->ProcessSendBufferComplete = tgt_HTCSendCompleteHandler;
1796 svc->ProcessConnect = tgt_ServiceConnect;
1797 svc->MaxSvcMsgSize = 1600;
1798 svc->TrailerSpcCheckLimit = 0;
1799 svc->ServiceID = svcId;
1800 svc->ServiceCtx = sc;
1801 HTC_RegisterService(sc->tgt_htc_handle, svc);
1804 static void tgt_hif_htc_wmi_init(struct ath_softc_tgt *sc)
1806 HTC_CONFIG htc_conf;
1807 WMI_SVC_CONFIG wmiConfig;
1808 WMI_DISPATCH_TABLE *Magpie_Sys_Commands_Tbl;
1810 /* Init dynamic buf pool */
1811 sc->pool_handle = BUF_Pool_init(sc->sc_hdl);
1813 /* Init target-side HIF */
1814 sc->tgt_hif_handle = HIF_init(0);
1816 /* Init target-side HTC */
1817 htc_conf.HIFHandle = sc->tgt_hif_handle;
1818 htc_conf.CreditSize = 320;
1819 htc_conf.CreditNumber = ATH_TXBUF;
1820 htc_conf.OSHandle = sc->sc_hdl;
1821 htc_conf.PoolHandle = sc->pool_handle;
1822 sc->tgt_htc_handle = HTC_init(htc_setup_comp, &htc_conf);
1823 #if defined(PROJECT_MAGPIE)
1824 init_htc_handle = sc->tgt_htc_handle;
1827 tgt_reg_service(sc, &sc->htc_beacon_service, WMI_BEACON_SVC, tgt_HTCRecv_beaconhandler);
1828 tgt_reg_service(sc, &sc->htc_cab_service, WMI_CAB_SVC, tgt_HTCRecv_cabhandler);
1829 tgt_reg_service(sc, &sc->htc_uapsd_service, WMI_UAPSD_SVC, tgt_HTCRecv_uapsdhandler);
1830 tgt_reg_service(sc, &sc->htc_mgmt_service, WMI_MGMT_SVC, tgt_HTCRecv_mgmthandler);
1831 tgt_reg_service(sc, &sc->htc_data_BE_service, WMI_DATA_BE_SVC, tgt_HTCRecvMessageHandler);
1832 tgt_reg_service(sc, &sc->htc_data_BK_service, WMI_DATA_BK_SVC, tgt_HTCRecvMessageHandler);
1833 tgt_reg_service(sc, &sc->htc_data_VI_service, WMI_DATA_VI_SVC, tgt_HTCRecvMessageHandler);
1834 tgt_reg_service(sc, &sc->htc_data_VO_service, WMI_DATA_VO_SVC, tgt_HTCRecvMessageHandler);
1836 /* Init target-side WMI */
1837 Magpie_Sys_Commands_Tbl = (WMI_DISPATCH_TABLE *)adf_os_mem_alloc(sizeof(WMI_DISPATCH_TABLE));
1838 adf_os_mem_zero(Magpie_Sys_Commands_Tbl, sizeof(WMI_DISPATCH_TABLE));
1839 Magpie_Sys_Commands_Tbl->NumberOfEntries = WMI_DISPATCH_ENTRY_COUNT(Magpie_Sys_DispatchEntries);
1840 Magpie_Sys_Commands_Tbl->pTable = Magpie_Sys_DispatchEntries;
1842 adf_os_mem_zero(&wmiConfig, sizeof(WMI_SVC_CONFIG));
1843 wmiConfig.HtcHandle = sc->tgt_htc_handle;
1844 wmiConfig.PoolHandle = sc->pool_handle;
1845 wmiConfig.MaxCmdReplyEvts = ATH_WMI_MAX_CMD_REPLY;
1846 wmiConfig.MaxEventEvts = ATH_WMI_MAX_EVENTS;
1848 sc->tgt_wmi_handle = WMI_Init(&wmiConfig);
1849 Magpie_Sys_Commands_Tbl->pContext = sc;
1850 WMI_RegisterDispatchTable(sc->tgt_wmi_handle, Magpie_Sys_Commands_Tbl);
1852 HTC_NotifyTargetInserted(sc->tgt_htc_handle);
1854 /* Start HTC messages exchange */
1855 HTC_Ready(sc->tgt_htc_handle);
1858 a_int32_t ath_tgt_attach(a_uint32_t devid, struct ath_softc_tgt *sc, adf_os_device_t osdev)
1862 a_int32_t error = 0, i, flags = 0;
1865 adf_os_pci_config_read8(osdev, ATH_PCI_CACHE_LINE_SIZE, &csz);
1869 sc->sc_cachelsz = csz << 2;
1874 ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_rxtq, ath_tgt_rx_tasklet, sc);
1875 ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_txtq, owl_tgt_tx_tasklet, sc);
1876 ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_bmisstq, ath_bmiss_tasklet, sc);
1877 ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_fataltq, ath_fatal_tasklet, sc);
1879 flags |= AH_USE_EEPROM;
1880 ah = _ath_hal_attach_tgt(devid, sc, sc->sc_dev, flags, &status);
1887 tgt_hif_htc_wmi_init(sc);
1889 sc->sc_bhalq = HAL_NUM_TX_QUEUES - 1;
1891 ath_rate_setup(sc, IEEE80211_MODE_11NA);
1892 ath_rate_setup(sc, IEEE80211_MODE_11NG);
1894 sc->sc_rc = ath_rate_attach(sc);
1895 if (sc->sc_rc == NULL) {
1900 for (i=0; i < TARGET_NODE_MAX; i++) {
1901 sc->sc_sta[i].an_rcnode = adf_os_mem_alloc(sc->sc_rc->arc_space);
1904 error = ath_desc_alloc(sc);
1909 BUF_Pool_create_pool(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ath_numrxdescs, 1664);
1911 ath_tgt_txq_setup(sc);
1913 ah->ah_setInterrupts(ah, 0);
1923 static void tgt_hif_htc_wmi_shutdown(struct ath_softc_tgt *sc)
1925 HTC_NotifyTargetDetached(sc->tgt_htc_handle);
1927 WMI_Shutdown(sc->tgt_wmi_handle);
1928 HTC_Shutdown(sc->tgt_htc_handle);
1929 HIF_shutdown(sc->tgt_hif_handle);
1930 BUF_Pool_shutdown(sc->pool_handle);
1933 a_int32_t ath_detach(struct ath_softc_tgt *sc)
1935 tgt_hif_htc_wmi_shutdown(sc);