2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <adf_os_types.h>
37 #include <adf_os_pci.h>
38 #include <adf_os_dma.h>
39 #include <adf_os_timer.h>
40 #include <adf_os_lock.h>
41 #include <adf_os_io.h>
42 #include <adf_os_mem.h>
43 #include <adf_os_util.h>
44 #include <adf_os_stdtypes.h>
45 #include <adf_os_defer.h>
46 #include <adf_os_atomic.h>
49 #include <adf_net_wcmd.h>
50 #include <adf_os_irq.h>
52 #include <if_ath_pci.h>
54 #include "ieee80211_var.h"
55 #include "if_athrate.h"
56 #include "if_athvar.h"
60 static a_int32_t ath_numrxbufs = -1;
61 static a_int32_t ath_numrxdescs = -1;
63 #if defined(PROJECT_MAGPIE)
64 uint32_t *init_htc_handle = 0;
67 #define RX_ENDPOINT_ID 3
68 #define ATH_CABQ_HANDLING_THRESHOLD 9000
72 void owl_tgt_tx_tasklet(TQUEUE_ARG data);
73 static void ath_tgt_send_beacon(struct ath_softc_tgt *sc,adf_nbuf_t bc_hdr,adf_nbuf_t nbuf,HTC_ENDPOINT_ID EndPt);
74 static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen);
75 static void ath_hal_reg_rmw_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen);
76 extern struct ath_tx_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc, adf_nbuf_t skb, ath_data_hdr_t *dh);
77 extern void ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t mgt_hdr, adf_nbuf_t skb,HTC_ENDPOINT_ID EndPt);
78 extern HAL_BOOL ath_hal_wait(struct ath_hal *ah, a_uint32_t reg, a_uint32_t mask, a_uint32_t val);
79 extern void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq, owl_txq_state_t txqstate);
80 void owl_tgt_node_init(struct ath_node_target * an);
81 void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, struct ath_buf *bf);
82 void ath_tgt_tx_sched_nonaggr(struct ath_softc_tgt *sc,struct ath_buf * bf_host);
85 * Extend a 32 bit TSF to 64 bit, taking wrapping into account.
87 static u_int64_t ath_extend_tsf(struct ath_softc_tgt *sc, u_int32_t rstamp)
89 struct ath_hal *ah = sc->sc_ah;
94 tsf = ah->ah_getTsf64(ah);
95 tsf_low = tsf & 0xffffffff;
96 tsf64 = (tsf & ~0xffffffffULL) | rstamp;
98 if (rstamp > tsf_low && (rstamp - tsf_low > 0x10000000))
99 tsf64 -= 0x100000000ULL;
101 if (rstamp < tsf_low && (tsf_low - rstamp > 0x10000000))
102 tsf64 += 0x100000000ULL;
107 static a_int32_t ath_rate_setup(struct ath_softc_tgt *sc, a_uint32_t mode)
109 struct ath_hal *ah = sc->sc_ah;
110 const HAL_RATE_TABLE *rt;
113 case IEEE80211_MODE_11NA:
114 sc->sc_rates[mode] = ah->ah_getRateTable(ah, HAL_MODE_11NA);
116 case IEEE80211_MODE_11NG:
117 sc->sc_rates[mode] = ah->ah_getRateTable(ah, HAL_MODE_11NG);
122 rt = sc->sc_rates[mode];
129 static void ath_setcurmode(struct ath_softc_tgt *sc,
130 enum ieee80211_phymode mode)
132 const HAL_RATE_TABLE *rt;
135 adf_os_mem_set(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
137 rt = sc->sc_rates[mode];
138 adf_os_assert(rt != NULL);
140 for (i = 0; i < rt->rateCount; i++) {
141 sc->sc_rixmap[rt->info[i].rateCode] = i;
144 sc->sc_currates = rt;
145 sc->sc_curmode = mode;
146 sc->sc_protrix = ((mode == IEEE80211_MODE_11NG) ? 3 : 0);
150 void wmi_event(wmi_handle_t handle, WMI_EVENT_ID evt_id,
151 void *buffer, a_int32_t Length)
153 adf_nbuf_t netbuf = ADF_NBUF_NULL;
156 netbuf = WMI_AllocEvent(handle, WMI_EVT_CLASS_CMD_EVENT,
157 sizeof(WMI_CMD_HDR) + Length);
159 if (netbuf == ADF_NBUF_NULL) {
160 adf_os_print("Buf null\n");
164 if (buffer != NULL && Length != 0 && Length < WMI_SVC_MAX_BUFFERED_EVENT_SIZE) {
165 pData = adf_nbuf_put_tail(netbuf, Length);
166 adf_os_mem_copy(pData, buffer, Length);
169 WMI_SendEvent(handle, netbuf, evt_id, 0, Length);
172 void wmi_cmd_rsp(void *pContext, WMI_COMMAND_ID cmd_id, A_UINT16 SeqNo,
173 void *buffer, a_int32_t Length)
175 adf_nbuf_t netbuf = ADF_NBUF_NULL;
178 netbuf = WMI_AllocEvent(pContext, WMI_EVT_CLASS_CMD_REPLY,
179 sizeof(WMI_CMD_HDR) + Length);
181 if (netbuf == ADF_NBUF_NULL) {
186 if (Length != 0 && buffer != NULL) {
187 pData = (A_UINT8 *)adf_nbuf_put_tail(netbuf, Length);
188 adf_os_mem_copy(pData, buffer, Length);
191 WMI_SendEvent(pContext, netbuf, cmd_id, SeqNo, Length);
194 static void ath_node_vdelete_tgt(struct ath_softc_tgt *sc, a_uint8_t vap_index)
198 for (i = 0; i < TARGET_NODE_MAX; i++) {
199 if(sc->sc_sta[i].ni.ni_vapindex == vap_index)
200 sc->sc_sta[i].an_valid = 0;
204 a_uint8_t ath_get_minrateidx(struct ath_softc_tgt *sc, struct ath_vap_target *avp)
206 if (sc->sc_curmode == IEEE80211_MODE_11NG)
207 return avp->av_minrateidx[0];
208 else if (sc->sc_curmode == IEEE80211_MODE_11NA)
209 return avp->av_minrateidx[1];
218 static adf_nbuf_t ath_alloc_skb_align(struct ath_softc_tgt *sc,
219 a_uint32_t size, a_uint32_t align)
223 skb = BUF_Pool_alloc_buf_align(sc->pool_handle, POOL_ID_WLAN_RX_BUF,
224 RX_HEADER_SPACE, align);
228 static a_int32_t ath_rxdesc_init(struct ath_softc_tgt *sc, struct ath_rx_desc *ds)
230 struct ath_hal *ah = sc->sc_ah;
231 struct ath_rx_desc *ds_held;
235 if (!sc->sc_rxdesc_held) {
236 sc->sc_rxdesc_held = ds;
240 ds_held = sc->sc_rxdesc_held;
241 sc->sc_rxdesc_held = ds;
244 if (ds->ds_nbuf == ADF_NBUF_NULL) {
245 ds->ds_nbuf = ath_alloc_skb_align(sc, sc->sc_rxbufsize, sc->sc_cachelsz);
246 if (ds->ds_nbuf == ADF_NBUF_NULL) {
247 sc->sc_rxdesc_held = ds;
248 sc->sc_rx_stats.ast_rx_nobuf++;
251 adf_nbuf_map(sc->sc_dev, ds->ds_dmap, ds->ds_nbuf, ADF_OS_DMA_FROM_DEVICE);
252 adf_nbuf_dmamap_info(ds->ds_dmap, &ds->ds_dmap_info);
253 ds->ds_data = ds->ds_dmap_info.dma_segs[0].paddr;
257 adf_nbuf_peek_header(ds->ds_nbuf, &anbdata, &anblen);
259 ah->ah_setupRxDesc(ds, adf_nbuf_tailroom(ds->ds_nbuf), 0);
261 if (sc->sc_rxlink == NULL) {
262 ah->ah_setRxDP(ah, ds->ds_daddr);
265 *sc->sc_rxlink = ds->ds_daddr;
267 sc->sc_rxlink = &ds->ds_link;
268 ah->ah_enableReceive(ah);
273 static void ath_rx_complete(struct ath_softc_tgt *sc, adf_nbuf_t buf)
275 struct ath_rx_desc *ds;
277 adf_nbuf_queue_t nbuf_head;
279 adf_nbuf_split_to_frag(buf, &nbuf_head);
280 ds = asf_tailq_first(&sc->sc_rxdesc_idle);
283 struct ath_rx_desc *ds_tmp;
284 buf_tmp = adf_nbuf_queue_remove(&nbuf_head);
286 if (buf_tmp == NULL) {
290 BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, buf_tmp);
293 ds = asf_tailq_next(ds, ds_list);
295 ath_rxdesc_init(sc, ds_tmp);
297 asf_tailq_remove(&sc->sc_rxdesc_idle, ds_tmp, ds_list);
298 asf_tailq_insert_tail(&sc->sc_rxdesc, ds_tmp, ds_list);
302 static void tgt_HTCSendCompleteHandler(HTC_ENDPOINT_ID Endpt, adf_nbuf_t buf, void *ServiceCtx)
304 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
306 if (Endpt == RX_ENDPOINT_ID) {
307 sc->sc_rx_stats.ast_rx_done++;
308 ath_rx_complete(sc, buf);
312 static void ath_uapsd_processtriggers(struct ath_softc_tgt *sc)
314 struct ath_hal *ah = sc->sc_ah;
315 struct ath_rx_buf *bf = NULL;
316 struct ath_rx_desc *ds, *ds_head, *ds_tail, *ds_tmp;
319 a_uint16_t frame_len = 0;
322 #define PA2DESC(_sc, _pa) \
323 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
324 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
326 tsf = ah->ah_getTsf64(ah);
327 bf = asf_tailq_first(&sc->sc_rxbuf);
329 ds = asf_tailq_first(&sc->sc_rxdesc);
335 if (cnt == ath_numrxbufs - 1) {
336 adf_os_print("VERY LONG PACKET!!!!!\n");
340 struct ath_rx_desc *ds_rmv;
341 adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE);
343 ds_tmp = asf_tailq_next(ds_tmp, ds_list);
345 if (ds_tmp == NULL) {
346 adf_os_print("ds_tmp is NULL\n");
350 BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ds_rmv->ds_nbuf);
351 ds_rmv->ds_nbuf = ADF_NBUF_NULL;
353 if (ath_rxdesc_init(sc, ds_rmv) == 0) {
354 asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
355 asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list);
358 asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
359 asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list);
362 if (ds_rmv == ds_tail) {
369 if (ds->ds_link == 0) {
373 if (bf->bf_status & ATH_BUFSTATUS_DONE) {
377 retval = ah->ah_procRxDescFast(ah, ds, ds->ds_daddr,
378 PA2DESC(sc, ds->ds_link), &bf->bf_rx_status);
379 if (HAL_EINPROGRESS == retval) {
383 if (adf_nbuf_len(ds->ds_nbuf) == 0) {
384 adf_nbuf_put_tail(ds->ds_nbuf, bf->bf_rx_status.rs_datalen);
387 frame_len += bf->bf_rx_status.rs_datalen;
389 if (bf->bf_rx_status.rs_more == 0) {
390 adf_nbuf_queue_t nbuf_head;
391 adf_nbuf_queue_init(&nbuf_head);
396 ds = asf_tailq_next(ds, ds_list);
399 ds_head = asf_tailq_next(ds_tail, ds_list);
402 struct ath_rx_desc *ds_rmv;
404 adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE);
405 adf_nbuf_queue_add(&nbuf_head, ds_tmp->ds_nbuf);
406 ds_tmp->ds_nbuf = ADF_NBUF_NULL;
409 ds_tmp = asf_tailq_next(ds_tmp, ds_list);
410 if (ds_tmp == NULL) {
414 if (ath_rxdesc_init(sc, ds_rmv) == 0) {
415 asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
416 asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list);
418 asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
419 asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list);
422 if (ds_rmv == ds_tail) {
428 bf->bf_rx_status.rs_datalen = frame_len;
431 bf->bf_skb = adf_nbuf_create_frm_frag(&nbuf_head);
433 bf->bf_status |= ATH_BUFSTATUS_DONE;
435 bf = (struct ath_rx_buf *)asf_tailq_next(bf, bf_list);
438 ds = asf_tailq_next(ds, ds_list);
445 static a_int32_t ath_startrecv(struct ath_softc_tgt *sc)
447 struct ath_hal *ah = sc->sc_ah;
448 struct ath_rx_desc *ds;
450 sc->sc_rxbufsize = 1024+512+128;
451 sc->sc_rxlink = NULL;
453 sc->sc_rxdesc_held = NULL;
455 asf_tailq_foreach(ds, &sc->sc_rxdesc, ds_list) {
456 a_int32_t error = ath_rxdesc_init(sc, ds);
462 ds = asf_tailq_first(&sc->sc_rxdesc);
463 ah->ah_setRxDP(ah, ds->ds_daddr);
468 static void ath_tgt_rx_tasklet(TQUEUE_ARG data)
470 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
471 struct ath_rx_buf *bf = NULL;
472 struct ath_hal *ah = sc->sc_ah;
473 struct rx_frame_header *rxhdr;
474 struct ath_rx_status *rxstats;
475 adf_nbuf_t skb = ADF_NBUF_NULL;
478 bf = asf_tailq_first(&sc->sc_rxbuf);
483 if (!(bf->bf_status & ATH_BUFSTATUS_DONE)) {
492 asf_tailq_remove(&sc->sc_rxbuf, bf, bf_list);
496 rxhdr = (struct rx_frame_header *)adf_nbuf_push_head(skb,
497 sizeof(struct rx_frame_header));
498 rxstats = (struct ath_rx_status *)(&rxhdr->rx_stats[0]);
499 adf_os_mem_copy(rxstats, &(bf->bf_rx_status),
500 sizeof(struct ath_rx_status));
502 rxstats->rs_tstamp = ath_extend_tsf(sc, (u_int32_t)rxstats->rs_tstamp);
504 HTC_SendMsg(sc->tgt_htc_handle, RX_ENDPOINT_ID, skb);
505 sc->sc_rx_stats.ast_rx_send++;
507 bf->bf_status &= ~ATH_BUFSTATUS_DONE;
508 asf_tailq_insert_tail(&sc->sc_rxbuf, bf, bf_list);
512 sc->sc_imask |= HAL_INT_RX;
513 ah->ah_setInterrupts(ah, sc->sc_imask);
516 /*******************/
517 /* Beacon Handling */
518 /*******************/
521 * Setup the beacon frame for transmit.
522 * FIXME: Short Preamble.
524 static void ath_beacon_setup(struct ath_softc_tgt *sc,
525 struct ath_tx_buf *bf,
526 struct ath_vap_target *avp)
528 adf_nbuf_t skb = bf->bf_skb;
529 struct ath_hal *ah = sc->sc_ah;
530 struct ath_tx_desc *ds;
532 const HAL_RATE_TABLE *rt;
534 HAL_11N_RATE_SERIES series[4] = {{ 0 }};
536 flags = HAL_TXDESC_NOACK;
540 ds->ds_data = bf->bf_dmamap_info.dma_segs[0].paddr;
542 rix = ath_get_minrateidx(sc, avp);
543 rt = sc->sc_currates;
544 rate = rt->info[rix].rateCode;
546 ah->ah_setupTxDesc(ds
547 , adf_nbuf_len(skb) + IEEE80211_CRC_LEN
548 , sizeof(struct ieee80211_frame)
549 , HAL_PKT_TYPE_BEACON
552 , HAL_TXKEYIX_INVALID
558 , asf_roundup(adf_nbuf_len(skb), 4)
564 series[0].Rate = rate;
565 series[0].ChSel = sc->sc_ic.ic_tx_chainmask;
566 series[0].RateFlags = 0;
567 ah->ah_set11nRateScenario(ds, 0, 0, series, 4, 0);
570 static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr,
571 adf_nbuf_t nbuf, HTC_ENDPOINT_ID EndPt)
573 struct ath_hal *ah = sc->sc_ah;
574 struct ath_tx_buf *bf;
575 a_uint8_t vap_index, *anbdata;
576 ath_beacon_hdr_t *bhdr;
577 struct ieee80211vap_target *vap;
579 struct ieee80211_frame *wh;
582 adf_nbuf_peek_header(nbuf, &anbdata, &anblen);
583 bhdr = (ath_beacon_hdr_t *)anbdata;
585 adf_os_print("found bc_hdr! 0x%x\n", bc_hdr);
588 vap_index = bhdr->vap_index;
589 adf_os_assert(vap_index < TARGET_VAP_MAX);
590 vap = &sc->sc_vap[vap_index].av_vap;
592 wh = (struct ieee80211_frame *)adf_nbuf_pull_head(nbuf,
593 sizeof(ath_beacon_hdr_t));
595 bf = sc->sc_vap[vap_index].av_bcbuf;
597 bf->bf_endpt = EndPt;
600 adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE);
601 adf_nbuf_push_head(bf->bf_skb, sizeof(ath_beacon_hdr_t));
602 ath_free_tx_skb(sc->tgt_htc_handle, bf->bf_endpt, bf->bf_skb);
607 adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, nbuf, ADF_OS_DMA_TO_DEVICE);
608 adf_nbuf_dmamap_info(bf->bf_dmamap,&bf->bf_dmamap_info);
610 ath_beacon_setup(sc, bf, &sc->sc_vap[vap_index]);
611 ah->ah_stopTxDma(ah, sc->sc_bhalq);
612 ah->ah_setTxDP(ah, sc->sc_bhalq, ATH_BUF_GET_DESC_PHY_ADDR(bf));
613 ah->ah_startTxDma(ah, sc->sc_bhalq);
620 static void ath_tx_stopdma(struct ath_softc_tgt *sc, struct ath_txq *txq)
622 struct ath_hal *ah = sc->sc_ah;
624 ah->ah_stopTxDma(ah, txq->axq_qnum);
627 static void owltgt_txq_drain(struct ath_softc_tgt *sc, struct ath_txq *txq)
629 owltgt_tx_processq(sc, txq, OWL_TXQ_STOPPED);
632 static void ath_tx_draintxq(struct ath_softc_tgt *sc, struct ath_txq *txq)
634 owltgt_txq_drain(sc, txq);
637 static void ath_draintxq(struct ath_softc_tgt *sc, HAL_BOOL drain_softq)
639 struct ath_hal *ah = sc->sc_ah;
641 struct ath_txq *txq = NULL;
642 struct ath_atx_tid *tid = NULL;
644 ath_tx_status_clear(sc);
645 sc->sc_tx_draining = 1;
647 ah->ah_stopTxDma(ah, sc->sc_bhalq);
649 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
650 if (ATH_TXQ_SETUP(sc, i))
651 ath_tx_stopdma(sc, ATH_TXQ(sc, i));
653 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
654 if (ATH_TXQ_SETUP(sc, i)) {
655 owltgt_tx_processq(sc, ATH_TXQ(sc,i), OWL_TXQ_STOPPED);
658 while (!asf_tailq_empty(&txq->axq_tidq)){
659 TAILQ_DEQ(&txq->axq_tidq, tid, tid_qelem);
662 tid->sched = AH_FALSE;
663 ath_tgt_tid_drain(sc,tid);
667 sc->sc_tx_draining = 0;
670 static void ath_tgt_txq_setup(struct ath_softc_tgt *sc)
677 for (qnum=0;qnum<HAL_NUM_TX_QUEUES;qnum++) {
678 txq= &sc->sc_txq[qnum];
679 txq->axq_qnum = qnum;
680 txq->axq_link = NULL;
681 asf_tailq_init(&txq->axq_q);
683 txq->axq_linkbuf = NULL;
684 asf_tailq_init(&txq->axq_tidq);
685 sc->sc_txqsetup |= 1<<qnum;
688 sc->sc_uapsdq = &sc->sc_txq[UAPSDQ_NUM];
689 sc->sc_cabq = &sc->sc_txq[CABQ_NUM];
691 sc->sc_ac2q[WME_AC_BE] = &sc->sc_txq[0];
692 sc->sc_ac2q[WME_AC_BK] = &sc->sc_txq[1];
693 sc->sc_ac2q[WME_AC_VI] = &sc->sc_txq[2];
694 sc->sc_ac2q[WME_AC_VO] = &sc->sc_txq[3];
700 static void tgt_HTCRecv_beaconhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
701 adf_nbuf_t buf, void *ServiceCtx)
703 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
705 ath_tgt_send_beacon(sc, hdr_buf, buf, EndPt);
708 static void tgt_HTCRecv_uapsdhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
709 adf_nbuf_t buf, void *ServiceCtx)
713 static void tgt_HTCRecv_mgmthandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
714 adf_nbuf_t buf, void *ServiceCtx)
716 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
718 ath_tgt_send_mgt(sc,hdr_buf,buf,EndPt);
721 static void tgt_HTCRecvMessageHandler(HTC_ENDPOINT_ID EndPt,
722 adf_nbuf_t hdr_buf, adf_nbuf_t buf,
725 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
726 struct ath_tx_buf *bf;
730 struct ath_node_target *an;
731 struct ath_atx_tid *tid;
734 adf_nbuf_peek_header(buf, &data, &len);
735 adf_nbuf_pull_head(buf, sizeof(ath_data_hdr_t));
737 adf_nbuf_peek_header(hdr_buf, &data, &len);
740 adf_os_assert(len >= sizeof(ath_data_hdr_t));
741 dh = (ath_data_hdr_t *)data;
743 an = &sc->sc_sta[dh->ni_index];
744 tid = ATH_AN_2_TID(an, dh->tidno);
746 sc->sc_tx_stats.tx_tgt++;
748 bf = ath_tgt_tx_prepare(sc, buf, dh);
750 ath_free_tx_skb(sc->tgt_htc_handle,EndPt,buf);
754 bf->bf_endpt = EndPt;
755 bf->bf_cookie = dh->cookie;
757 if (tid->flag & TID_AGGR_ENABLED)
758 ath_tgt_handle_aggr(sc, bf);
760 ath_tgt_handle_normal(sc, bf);
763 static void tgt_HTCRecv_cabhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
764 adf_nbuf_t buf, void *ServiceCtx)
766 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
767 struct ath_hal *ah = sc->sc_ah;
771 #ifdef ATH_ENABLE_CABQ
772 tsf = ah->ah_getTsf64(ah);
773 tmp = tsf - sc->sc_swba_tsf;
775 if ( tmp > ATH_CABQ_HANDLING_THRESHOLD ) {
776 HTC_ReturnBuffers(sc->tgt_htc_handle, EndPt, buf);
780 tgt_HTCRecvMessageHandler(EndPt, hdr_buf, buf, ServiceCtx);
784 /***********************/
785 /* Descriptor Handling */
786 /***********************/
788 static a_int32_t ath_descdma_setup(struct ath_softc_tgt *sc,
789 struct ath_descdma *dd, ath_bufhead *head,
790 const char *name, a_int32_t nbuf, a_int32_t ndesc,
791 a_uint32_t bfSize, a_uint32_t descSize)
793 #define DS2PHYS(_dd, _ds) \
794 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
798 a_int32_t i, bsize, error;
803 dd->dd_desc_len = descSize * nbuf * ndesc;
805 dd->dd_desc = adf_os_dmamem_alloc(sc->sc_dev,
806 dd->dd_desc_len, 1, &dd->dd_desc_dmamap);
807 dd->dd_desc_paddr = adf_os_dmamem_map2addr(dd->dd_desc_dmamap);
808 if (dd->dd_desc == NULL) {
814 bsize = bfSize * nbuf;
815 bf = adf_os_mem_alloc(bsize);
820 adf_os_mem_set(bf, 0, bsize);
823 bf_addr = (a_uint8_t *)bf;
824 ds_addr = (a_uint8_t *)ds;
826 asf_tailq_init(head);
828 for (i = 0; i < nbuf; i++) {
831 if (adf_nbuf_dmamap_create( sc->sc_dev, &bf->bf_dmamap) != A_STATUS_OK) {
835 bf->bf_desc = bf->bf_descarr = bf->bf_lastds = ds;
836 for (j = 0; j < ndesc; j++)
837 ATH_BUF_SET_DESC_PHY_ADDR_WITH_IDX(bf, j, (ds_addr + (j*descSize)));
839 ATH_BUF_SET_DESC_PHY_ADDR(bf, ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, 0));
841 adf_nbuf_queue_init(&bf->bf_skbhead);
842 asf_tailq_insert_tail(head, bf, bf_list);
845 ds_addr += (ndesc * descSize);
846 bf = (struct ath_buf *)bf_addr;
847 ds = (struct ath_desc *)ds_addr;
852 adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len,
853 1, dd->dd_desc, dd->dd_desc_dmamap);
855 adf_os_mem_set(dd, 0, sizeof(*dd));
862 static void ath_descdma_cleanup(struct ath_softc_tgt *sc,
863 struct ath_descdma *dd,
864 ath_bufhead *head, a_int32_t dir)
867 struct ieee80211_node_target *ni;
869 asf_tailq_foreach(bf, head, bf_list) {
870 if (adf_nbuf_queue_len(&bf->bf_skbhead) != 0) {
871 adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, dir);
872 while(adf_nbuf_queue_len(&bf->bf_skbhead) != 0) {
874 adf_nbuf_queue_remove(&bf->bf_skbhead));
877 } else if (bf->bf_skb != NULL) {
878 adf_nbuf_unmap(sc->sc_dev,bf->bf_dmamap, dir);
879 ath_free_rx_skb(sc, bf->bf_skb);
883 adf_nbuf_dmamap_destroy(sc->sc_dev, bf->bf_dmamap);
889 adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len,
890 1, dd->dd_desc, dd->dd_desc_dmamap);
892 asf_tailq_init(head);
893 adf_os_mem_free(dd->dd_bufptr);
894 adf_os_mem_set(dd, 0, sizeof(*dd));
897 static a_int32_t ath_desc_alloc(struct ath_softc_tgt *sc)
899 #define DS2PHYS(_dd, _ds) \
900 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
903 struct ath_tx_buf *bf;
905 if(ath_numrxbufs == -1)
906 ath_numrxbufs = ATH_RXBUF;
908 if (ath_numrxdescs == -1)
909 ath_numrxdescs = ATH_RXDESC;
911 error = ath_descdma_setup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
912 "rx", ath_numrxdescs, 1,
913 sizeof(struct ath_rx_buf),
914 sizeof(struct ath_rx_desc));
919 struct ath_descdma *dd = &sc->sc_rxdma;
920 struct ath_rx_desc *ds = (struct ath_rx_desc *)dd->dd_desc;
921 struct ath_rx_desc *ds_prev = NULL;
923 asf_tailq_init(&sc->sc_rxdesc);
924 asf_tailq_init(&sc->sc_rxdesc_idle);
926 for (i = 0; i < ath_numrxdescs; i++, ds++) {
928 if (ds->ds_nbuf != ADF_NBUF_NULL) {
929 ds->ds_nbuf = ADF_NBUF_NULL;
932 if (adf_nbuf_dmamap_create(sc->sc_dev, &ds->ds_dmap) != A_STATUS_OK) {
936 ds->ds_daddr = DS2PHYS(&sc->sc_rxdma, ds);
939 ds_prev->ds_link = ds->ds_daddr;
945 asf_tailq_insert_tail(&sc->sc_rxdesc, ds, ds_list);
948 error = ath_descdma_setup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
949 "tx", ATH_TXBUF + 1, ATH_TXDESC,
950 sizeof(struct ath_tx_buf),
951 sizeof(struct ath_tx_desc));
953 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
954 ADF_OS_DMA_FROM_DEVICE);
958 error = ath_descdma_setup(sc, &sc->sc_bdma, (ath_bufhead *)&sc->sc_bbuf,
959 "beacon", ATH_BCBUF, 1,
960 sizeof(struct ath_tx_buf),
961 sizeof(struct ath_tx_desc));
963 ath_descdma_cleanup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
964 ADF_OS_DMA_TO_DEVICE);
965 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
966 ADF_OS_DMA_FROM_DEVICE);
970 bf = asf_tailq_first(&sc->sc_txbuf);
971 bf->bf_isaggr = bf->bf_isretried = bf->bf_retries = 0;
972 asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
974 sc->sc_txbuf_held = bf;
981 static void ath_desc_free(struct ath_softc_tgt *sc)
983 asf_tailq_insert_tail(&sc->sc_txbuf, sc->sc_txbuf_held, bf_list);
985 sc->sc_txbuf_held = NULL;
987 if (sc->sc_txdma.dd_desc_len != 0)
988 ath_descdma_cleanup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
989 ADF_OS_DMA_TO_DEVICE);
990 if (sc->sc_rxdma.dd_desc_len != 0)
991 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
992 ADF_OS_DMA_FROM_DEVICE);
995 /**********************/
996 /* Interrupt Handling */
997 /**********************/
999 adf_os_irq_resp_t ath_intr(adf_drv_handle_t hdl)
1001 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)hdl;
1002 struct ath_hal *ah = sc->sc_ah;
1006 return ADF_OS_IRQ_NONE;
1008 if (!ah->ah_isInterruptPending(ah))
1009 return ADF_OS_IRQ_NONE;
1011 ah->ah_getPendingInterrupts(ah, &status);
1013 status &= sc->sc_imask;
1015 if (status & HAL_INT_FATAL) {
1016 ah->ah_setInterrupts(ah, 0);
1017 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_fataltq);
1019 if (status & HAL_INT_SWBA) {
1020 WMI_SWBA_EVENT swbaEvt;
1021 struct ath_txq *txq = ATH_TXQ(sc, 8);
1023 swbaEvt.tsf = ah->ah_getTsf64(ah);
1024 swbaEvt.beaconPendingCount = ah->ah_numTxPending(ah, sc->sc_bhalq);
1025 sc->sc_swba_tsf = ah->ah_getTsf64(ah);
1027 wmi_event(sc->tgt_wmi_handle,
1030 sizeof(WMI_SWBA_EVENT));
1032 ath_tx_draintxq(sc, txq);
1035 if (status & HAL_INT_RXORN)
1036 sc->sc_int_stats.ast_rxorn++;
1038 if (status & HAL_INT_RXEOL)
1039 sc->sc_int_stats.ast_rxeol++;
1041 if (status & (HAL_INT_RX | HAL_INT_RXEOL | HAL_INT_RXORN)) {
1042 if (status & HAL_INT_RX)
1043 sc->sc_int_stats.ast_rx++;
1045 ath_uapsd_processtriggers(sc);
1047 sc->sc_imask &= ~HAL_INT_RX;
1048 ah->ah_setInterrupts(ah, sc->sc_imask);
1050 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_rxtq);
1053 if (status & HAL_INT_TXURN) {
1054 sc->sc_int_stats.ast_txurn++;
1055 ah->ah_updateTxTrigLevel(ah, AH_TRUE);
1058 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_txtq);
1060 if (status & HAL_INT_BMISS) {
1061 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_bmisstq);
1064 if (status & HAL_INT_GTT)
1065 sc->sc_int_stats.ast_txto++;
1067 if (status & HAL_INT_CST)
1068 sc->sc_int_stats.ast_cst++;
1071 return ADF_OS_IRQ_HANDLED;
1074 static void ath_fatal_tasklet(TQUEUE_ARG data )
1076 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
1078 wmi_event(sc->tgt_wmi_handle, WMI_FATAL_EVENTID, NULL, 0);
1081 static void ath_bmiss_tasklet(TQUEUE_ARG data)
1083 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
1085 wmi_event(sc->tgt_wmi_handle, WMI_BMISS_EVENTID, NULL, 0);
1092 static void ath_enable_intr_tgt(void *Context, A_UINT16 Command,
1093 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1095 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1096 struct ath_hal *ah = sc->sc_ah;
1100 intr = (*(a_uint32_t *)data);
1102 intr = adf_os_ntohl(intr);
1104 if (intr & HAL_INT_SWBA) {
1105 sc->sc_imask |= HAL_INT_SWBA;
1107 sc->sc_imask &= ~HAL_INT_SWBA;
1110 if (intr & HAL_INT_BMISS) {
1111 sc->sc_imask |= HAL_INT_BMISS;
1114 ah->ah_setInterrupts(ah, sc->sc_imask);
1115 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
1118 static void ath_init_tgt(void *Context, A_UINT16 Command,
1119 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1121 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1122 struct ath_hal *ah = sc->sc_ah;
1124 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
1125 | HAL_INT_RXEOL | HAL_INT_RXORN
1126 | HAL_INT_FATAL | HAL_INT_GLOBAL;
1128 sc->sc_imask |= HAL_INT_GTT;
1130 if (ath_hal_getcapability(ah, HAL_CAP_HT))
1131 sc->sc_imask |= HAL_INT_CST;
1133 adf_os_setup_intr(sc->sc_dev, ath_intr);
1134 ah->ah_setInterrupts(ah, sc->sc_imask);
1136 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1139 static void ath_int_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1140 A_UINT8 *data, a_int32_t datalen)
1142 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1144 struct fusion_stats {
1146 a_uint32_t ast_rxorn;
1147 a_uint32_t ast_rxeol;
1148 a_uint32_t ast_txurn;
1149 a_uint32_t ast_txto;
1153 struct fusion_stats stats;
1155 stats.ast_rx = sc->sc_int_stats.ast_rx;
1156 stats.ast_rxorn = sc->sc_int_stats.ast_rxorn;
1157 stats.ast_rxeol = sc->sc_int_stats.ast_rxeol;
1158 stats.ast_txurn = sc->sc_int_stats.ast_txurn;
1159 stats.ast_txto = sc->sc_int_stats.ast_txto;
1160 stats.ast_cst = sc->sc_int_stats.ast_cst;
1162 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1165 static void ath_tx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1166 A_UINT8 *data, a_int32_t datalen)
1168 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1170 struct fusion_stats {
1171 a_uint32_t ast_tx_xretries;
1172 a_uint32_t ast_tx_fifoerr;
1173 a_uint32_t ast_tx_filtered;
1174 a_uint32_t ast_tx_timer_exp;
1175 a_uint32_t ast_tx_shortretry;
1176 a_uint32_t ast_tx_longretry;
1178 a_uint32_t tx_qnull;
1179 a_uint32_t tx_noskbs;
1180 a_uint32_t tx_nobufs;
1183 struct fusion_stats stats;
1185 stats.ast_tx_xretries = sc->sc_tx_stats.ast_tx_xretries;
1186 stats.ast_tx_fifoerr = sc->sc_tx_stats.ast_tx_fifoerr;
1187 stats.ast_tx_filtered = sc->sc_tx_stats.ast_tx_filtered;
1188 stats.ast_tx_timer_exp = sc->sc_tx_stats.ast_tx_timer_exp;
1189 stats.ast_tx_shortretry = sc->sc_tx_stats.ast_tx_shortretry;
1190 stats.ast_tx_longretry = sc->sc_tx_stats.ast_tx_longretry;
1191 stats.tx_qnull = sc->sc_tx_stats.tx_qnull;
1192 stats.tx_noskbs = sc->sc_tx_stats.tx_noskbs;
1193 stats.tx_nobufs = sc->sc_tx_stats.tx_nobufs;
1195 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1198 static void ath_rx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1199 A_UINT8 *data, a_int32_t datalen)
1201 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1203 struct fusion_stats {
1204 a_uint32_t ast_rx_nobuf;
1205 a_uint32_t ast_rx_send;
1206 a_uint32_t ast_rx_done;
1209 struct fusion_stats stats;
1211 stats.ast_rx_nobuf = sc->sc_rx_stats.ast_rx_nobuf;
1212 stats.ast_rx_send = sc->sc_rx_stats.ast_rx_send;
1213 stats.ast_rx_done = sc->sc_rx_stats.ast_rx_done;
1215 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1218 static void ath_get_tgt_version(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1219 A_UINT8 *data, a_int32_t datalen)
1221 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1222 struct wmi_fw_version ver;
1224 ver.major = ATH_VERSION_MAJOR;
1225 ver.minor = ATH_VERSION_MINOR;
1227 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &ver, sizeof(ver));
1230 static void ath_enable_aggr_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1231 A_UINT8 *data, a_int32_t datalen)
1233 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1234 struct ath_aggr_info *aggr = (struct ath_aggr_info *)data;
1235 a_uint8_t nodeindex = aggr->nodeindex;
1236 a_uint8_t tidno = aggr->tidno;
1237 struct ath_node_target *an = NULL ;
1238 struct ath_atx_tid *tid = NULL;
1240 if (nodeindex >= TARGET_NODE_MAX) {
1244 an = &sc->sc_sta[nodeindex];
1245 if (!an->an_valid) {
1249 if (tidno >= WME_NUM_TID) {
1250 adf_os_print("[%s] enable_aggr with invalid tid %d(node = %d)\n",
1251 __FUNCTION__, tidno, nodeindex);
1255 tid = ATH_AN_2_TID(an, tidno);
1257 if (aggr->aggr_enable) {
1258 tid->flag |= TID_AGGR_ENABLED;
1259 } else if ( tid->flag & TID_AGGR_ENABLED ) {
1260 tid->flag &= ~TID_AGGR_ENABLED;
1261 ath_tgt_tx_cleanup(sc, an, tid, 1);
1264 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1267 static void ath_ic_update_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1268 A_UINT8 *data, a_int32_t datalen)
1270 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1271 struct ieee80211com_target *ic = (struct ieee80211com_target * )data;
1272 struct ieee80211com_target *ictgt = &sc->sc_ic ;
1274 adf_os_mem_copy(ictgt, ic, sizeof(struct ieee80211com_target));
1276 ictgt->ic_ampdu_limit = adf_os_ntohl(ic->ic_ampdu_limit);
1278 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1281 static void ath_vap_create_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1282 A_UINT8 *data, a_int32_t datalen)
1284 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1285 struct ieee80211vap_target *vap;
1286 a_uint8_t vap_index;
1288 vap = (struct ieee80211vap_target *)data;
1290 vap->iv_rtsthreshold = adf_os_ntohs(vap->iv_rtsthreshold);
1291 vap->iv_opmode = adf_os_ntohl(vap->iv_opmode);
1293 vap_index = vap->iv_vapindex;
1295 adf_os_assert(sc->sc_vap[vap_index].av_valid == 0);
1297 adf_os_mem_copy(&(sc->sc_vap[vap_index].av_vap), vap,
1300 sc->sc_vap[vap_index].av_bcbuf = asf_tailq_first(&(sc->sc_bbuf));
1301 sc->sc_vap[vap_index].av_valid = 1;
1303 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1306 static void ath_node_create_tgt(void *Context, A_UINT16 Command,
1307 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1309 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1310 struct ieee80211_node_target *node;
1311 a_uint8_t vap_index;
1312 a_uint8_t node_index;
1314 node = (struct ieee80211_node_target *)data;
1316 node_index = node->ni_nodeindex;
1318 node->ni_htcap = adf_os_ntohs(node->ni_htcap);
1319 node->ni_flags = adf_os_ntohs(node->ni_flags);
1320 node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu);
1322 adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node,
1325 vap_index = sc->sc_sta[node_index].ni.ni_vapindex;
1326 sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap);
1327 if(sc->sc_sta[node_index].ni.ni_is_vapnode == 1)
1328 sc->sc_vap[vap_index].av_vap.iv_nodeindex = node_index;
1330 sc->sc_sta[node_index].an_valid = 1;
1331 sc->sc_sta[node_index].ni.ni_txseqmgmt = 0;
1332 sc->sc_sta[node_index].ni.ni_iv16 = 0;
1333 sc->sc_sta[node_index].ni.ni_iv32 = 0;
1335 owl_tgt_node_init(&sc->sc_sta[node_index]);
1337 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1340 static void ath_node_cleanup_tgt(void *Context, A_UINT16 Command,
1341 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1343 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1344 a_uint8_t node_index;
1345 a_uint8_t *nodedata;
1347 nodedata = (a_uint8_t *)data;
1348 node_index = *nodedata;
1349 sc->sc_sta[node_index].an_valid = 0;
1351 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1354 static void ath_node_update_tgt(void *Context, A_UINT16 Command,
1355 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1357 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1358 struct ieee80211_node_target *node;
1359 a_uint8_t vap_index;
1360 a_uint8_t node_index;
1362 node = (struct ieee80211_node_target *)data;
1364 node_index = node->ni_nodeindex;
1366 node->ni_htcap = adf_os_ntohs(node->ni_htcap);
1367 node->ni_flags = adf_os_ntohs(node->ni_flags);
1368 node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu);
1370 adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node,
1373 vap_index = sc->sc_sta[node_index].ni.ni_vapindex;
1374 sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap);
1376 sc->sc_sta[node_index].ni.ni_txseqmgmt = 0;
1377 sc->sc_sta[node_index].ni.ni_iv16 = 0;
1378 sc->sc_sta[node_index].ni.ni_iv32 = 0;
1380 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1383 static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command,
1384 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1386 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1387 struct ath_hal *ah = sc->sc_ah;
1392 for (i = 0; i < datalen; i += sizeof(a_int32_t)) {
1393 addr = *(a_uint32_t *)(data + i);
1394 addr = adf_os_ntohl(addr);
1396 if ((addr & 0xffffe000) == 0x2000) {
1398 ath_hal_reg_read_target(ah, addr);
1399 if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0)) {
1400 adf_os_print("SEEPROM Read fail: 0x%08x\n", addr);
1402 val[i/sizeof(a_int32_t)] = (ath_hal_reg_read_target(ah, 0x407c) & 0x0000ffff);
1403 } else if (addr > 0xffff) {
1404 val[i/sizeof(a_int32_t)] = *(a_uint32_t *)addr;
1406 val[i/sizeof(a_int32_t)] = ath_hal_reg_read_target(ah, addr);
1408 val[i/sizeof(a_int32_t)] = adf_os_ntohl(val[i/sizeof(a_int32_t)]);
1411 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &val[0], datalen);
1414 static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command,
1415 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1417 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1418 struct ath_hal *ah = sc->sc_ah;
1420 struct registerWrite {
1425 for (i = 0; i < datalen; i += sizeof(struct registerWrite)) {
1426 t = (struct registerWrite *)(data+i);
1428 if( t->reg > 0xffff ) {
1429 HAL_WORD_REG_WRITE(t->reg, t->val);
1430 #if defined(PROJECT_K2)
1431 if( t->reg == 0x50040 ) {
1432 static uint8_t flg=0;
1436 A_UART_HWINIT(117*1000*1000, 19200);
1442 #if defined(PROJECT_K2)
1443 if( t->reg == 0x7014 ) {
1444 static uint8_t resetPLL = 0;
1446 if( resetPLL == 0 ) {
1447 /* here we write to core register */
1448 HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x0);
1449 /* and here to mac register */
1450 ath_hal_reg_write_target(ah, 0x786c,
1451 ath_hal_reg_read_target(ah,0x786c) | 0x6000000);
1452 ath_hal_reg_write_target(ah, 0x786c,
1453 ath_hal_reg_read_target(ah,0x786c) & (~0x6000000));
1455 HAL_WORD_REG_WRITE(MAGPIE_REG_RST_PWDN_CTRL_ADDR, 0x20);
1459 #elif defined(PROJECT_MAGPIE) && !defined (FPGA)
1460 if( t->reg == 0x7014 ){
1461 static uint8_t resetPLL = 0;
1463 if( resetPLL == 0 ) {
1464 ath_hal_reg_write_target(ah, 0x7890,
1465 ath_hal_reg_read_target(ah,0x7890) | 0x1800000);
1466 ath_hal_reg_write_target(ah, 0x7890,
1467 ath_hal_reg_read_target(ah,0x7890) & (~0x1800000));
1472 ath_hal_reg_write_target(ah,t->reg,t->val);
1476 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1479 static void ath_hal_reg_rmw_tgt(void *Context, A_UINT16 Command,
1480 A_UINT16 SeqNo, A_UINT8 *data,
1483 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1484 struct ath_hal *ah = sc->sc_ah;
1485 struct register_rmw *buf = (struct register_rmw *)data;
1488 for (i = 0; i < datalen;
1489 i += sizeof(struct register_rmw)) {
1491 buf = (struct register_rmw *)(data + i);
1493 val = ath_hal_reg_read_target(ah, buf->reg);
1496 ath_hal_reg_write_target(ah, buf->reg, val);
1498 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1501 static void ath_vap_delete_tgt(void *Context, A_UINT16 Command,
1502 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1504 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1505 a_uint8_t vap_index;
1507 vap_index = *(a_uint8_t *)data;
1509 sc->sc_vap[vap_index].av_valid = 0;
1510 sc->sc_vap[vap_index].av_bcbuf = NULL;
1511 ath_node_vdelete_tgt(sc, vap_index);
1512 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1515 static void ath_disable_intr_tgt(void *Context, A_UINT16 Command,
1516 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1518 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1519 struct ath_hal *ah = sc->sc_ah;
1521 ah->ah_setInterrupts(ah, 0);
1522 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
1525 static void ath_flushrecv_tgt(void *Context, A_UINT16 Command,
1526 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1528 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1529 struct ath_rx_buf *bf;
1531 asf_tailq_foreach(bf, &sc->sc_rxbuf, bf_list)
1532 if (bf->bf_skb != NULL) {
1533 adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap,
1534 ADF_OS_DMA_FROM_DEVICE);
1535 ath_free_rx_skb(sc, adf_nbuf_queue_remove(&bf->bf_skbhead));
1539 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1542 static void ath_tx_draintxq_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1543 A_UINT8 *data, a_int32_t datalen)
1545 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1546 a_uint32_t q = *(a_uint32_t *)data;
1547 struct ath_txq *txq = NULL;
1549 q = adf_os_ntohl(q);
1550 txq = ATH_TXQ(sc, q);
1552 ath_tx_draintxq(sc, txq);
1553 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1556 static void ath_draintxq_tgt(void *Context, A_UINT16 Command,
1557 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1559 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1560 HAL_BOOL b = (HAL_BOOL) *(a_int32_t *)data;
1562 ath_draintxq(Context, b);
1563 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1566 static void ath_aborttx_dma_tgt(void *Context, A_UINT16 Command,
1567 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1569 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1570 struct ath_hal *ah = sc->sc_ah;
1572 ah->ah_abortTxDma(sc->sc_ah);
1573 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1576 static void ath_aborttxq_tgt(void *Context, A_UINT16 Command,
1577 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1580 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1583 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
1584 if (ATH_TXQ_SETUP(sc, i))
1585 ath_tx_draintxq(sc, ATH_TXQ(sc,i));
1588 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1591 static void ath_stop_tx_dma_tgt(void *Context, A_UINT16 Command,
1592 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1594 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1595 struct ath_hal *ah = sc->sc_ah;
1599 q = *(a_uint32_t *)data;
1601 q = adf_os_ntohl(q);
1602 ah->ah_stopTxDma(ah, q);
1603 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1606 static void ath_startrecv_tgt(void *Context, A_UINT16 Command,
1607 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1610 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1613 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1616 static void ath_stoprecv_tgt(void *Context, A_UINT16 Command,
1617 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1619 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1620 struct ath_hal *ah = sc->sc_ah;
1622 ah->ah_stopPcuReceive(ah);
1623 ah->ah_setRxFilter(ah, 0);
1624 ah->ah_stopDmaReceive(ah);
1626 sc->sc_rxlink = NULL;
1627 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1630 static void ath_setcurmode_tgt(void *Context, A_UINT16 Command,
1631 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1633 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1636 mode= *((a_uint16_t *)data);
1637 mode = adf_os_ntohs(mode);
1639 ath_setcurmode(sc, mode);
1641 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1644 static void ath_detach_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1645 A_UINT8 *data, a_int32_t datalen)
1647 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1648 struct ath_hal *ah = sc->sc_ah;
1652 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1653 adf_os_mem_free(sc);
1656 static void handle_echo_command(void *pContext, A_UINT16 Command,
1657 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1659 wmi_cmd_rsp(pContext, WMI_ECHO_CMDID, SeqNo, buffer, Length);
1662 static void handle_rc_state_change_cmd(void *Context, A_UINT16 Command,
1663 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1666 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1667 struct wmi_rc_state_change_cmd *wmi_data = (struct wmi_rc_state_change_cmd *)buffer;
1669 a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag);
1671 ath_rate_newstate(sc, &sc->sc_vap[wmi_data->vap_index].av_vap,
1672 wmi_data->vap_state,
1676 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1679 static void handle_rc_rate_update_cmd(void *Context, A_UINT16 Command,
1680 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1682 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1683 struct wmi_rc_rate_update_cmd *wmi_data = (struct wmi_rc_rate_update_cmd *)buffer;
1685 a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag);
1687 ath_rate_node_update(sc, &sc->sc_sta[wmi_data->node_index],
1692 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1695 static void dispatch_magpie_sys_cmds(void *pContext, A_UINT16 Command,
1696 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1701 static void ath_rc_mask_tgt(void *Context, A_UINT16 Command,
1702 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1704 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1705 struct wmi_rc_rate_mask_cmd *wmi_data = (struct wmi_rc_rate_mask_cmd *)buffer;
1708 idx = wmi_data->vap_index;
1709 band = wmi_data->band;
1711 sc->sc_vap[idx].av_rate_mask[band] = adf_os_ntohl(wmi_data->mask);
1713 if (sc->sc_vap[idx].av_rate_mask[band]) {
1714 for (i = 0; i < RATE_TABLE_SIZE; i++) {
1715 if ((1 << i) & sc->sc_vap[idx].av_rate_mask[band]) {
1716 sc->sc_vap[idx].av_minrateidx[band] = i;
1721 sc->sc_vap[idx].av_minrateidx[band] = 0;
1724 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1727 static WMI_DISPATCH_ENTRY Magpie_Sys_DispatchEntries[] =
1729 {handle_echo_command, WMI_ECHO_CMDID, 0},
1730 {dispatch_magpie_sys_cmds, WMI_ACCESS_MEMORY_CMDID, 0},
1731 {ath_get_tgt_version, WMI_GET_FW_VERSION, 0},
1732 {ath_disable_intr_tgt, WMI_DISABLE_INTR_CMDID, 0},
1733 {ath_enable_intr_tgt, WMI_ENABLE_INTR_CMDID, 0},
1734 {ath_init_tgt, WMI_ATH_INIT_CMDID, 0},
1735 {ath_aborttxq_tgt, WMI_ABORT_TXQ_CMDID, 0},
1736 {ath_stop_tx_dma_tgt, WMI_STOP_TX_DMA_CMDID, 0},
1737 {ath_aborttx_dma_tgt, WMI_ABORT_TX_DMA_CMDID, 0},
1738 {ath_tx_draintxq_tgt, WMI_DRAIN_TXQ_CMDID, 0},
1739 {ath_draintxq_tgt, WMI_DRAIN_TXQ_ALL_CMDID, 0},
1740 {ath_startrecv_tgt, WMI_START_RECV_CMDID, 0},
1741 {ath_stoprecv_tgt, WMI_STOP_RECV_CMDID, 0},
1742 {ath_flushrecv_tgt, WMI_FLUSH_RECV_CMDID, 0},
1743 {ath_setcurmode_tgt, WMI_SET_MODE_CMDID, 0},
1744 {ath_node_create_tgt, WMI_NODE_CREATE_CMDID, 0},
1745 {ath_node_cleanup_tgt, WMI_NODE_REMOVE_CMDID, 0},
1746 {ath_vap_delete_tgt, WMI_VAP_REMOVE_CMDID, 0},
1747 {ath_vap_create_tgt, WMI_VAP_CREATE_CMDID, 0},
1748 {ath_hal_reg_read_tgt, WMI_REG_READ_CMDID, 0},
1749 {ath_hal_reg_write_tgt, WMI_REG_WRITE_CMDID, 0},
1750 {handle_rc_state_change_cmd, WMI_RC_STATE_CHANGE_CMDID, 0},
1751 {handle_rc_rate_update_cmd, WMI_RC_RATE_UPDATE_CMDID, 0},
1752 {ath_ic_update_tgt, WMI_TARGET_IC_UPDATE_CMDID, 0},
1753 {ath_enable_aggr_tgt, WMI_TX_AGGR_ENABLE_CMDID, 0},
1754 {ath_detach_tgt, WMI_TGT_DETACH_CMDID, 0},
1755 {ath_node_update_tgt, WMI_NODE_UPDATE_CMDID, 0},
1756 {ath_int_stats_tgt, WMI_INT_STATS_CMDID, 0},
1757 {ath_tx_stats_tgt, WMI_TX_STATS_CMDID, 0},
1758 {ath_rx_stats_tgt, WMI_RX_STATS_CMDID, 0},
1759 {ath_rc_mask_tgt, WMI_BITRATE_MASK_CMDID, 0},
1760 {ath_hal_reg_rmw_tgt, WMI_REG_RMW_CMDID, 0},
1767 static void htc_setup_comp(void)
1771 static A_UINT8 tgt_ServiceConnect(HTC_SERVICE *pService,
1772 HTC_ENDPOINT_ID eid,
1776 a_int32_t *pLengthOut)
1778 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)pService->ServiceCtx;
1780 switch(pService->ServiceID) {
1781 case WMI_CONTROL_SVC:
1782 sc->wmi_command_ep= eid;
1784 case WMI_BEACON_SVC:
1796 case WMI_DATA_VO_SVC:
1797 sc->data_VO_ep = eid;
1799 case WMI_DATA_VI_SVC:
1800 sc->data_VI_ep = eid;
1802 case WMI_DATA_BE_SVC:
1803 sc->data_BE_ep = eid;
1805 case WMI_DATA_BK_SVC:
1806 sc->data_BK_ep = eid;
1812 return HTC_SERVICE_SUCCESS;
1815 static void tgt_reg_service(struct ath_softc_tgt *sc, HTC_SERVICE *svc,
1816 int svcId, HTC_SERVICE_ProcessRecvMsg recvMsg)
1818 svc->ProcessRecvMsg = recvMsg;
1819 svc->ProcessSendBufferComplete = tgt_HTCSendCompleteHandler;
1820 svc->ProcessConnect = tgt_ServiceConnect;
1821 svc->MaxSvcMsgSize = 1600;
1822 svc->TrailerSpcCheckLimit = 0;
1823 svc->ServiceID = svcId;
1824 svc->ServiceCtx = sc;
1825 HTC_RegisterService(sc->tgt_htc_handle, svc);
1828 static void tgt_hif_htc_wmi_init(struct ath_softc_tgt *sc)
1830 HTC_CONFIG htc_conf;
1831 WMI_SVC_CONFIG wmiConfig;
1832 WMI_DISPATCH_TABLE *Magpie_Sys_Commands_Tbl;
1834 /* Init dynamic buf pool */
1835 sc->pool_handle = BUF_Pool_init(sc->sc_hdl);
1837 /* Init target-side HIF */
1838 sc->tgt_hif_handle = HIF_init(0);
1840 /* Init target-side HTC */
1841 htc_conf.HIFHandle = sc->tgt_hif_handle;
1842 htc_conf.CreditSize = 320;
1843 htc_conf.CreditNumber = ATH_TXBUF;
1844 htc_conf.OSHandle = sc->sc_hdl;
1845 htc_conf.PoolHandle = sc->pool_handle;
1846 sc->tgt_htc_handle = HTC_init(htc_setup_comp, &htc_conf);
1847 #if defined(PROJECT_MAGPIE)
1848 init_htc_handle = sc->tgt_htc_handle;
1851 tgt_reg_service(sc, &sc->htc_beacon_service, WMI_BEACON_SVC, tgt_HTCRecv_beaconhandler);
1852 tgt_reg_service(sc, &sc->htc_cab_service, WMI_CAB_SVC, tgt_HTCRecv_cabhandler);
1853 tgt_reg_service(sc, &sc->htc_uapsd_service, WMI_UAPSD_SVC, tgt_HTCRecv_uapsdhandler);
1854 tgt_reg_service(sc, &sc->htc_mgmt_service, WMI_MGMT_SVC, tgt_HTCRecv_mgmthandler);
1855 tgt_reg_service(sc, &sc->htc_data_BE_service, WMI_DATA_BE_SVC, tgt_HTCRecvMessageHandler);
1856 tgt_reg_service(sc, &sc->htc_data_BK_service, WMI_DATA_BK_SVC, tgt_HTCRecvMessageHandler);
1857 tgt_reg_service(sc, &sc->htc_data_VI_service, WMI_DATA_VI_SVC, tgt_HTCRecvMessageHandler);
1858 tgt_reg_service(sc, &sc->htc_data_VO_service, WMI_DATA_VO_SVC, tgt_HTCRecvMessageHandler);
1860 /* Init target-side WMI */
1861 Magpie_Sys_Commands_Tbl = (WMI_DISPATCH_TABLE *)adf_os_mem_alloc(sizeof(WMI_DISPATCH_TABLE));
1862 adf_os_mem_zero(Magpie_Sys_Commands_Tbl, sizeof(WMI_DISPATCH_TABLE));
1863 Magpie_Sys_Commands_Tbl->NumberOfEntries = WMI_DISPATCH_ENTRY_COUNT(Magpie_Sys_DispatchEntries);
1864 Magpie_Sys_Commands_Tbl->pTable = Magpie_Sys_DispatchEntries;
1866 adf_os_mem_zero(&wmiConfig, sizeof(WMI_SVC_CONFIG));
1867 wmiConfig.HtcHandle = sc->tgt_htc_handle;
1868 wmiConfig.PoolHandle = sc->pool_handle;
1869 wmiConfig.MaxCmdReplyEvts = ATH_WMI_MAX_CMD_REPLY;
1870 wmiConfig.MaxEventEvts = ATH_WMI_MAX_EVENTS;
1872 sc->tgt_wmi_handle = WMI_Init(&wmiConfig);
1873 Magpie_Sys_Commands_Tbl->pContext = sc;
1874 WMI_RegisterDispatchTable(sc->tgt_wmi_handle, Magpie_Sys_Commands_Tbl);
1876 HTC_NotifyTargetInserted(sc->tgt_htc_handle);
1878 /* Start HTC messages exchange */
1879 HTC_Ready(sc->tgt_htc_handle);
1882 a_int32_t ath_tgt_attach(a_uint32_t devid, struct ath_softc_tgt *sc, adf_os_device_t osdev)
1886 a_int32_t error = 0, i, flags = 0;
1889 adf_os_pci_config_read8(osdev, ATH_PCI_CACHE_LINE_SIZE, &csz);
1893 sc->sc_cachelsz = csz << 2;
1898 ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_rxtq, ath_tgt_rx_tasklet, sc);
1899 ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_txtq, owl_tgt_tx_tasklet, sc);
1900 ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_bmisstq, ath_bmiss_tasklet, sc);
1901 ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_fataltq, ath_fatal_tasklet, sc);
1903 flags |= AH_USE_EEPROM;
1904 ah = _ath_hal_attach_tgt(devid, sc, sc->sc_dev, flags, &status);
1911 tgt_hif_htc_wmi_init(sc);
1913 sc->sc_bhalq = HAL_NUM_TX_QUEUES - 1;
1915 ath_rate_setup(sc, IEEE80211_MODE_11NA);
1916 ath_rate_setup(sc, IEEE80211_MODE_11NG);
1918 sc->sc_rc = ath_rate_attach(sc);
1919 if (sc->sc_rc == NULL) {
1924 for (i=0; i < TARGET_NODE_MAX; i++) {
1925 sc->sc_sta[i].an_rcnode = adf_os_mem_alloc(sc->sc_rc->arc_space);
1928 error = ath_desc_alloc(sc);
1933 BUF_Pool_create_pool(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ath_numrxdescs, 1664);
1935 ath_tgt_txq_setup(sc);
1937 ah->ah_setInterrupts(ah, 0);
1947 static void tgt_hif_htc_wmi_shutdown(struct ath_softc_tgt *sc)
1949 HTC_NotifyTargetDetached(sc->tgt_htc_handle);
1951 WMI_Shutdown(sc->tgt_wmi_handle);
1952 HTC_Shutdown(sc->tgt_htc_handle);
1953 HIF_shutdown(sc->tgt_hif_handle);
1954 BUF_Pool_shutdown(sc->pool_handle);
1957 a_int32_t ath_detach(struct ath_softc_tgt *sc)
1959 tgt_hif_htc_wmi_shutdown(sc);