2 * Copyright (c) 2013 Qualcomm Atheros, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted (subject to the limitations in the
7 * disclaimer below) provided that the following conditions are met:
9 * * Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the
17 * * Neither the name of Qualcomm Atheros nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
22 * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
23 * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
32 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
33 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <adf_os_types.h>
37 #include <adf_os_pci.h>
38 #include <adf_os_dma.h>
39 #include <adf_os_timer.h>
40 #include <adf_os_lock.h>
41 #include <adf_os_io.h>
42 #include <adf_os_mem.h>
43 #include <adf_os_util.h>
44 #include <adf_os_stdtypes.h>
45 #include <adf_os_defer.h>
46 #include <adf_os_atomic.h>
49 #include <adf_net_wcmd.h>
50 #include <adf_os_irq.h>
52 #include <if_ath_pci.h>
54 #include "ieee80211_var.h"
55 #include "if_athrate.h"
56 #include "if_athvar.h"
59 static a_int32_t ath_numrxbufs = -1;
60 static a_int32_t ath_numrxdescs = -1;
62 #if defined(PROJECT_MAGPIE)
63 uint32_t *init_htc_handle = 0;
66 #define RX_ENDPOINT_ID 3
67 #define ATH_CABQ_HANDLING_THRESHOLD 9000
71 void owl_tgt_tx_tasklet(TQUEUE_ARG data);
72 static void ath_tgt_send_beacon(struct ath_softc_tgt *sc,adf_nbuf_t bc_hdr,adf_nbuf_t nbuf,HTC_ENDPOINT_ID EndPt);
73 static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen);
74 extern struct ath_tx_buf* ath_tgt_tx_prepare(struct ath_softc_tgt *sc, adf_nbuf_t skb, ath_data_hdr_t *dh);
75 extern void ath_tgt_send_mgt(struct ath_softc_tgt *sc,adf_nbuf_t mgt_hdr, adf_nbuf_t skb,HTC_ENDPOINT_ID EndPt);
76 extern HAL_BOOL ath_hal_wait(struct ath_hal *ah, a_uint32_t reg, a_uint32_t mask, a_uint32_t val);
77 extern void owltgt_tx_processq(struct ath_softc_tgt *sc, struct ath_txq *txq, owl_txq_state_t txqstate);
78 void owl_tgt_node_init(struct ath_node_target * an);
79 void ath_tgt_tx_sched_normal(struct ath_softc_tgt *sc, struct ath_buf *bf);
80 void ath_tgt_tx_sched_nonaggr(struct ath_softc_tgt *sc,struct ath_buf * bf_host);
86 #undef adf_os_cpu_to_le16
88 static a_uint16_t adf_os_cpu_to_le16(a_uint16_t x)
90 return ((((x) & 0xff00) >> 8) | (((x) & 0x00ff) << 8));
94 * Extend a 32 bit TSF to 64 bit, taking wrapping into account.
96 static u_int64_t ath_extend_tsf(struct ath_softc_tgt *sc, u_int32_t rstamp)
102 tsf = ath_hal_gettsf64(sc->sc_ah);
103 tsf_low = tsf & 0xffffffff;
104 tsf64 = (tsf & ~0xffffffffULL) | rstamp;
106 if (rstamp > tsf_low && (rstamp - tsf_low > 0x10000000))
107 tsf64 -= 0x100000000ULL;
109 if (rstamp < tsf_low && (tsf_low - rstamp > 0x10000000))
110 tsf64 += 0x100000000ULL;
115 static a_int32_t ath_rate_setup(struct ath_softc_tgt *sc, a_uint32_t mode)
117 struct ath_hal *ah = sc->sc_ah;
118 const HAL_RATE_TABLE *rt;
121 case IEEE80211_MODE_11NA:
122 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11NA);
124 case IEEE80211_MODE_11NG:
125 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11NG);
130 rt = sc->sc_rates[mode];
137 static void ath_setcurmode(struct ath_softc_tgt *sc,
138 enum ieee80211_phymode mode)
140 const HAL_RATE_TABLE *rt;
143 adf_os_mem_set(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
145 rt = sc->sc_rates[mode];
146 adf_os_assert(rt != NULL);
148 for (i = 0; i < rt->rateCount; i++) {
149 sc->sc_rixmap[rt->info[i].rateCode] = i;
152 sc->sc_currates = rt;
153 sc->sc_curmode = mode;
154 sc->sc_protrix = ((mode == IEEE80211_MODE_11NG) ? 3 : 0);
158 void wmi_event(wmi_handle_t handle, WMI_EVENT_ID evt_id,
159 void *buffer, a_int32_t Length)
161 adf_nbuf_t netbuf = ADF_NBUF_NULL;
164 netbuf = WMI_AllocEvent(handle, WMI_EVT_CLASS_CMD_EVENT,
165 sizeof(WMI_CMD_HDR) + Length);
167 if (netbuf == ADF_NBUF_NULL) {
168 adf_os_print("Buf null\n");
172 if (buffer != NULL && Length != 0 && Length < WMI_SVC_MAX_BUFFERED_EVENT_SIZE) {
173 pData = adf_nbuf_put_tail(netbuf, Length);
174 adf_os_mem_copy(pData, buffer, Length);
177 WMI_SendEvent(handle, netbuf, evt_id, 0, Length);
180 void wmi_cmd_rsp(void *pContext, WMI_COMMAND_ID cmd_id, A_UINT16 SeqNo,
181 void *buffer, a_int32_t Length)
183 adf_nbuf_t netbuf = ADF_NBUF_NULL;
186 netbuf = WMI_AllocEvent(pContext, WMI_EVT_CLASS_CMD_REPLY,
187 sizeof(WMI_CMD_HDR) + Length);
189 if (netbuf == ADF_NBUF_NULL) {
194 if (Length != 0 && buffer != NULL) {
195 pData = (A_UINT8 *)adf_nbuf_put_tail(netbuf, Length);
196 adf_os_mem_copy(pData, buffer, Length);
199 WMI_SendEvent(pContext, netbuf, cmd_id, SeqNo, Length);
202 static void ath_node_vdelete_tgt(struct ath_softc_tgt *sc, a_uint8_t vap_index)
206 for (i = 0; i < TARGET_NODE_MAX; i++) {
207 if(sc->sc_sta[i].ni.ni_vapindex == vap_index)
208 sc->sc_sta[i].an_valid = 0;
212 a_uint8_t ath_get_minrateidx(struct ath_softc_tgt *sc, struct ath_vap_target *avp)
214 if (sc->sc_curmode == IEEE80211_MODE_11NG)
215 return avp->av_minrateidx[0];
216 else if (sc->sc_curmode == IEEE80211_MODE_11NA)
217 return avp->av_minrateidx[1];
226 static adf_nbuf_t ath_alloc_skb_align(struct ath_softc_tgt *sc,
227 a_uint32_t size, a_uint32_t align)
231 skb = BUF_Pool_alloc_buf_align(sc->pool_handle, POOL_ID_WLAN_RX_BUF,
232 RX_HEADER_SPACE, align);
236 static a_int32_t ath_rxdesc_init(struct ath_softc_tgt *sc, struct ath_rx_desc *ds)
238 struct ath_hal *ah = sc->sc_ah;
239 struct ath_rx_desc *ds_held;
243 if (!sc->sc_rxdesc_held) {
244 sc->sc_rxdesc_held = ds;
248 ds_held = sc->sc_rxdesc_held;
249 sc->sc_rxdesc_held = ds;
252 if (ds->ds_nbuf == ADF_NBUF_NULL) {
253 ds->ds_nbuf = ath_alloc_skb_align(sc, sc->sc_rxbufsize, sc->sc_cachelsz);
254 if (ds->ds_nbuf == ADF_NBUF_NULL) {
255 sc->sc_rxdesc_held = ds;
256 sc->sc_rx_stats.ast_rx_nobuf++;
259 adf_nbuf_map(sc->sc_dev, ds->ds_dmap, ds->ds_nbuf, ADF_OS_DMA_FROM_DEVICE);
260 adf_nbuf_dmamap_info(ds->ds_dmap, &ds->ds_dmap_info);
261 ds->ds_data = ds->ds_dmap_info.dma_segs[0].paddr;
265 adf_nbuf_peek_header(ds->ds_nbuf, &anbdata, &anblen);
267 ath_hal_setuprxdesc(ah, ds,
268 adf_nbuf_tailroom(ds->ds_nbuf),
271 if (sc->sc_rxlink == NULL) {
272 ath_hal_putrxbuf(ah, ds->ds_daddr);
275 *sc->sc_rxlink = ds->ds_daddr;
277 sc->sc_rxlink = &ds->ds_link;
283 static void ath_rx_complete(struct ath_softc_tgt *sc, adf_nbuf_t buf)
285 struct ath_rx_desc *ds;
287 adf_nbuf_queue_t nbuf_head;
289 adf_nbuf_split_to_frag(buf, &nbuf_head);
290 ds = asf_tailq_first(&sc->sc_rxdesc_idle);
293 struct ath_rx_desc *ds_tmp;
294 buf_tmp = adf_nbuf_queue_remove(&nbuf_head);
296 if (buf_tmp == NULL) {
300 BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, buf_tmp);
303 ds = asf_tailq_next(ds, ds_list);
305 ath_rxdesc_init(sc, ds_tmp);
307 asf_tailq_remove(&sc->sc_rxdesc_idle, ds_tmp, ds_list);
308 asf_tailq_insert_tail(&sc->sc_rxdesc, ds_tmp, ds_list);
312 static void tgt_HTCSendCompleteHandler(HTC_ENDPOINT_ID Endpt, adf_nbuf_t buf, void *ServiceCtx)
314 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
316 if (Endpt == RX_ENDPOINT_ID) {
317 sc->sc_rx_stats.ast_rx_done++;
318 ath_rx_complete(sc, buf);
322 static void ath_uapsd_processtriggers(struct ath_softc_tgt *sc)
324 struct ath_hal *ah = sc->sc_ah;
325 struct ath_rx_buf *bf = NULL;
326 struct ath_rx_desc *ds, *ds_head, *ds_tail, *ds_tmp;
329 a_uint16_t frame_len = 0;
332 #define PA2DESC(_sc, _pa) \
333 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \
334 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr)))
336 tsf = ath_hal_gettsf64(ah);
337 bf = asf_tailq_first(&sc->sc_rxbuf);
339 ds = asf_tailq_first(&sc->sc_rxdesc);
345 if (cnt == ath_numrxbufs - 1) {
346 adf_os_print("VERY LONG PACKET!!!!!\n");
350 struct ath_rx_desc *ds_rmv;
351 adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE);
353 ds_tmp = asf_tailq_next(ds_tmp, ds_list);
355 if (ds_tmp == NULL) {
356 adf_os_print("ds_tmp is NULL\n");
360 BUF_Pool_free_buf(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ds_rmv->ds_nbuf);
361 ds_rmv->ds_nbuf = ADF_NBUF_NULL;
363 if (ath_rxdesc_init(sc, ds_rmv) == 0) {
364 asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
365 asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list);
368 asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
369 asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list);
372 if (ds_rmv == ds_tail) {
379 if (ds->ds_link == 0) {
383 if (bf->bf_status & ATH_BUFSTATUS_DONE) {
387 retval = ath_hal_rxprocdescfast(ah, ds, ds->ds_daddr,
388 PA2DESC(sc, ds->ds_link), &bf->bf_rx_status);
389 if (HAL_EINPROGRESS == retval) {
393 if (adf_nbuf_len(ds->ds_nbuf) == 0) {
394 adf_nbuf_put_tail(ds->ds_nbuf, bf->bf_rx_status.rs_datalen);
397 frame_len += bf->bf_rx_status.rs_datalen;
399 if (bf->bf_rx_status.rs_more == 0) {
400 adf_nbuf_queue_t nbuf_head;
401 adf_nbuf_queue_init(&nbuf_head);
406 ds = asf_tailq_next(ds, ds_list);
409 ds_head = asf_tailq_next(ds_tail, ds_list);
412 struct ath_rx_desc *ds_rmv;
414 adf_nbuf_unmap(sc->sc_dev, ds_tmp->ds_dmap, ADF_OS_DMA_FROM_DEVICE);
415 adf_nbuf_queue_add(&nbuf_head, ds_tmp->ds_nbuf);
416 ds_tmp->ds_nbuf = ADF_NBUF_NULL;
419 ds_tmp = asf_tailq_next(ds_tmp, ds_list);
420 if (ds_tmp == NULL) {
424 if (ath_rxdesc_init(sc, ds_rmv) == 0) {
425 asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
426 asf_tailq_insert_tail(&sc->sc_rxdesc, ds_rmv, ds_list);
428 asf_tailq_remove(&sc->sc_rxdesc, ds_rmv, ds_list);
429 asf_tailq_insert_tail(&sc->sc_rxdesc_idle, ds_rmv, ds_list);
432 if (ds_rmv == ds_tail) {
438 bf->bf_rx_status.rs_datalen = frame_len;
441 bf->bf_skb = adf_nbuf_create_frm_frag(&nbuf_head);
443 bf->bf_status |= ATH_BUFSTATUS_DONE;
445 bf = (struct ath_rx_buf *)asf_tailq_next(bf, bf_list);
448 ds = asf_tailq_next(ds, ds_list);
455 static a_int32_t ath_startrecv(struct ath_softc_tgt *sc)
457 struct ath_hal *ah = sc->sc_ah;
458 struct ath_rx_desc *ds;
460 sc->sc_rxbufsize = 1024+512+128;
461 sc->sc_rxlink = NULL;
463 sc->sc_rxdesc_held = NULL;
465 asf_tailq_foreach(ds, &sc->sc_rxdesc, ds_list) {
466 a_int32_t error = ath_rxdesc_init(sc, ds);
472 ds = asf_tailq_first(&sc->sc_rxdesc);
473 ath_hal_putrxbuf(ah, ds->ds_daddr);
478 static void ath_tgt_rx_tasklet(TQUEUE_ARG data)
480 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
481 struct ath_rx_buf *bf = NULL;
482 struct ath_hal *ah = sc->sc_ah;
483 struct rx_frame_header *rxhdr;
484 struct ath_rx_status *rxstats;
485 adf_nbuf_t skb = ADF_NBUF_NULL;
488 bf = asf_tailq_first(&sc->sc_rxbuf);
493 if (!(bf->bf_status & ATH_BUFSTATUS_DONE)) {
502 asf_tailq_remove(&sc->sc_rxbuf, bf, bf_list);
506 rxhdr = (struct rx_frame_header *)adf_nbuf_push_head(skb,
507 sizeof(struct rx_frame_header));
508 rxstats = (struct ath_rx_status *)(&rxhdr->rx_stats[0]);
509 adf_os_mem_copy(rxstats, &(bf->bf_rx_status),
510 sizeof(struct ath_rx_status));
512 rxstats->rs_tstamp = ath_extend_tsf(sc, (u_int32_t)rxstats->rs_tstamp);
514 HTC_SendMsg(sc->tgt_htc_handle, RX_ENDPOINT_ID, skb);
515 sc->sc_rx_stats.ast_rx_send++;
517 bf->bf_status &= ~ATH_BUFSTATUS_DONE;
518 asf_tailq_insert_tail(&sc->sc_rxbuf, bf, bf_list);
522 sc->sc_imask |= HAL_INT_RX;
523 ath_hal_intrset(ah, sc->sc_imask);
526 /*******************/
527 /* Beacon Handling */
528 /*******************/
531 * Setup the beacon frame for transmit.
532 * FIXME: Short Preamble.
534 static void ath_beacon_setup(struct ath_softc_tgt *sc,
535 struct ath_tx_buf *bf,
536 struct ath_vap_target *avp)
538 adf_nbuf_t skb = bf->bf_skb;
539 struct ath_hal *ah = sc->sc_ah;
540 struct ath_tx_desc *ds;
542 const HAL_RATE_TABLE *rt;
544 HAL_11N_RATE_SERIES series[4] = {{ 0 }};
546 flags = HAL_TXDESC_NOACK;
550 ds->ds_data = bf->bf_dmamap_info.dma_segs[0].paddr;
552 rix = ath_get_minrateidx(sc, avp);
553 rt = sc->sc_currates;
554 rate = rt->info[rix].rateCode;
556 ath_hal_setuptxdesc(ah, ds
557 , adf_nbuf_len(skb) + IEEE80211_CRC_LEN
558 , sizeof(struct ieee80211_frame)
559 , HAL_PKT_TYPE_BEACON
562 , HAL_TXKEYIX_INVALID
569 , ATH_COMP_PROC_NO_COMP_NO_CCS);
571 ath_hal_filltxdesc(ah, ds
572 , asf_roundup(adf_nbuf_len(skb), 4)
578 series[0].Rate = rate;
579 series[0].ChSel = sc->sc_ic.ic_tx_chainmask;
580 series[0].RateFlags = 0;
581 ath_hal_set11n_ratescenario(ah, ds, 0, 0, 0, series, 4, 0);
584 static void ath_tgt_send_beacon(struct ath_softc_tgt *sc, adf_nbuf_t bc_hdr,
585 adf_nbuf_t nbuf, HTC_ENDPOINT_ID EndPt)
587 struct ath_hal *ah = sc->sc_ah;
588 struct ath_tx_buf *bf;
589 a_uint8_t vap_index, *anbdata;
590 ath_beacon_hdr_t *bhdr;
591 struct ieee80211vap_target *vap;
593 struct ieee80211_frame *wh;
596 adf_nbuf_peek_header(nbuf, &anbdata, &anblen);
597 bhdr = (ath_beacon_hdr_t *)anbdata;
599 adf_os_print("found bc_hdr! 0x%x\n", bc_hdr);
602 vap_index = bhdr->vap_index;
603 adf_os_assert(vap_index < TARGET_VAP_MAX);
604 vap = &sc->sc_vap[vap_index].av_vap;
606 wh = (struct ieee80211_frame *)adf_nbuf_pull_head(nbuf,
607 sizeof(ath_beacon_hdr_t));
609 bf = sc->sc_vap[vap_index].av_bcbuf;
611 bf->bf_endpt = EndPt;
614 adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, ADF_OS_DMA_TO_DEVICE);
615 adf_nbuf_push_head(bf->bf_skb, sizeof(ath_beacon_hdr_t));
616 ath_free_tx_skb(sc->tgt_htc_handle, bf->bf_endpt, bf->bf_skb);
621 adf_nbuf_map(sc->sc_dev, bf->bf_dmamap, nbuf, ADF_OS_DMA_TO_DEVICE);
622 adf_nbuf_dmamap_info(bf->bf_dmamap,&bf->bf_dmamap_info);
624 ath_beacon_setup(sc, bf, &sc->sc_vap[vap_index]);
625 ath_hal_stoptxdma(ah, sc->sc_bhalq);
626 ath_hal_puttxbuf(ah, sc->sc_bhalq, ATH_BUF_GET_DESC_PHY_ADDR(bf));
627 ath_hal_txstart(ah, sc->sc_bhalq);
634 static void ath_tx_stopdma(struct ath_softc_tgt *sc, struct ath_txq *txq)
636 struct ath_hal *ah = sc->sc_ah;
638 (void) ath_hal_stoptxdma(ah, txq->axq_qnum);
641 static void owltgt_txq_drain(struct ath_softc_tgt *sc, struct ath_txq *txq)
643 owltgt_tx_processq(sc, txq, OWL_TXQ_STOPPED);
646 static void ath_tx_draintxq(struct ath_softc_tgt *sc, struct ath_txq *txq)
648 owltgt_txq_drain(sc, txq);
651 static void ath_draintxq(struct ath_softc_tgt *sc, HAL_BOOL drain_softq)
653 struct ath_hal *ah = sc->sc_ah;
655 struct ath_txq *txq = NULL;
656 struct ath_atx_tid *tid = NULL;
658 ath_tx_status_clear(sc);
659 sc->sc_tx_draining = 1;
661 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq);
663 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
664 if (ATH_TXQ_SETUP(sc, i))
665 ath_tx_stopdma(sc, ATH_TXQ(sc, i));
667 for (i = 0; i < HAL_NUM_TX_QUEUES; i++)
668 if (ATH_TXQ_SETUP(sc, i)) {
669 owltgt_tx_processq(sc, ATH_TXQ(sc,i), OWL_TXQ_STOPPED);
672 while (!asf_tailq_empty(&txq->axq_tidq)){
673 TAILQ_DEQ(&txq->axq_tidq, tid, tid_qelem);
676 tid->sched = AH_FALSE;
677 ath_tgt_tid_drain(sc,tid);
681 sc->sc_tx_draining = 0;
684 static void ath_tgt_txq_setup(struct ath_softc_tgt *sc)
691 for (qnum=0;qnum<HAL_NUM_TX_QUEUES;qnum++) {
692 txq= &sc->sc_txq[qnum];
693 txq->axq_qnum = qnum;
694 txq->axq_link = NULL;
695 asf_tailq_init(&txq->axq_q);
697 txq->axq_linkbuf = NULL;
698 asf_tailq_init(&txq->axq_tidq);
699 sc->sc_txqsetup |= 1<<qnum;
702 sc->sc_uapsdq = &sc->sc_txq[UAPSDQ_NUM];
703 sc->sc_cabq = &sc->sc_txq[CABQ_NUM];
705 sc->sc_ac2q[WME_AC_BE] = &sc->sc_txq[0];
706 sc->sc_ac2q[WME_AC_BK] = &sc->sc_txq[1];
707 sc->sc_ac2q[WME_AC_VI] = &sc->sc_txq[2];
708 sc->sc_ac2q[WME_AC_VO] = &sc->sc_txq[3];
714 static void tgt_HTCRecv_beaconhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
715 adf_nbuf_t buf, void *ServiceCtx)
717 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
719 ath_tgt_send_beacon(sc, hdr_buf, buf, EndPt);
722 static void tgt_HTCRecv_uapsdhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
723 adf_nbuf_t buf, void *ServiceCtx)
727 static void tgt_HTCRecv_mgmthandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
728 adf_nbuf_t buf, void *ServiceCtx)
730 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
732 ath_tgt_send_mgt(sc,hdr_buf,buf,EndPt);
735 static void tgt_HTCRecvMessageHandler(HTC_ENDPOINT_ID EndPt,
736 adf_nbuf_t hdr_buf, adf_nbuf_t buf,
739 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
740 struct ath_tx_buf *bf;
744 struct ath_node_target *an;
745 struct ath_atx_tid *tid;
748 adf_nbuf_peek_header(buf, &data, &len);
749 adf_nbuf_pull_head(buf, sizeof(ath_data_hdr_t));
751 adf_nbuf_peek_header(hdr_buf, &data, &len);
754 adf_os_assert(len >= sizeof(ath_data_hdr_t));
755 dh = (ath_data_hdr_t *)data;
757 an = &sc->sc_sta[dh->ni_index];
758 tid = ATH_AN_2_TID(an, dh->tidno);
760 sc->sc_tx_stats.tx_tgt++;
762 bf = ath_tgt_tx_prepare(sc, buf, dh);
764 ath_free_tx_skb(sc->tgt_htc_handle,EndPt,buf);
768 bf->bf_endpt = EndPt;
769 bf->bf_cookie = dh->cookie;
771 if (tid->flag & TID_AGGR_ENABLED)
772 ath_tgt_handle_aggr(sc, bf);
774 ath_tgt_handle_normal(sc, bf);
777 static void tgt_HTCRecv_cabhandler(HTC_ENDPOINT_ID EndPt, adf_nbuf_t hdr_buf,
778 adf_nbuf_t buf, void *ServiceCtx)
780 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)ServiceCtx;
781 struct ath_hal *ah = sc->sc_ah;
785 #ifdef ATH_ENABLE_CABQ
786 tsf = ath_hal_gettsf64(ah);
787 tmp = tsf - sc->sc_swba_tsf;
789 if ( tmp > ATH_CABQ_HANDLING_THRESHOLD ) {
790 HTC_ReturnBuffers(sc->tgt_htc_handle, EndPt, buf);
794 tgt_HTCRecvMessageHandler(EndPt, hdr_buf, buf, ServiceCtx);
798 /***********************/
799 /* Descriptor Handling */
800 /***********************/
802 static a_int32_t ath_descdma_setup(struct ath_softc_tgt *sc,
803 struct ath_descdma *dd, ath_bufhead *head,
804 const char *name, a_int32_t nbuf, a_int32_t ndesc,
805 a_uint32_t bfSize, a_uint32_t descSize)
807 #define DS2PHYS(_dd, _ds) \
808 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
812 a_int32_t i, bsize, error;
817 dd->dd_desc_len = descSize * nbuf * ndesc;
819 dd->dd_desc = adf_os_dmamem_alloc(sc->sc_dev,
820 dd->dd_desc_len, 1, &dd->dd_desc_dmamap);
821 dd->dd_desc_paddr = adf_os_dmamem_map2addr(dd->dd_desc_dmamap);
822 if (dd->dd_desc == NULL) {
828 bsize = bfSize * nbuf;
829 bf = adf_os_mem_alloc(bsize);
834 adf_os_mem_set(bf, 0, bsize);
837 bf_addr = (a_uint8_t *)bf;
838 ds_addr = (a_uint8_t *)ds;
840 asf_tailq_init(head);
842 for (i = 0; i < nbuf; i++) {
845 if (adf_nbuf_dmamap_create( sc->sc_dev, &bf->bf_dmamap) != A_STATUS_OK) {
849 bf->bf_desc = bf->bf_descarr = bf->bf_lastds = ds;
850 for (j = 0; j < ndesc; j++)
851 ATH_BUF_SET_DESC_PHY_ADDR_WITH_IDX(bf, j, (ds_addr + (j*descSize)));
853 ATH_BUF_SET_DESC_PHY_ADDR(bf, ATH_BUF_GET_DESC_PHY_ADDR_WITH_IDX(bf, 0));
855 adf_nbuf_queue_init(&bf->bf_skbhead);
856 asf_tailq_insert_tail(head, bf, bf_list);
859 ds_addr += (ndesc * descSize);
860 bf = (struct ath_buf *)bf_addr;
861 ds = (struct ath_desc *)ds_addr;
866 adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len,
867 1, dd->dd_desc, dd->dd_desc_dmamap);
869 adf_os_mem_set(dd, 0, sizeof(*dd));
876 static void ath_descdma_cleanup(struct ath_softc_tgt *sc,
877 struct ath_descdma *dd,
878 ath_bufhead *head, a_int32_t dir)
881 struct ieee80211_node_target *ni;
883 asf_tailq_foreach(bf, head, bf_list) {
884 if (adf_nbuf_queue_len(&bf->bf_skbhead) != 0) {
885 adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap, dir);
886 while(adf_nbuf_queue_len(&bf->bf_skbhead) != 0) {
888 adf_nbuf_queue_remove(&bf->bf_skbhead));
891 } else if (bf->bf_skb != NULL) {
892 adf_nbuf_unmap(sc->sc_dev,bf->bf_dmamap, dir);
893 ath_free_rx_skb(sc, bf->bf_skb);
897 adf_nbuf_dmamap_destroy(sc->sc_dev, bf->bf_dmamap);
903 adf_os_dmamem_free(sc->sc_dev, dd->dd_desc_len,
904 1, dd->dd_desc, dd->dd_desc_dmamap);
906 asf_tailq_init(head);
907 adf_os_mem_free(dd->dd_bufptr);
908 adf_os_mem_set(dd, 0, sizeof(*dd));
911 static a_int32_t ath_desc_alloc(struct ath_softc_tgt *sc)
913 #define DS2PHYS(_dd, _ds) \
914 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
917 struct ath_tx_buf *bf;
919 if(ath_numrxbufs == -1)
920 ath_numrxbufs = ATH_RXBUF;
922 if (ath_numrxdescs == -1)
923 ath_numrxdescs = ATH_RXDESC;
925 error = ath_descdma_setup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
926 "rx", ath_numrxdescs, 1,
927 sizeof(struct ath_rx_buf),
928 sizeof(struct ath_rx_desc));
933 struct ath_descdma *dd = &sc->sc_rxdma;
934 struct ath_rx_desc *ds = (struct ath_rx_desc *)dd->dd_desc;
935 struct ath_rx_desc *ds_prev = NULL;
937 asf_tailq_init(&sc->sc_rxdesc);
938 asf_tailq_init(&sc->sc_rxdesc_idle);
940 for (i = 0; i < ath_numrxdescs; i++, ds++) {
942 if (ds->ds_nbuf != ADF_NBUF_NULL) {
943 ds->ds_nbuf = ADF_NBUF_NULL;
946 if (adf_nbuf_dmamap_create(sc->sc_dev, &ds->ds_dmap) != A_STATUS_OK) {
950 ds->ds_daddr = DS2PHYS(&sc->sc_rxdma, ds);
953 ds_prev->ds_link = ds->ds_daddr;
959 asf_tailq_insert_tail(&sc->sc_rxdesc, ds, ds_list);
962 error = ath_descdma_setup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
963 "tx", ATH_TXBUF + 1, ATH_TXDESC,
964 sizeof(struct ath_tx_buf),
965 sizeof(struct ath_tx_desc));
967 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
968 ADF_OS_DMA_FROM_DEVICE);
972 error = ath_descdma_setup(sc, &sc->sc_bdma, (ath_bufhead *)&sc->sc_bbuf,
973 "beacon", ATH_BCBUF, 1,
974 sizeof(struct ath_tx_buf),
975 sizeof(struct ath_tx_desc));
977 ath_descdma_cleanup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
978 ADF_OS_DMA_TO_DEVICE);
979 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
980 ADF_OS_DMA_FROM_DEVICE);
984 bf = asf_tailq_first(&sc->sc_txbuf);
985 bf->bf_isaggr = bf->bf_isretried = bf->bf_retries = 0;
986 asf_tailq_remove(&sc->sc_txbuf, bf, bf_list);
988 sc->sc_txbuf_held = bf;
995 static void ath_desc_free(struct ath_softc_tgt *sc)
997 asf_tailq_insert_tail(&sc->sc_txbuf, sc->sc_txbuf_held, bf_list);
999 sc->sc_txbuf_held = NULL;
1001 if (sc->sc_txdma.dd_desc_len != 0)
1002 ath_descdma_cleanup(sc, &sc->sc_txdma, (ath_bufhead *)&sc->sc_txbuf,
1003 ADF_OS_DMA_TO_DEVICE);
1004 if (sc->sc_rxdma.dd_desc_len != 0)
1005 ath_descdma_cleanup(sc, &sc->sc_rxdma, (ath_bufhead *)&sc->sc_rxbuf,
1006 ADF_OS_DMA_FROM_DEVICE);
1009 /**********************/
1010 /* Interrupt Handling */
1011 /**********************/
1013 adf_os_irq_resp_t ath_intr(adf_drv_handle_t hdl)
1015 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)hdl;
1016 struct ath_hal *ah = sc->sc_ah;
1020 return ADF_OS_IRQ_NONE;
1022 if (!ath_hal_intrpend(ah))
1023 return ADF_OS_IRQ_NONE;
1025 ath_hal_getisr(ah, &status);
1027 status &= sc->sc_imask;
1029 if (status & HAL_INT_FATAL) {
1030 ath_hal_intrset(ah, 0);
1031 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_fataltq);
1033 if (status & HAL_INT_SWBA) {
1034 WMI_SWBA_EVENT swbaEvt;
1035 struct ath_txq *txq = ATH_TXQ(sc, 8);
1037 swbaEvt.tsf = ath_hal_gettsf64(ah);
1038 swbaEvt.beaconPendingCount = ath_hal_numtxpending(ah, sc->sc_bhalq);
1039 sc->sc_swba_tsf = ath_hal_gettsf64(ah);
1041 wmi_event(sc->tgt_wmi_handle,
1044 sizeof(WMI_SWBA_EVENT));
1046 ath_tx_draintxq(sc, txq);
1049 if (status & HAL_INT_RXORN)
1050 sc->sc_int_stats.ast_rxorn++;
1052 if (status & HAL_INT_RXEOL)
1053 sc->sc_int_stats.ast_rxeol++;
1055 if (status & (HAL_INT_RX | HAL_INT_RXEOL | HAL_INT_RXORN)) {
1056 if (status & HAL_INT_RX)
1057 sc->sc_int_stats.ast_rx++;
1059 ath_uapsd_processtriggers(sc);
1061 sc->sc_imask &= ~HAL_INT_RX;
1062 ath_hal_intrset(ah, sc->sc_imask);
1064 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_rxtq);
1067 if (status & HAL_INT_TXURN) {
1068 sc->sc_int_stats.ast_txurn++;
1069 ath_hal_updatetxtriglevel(ah, AH_TRUE);
1072 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_txtq);
1074 if (status & HAL_INT_BMISS) {
1075 ATH_SCHEDULE_TQUEUE(sc->sc_dev, &sc->sc_bmisstq);
1078 if (status & HAL_INT_GTT)
1079 sc->sc_int_stats.ast_txto++;
1081 if (status & HAL_INT_CST)
1082 sc->sc_int_stats.ast_cst++;
1085 return ADF_OS_IRQ_HANDLED;
1088 static void ath_fatal_tasklet(TQUEUE_ARG data )
1090 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
1092 wmi_event(sc->tgt_wmi_handle, WMI_FATAL_EVENTID, NULL, 0);
1095 static void ath_bmiss_tasklet(TQUEUE_ARG data)
1097 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)data;
1099 wmi_event(sc->tgt_wmi_handle, WMI_BMISS_EVENTID, NULL, 0);
1106 static void ath_enable_intr_tgt(void *Context, A_UINT16 Command,
1107 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1109 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1110 struct ath_hal *ah = sc->sc_ah;
1114 intr = (*(a_uint32_t *)data);
1116 intr = adf_os_ntohl(intr);
1118 if (intr & HAL_INT_SWBA) {
1119 sc->sc_imask |= HAL_INT_SWBA;
1121 sc->sc_imask &= ~HAL_INT_SWBA;
1124 if (intr & HAL_INT_BMISS) {
1125 sc->sc_imask |= HAL_INT_BMISS;
1128 ath_hal_intrset(ah, sc->sc_imask);
1129 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
1132 static void ath_init_tgt(void *Context, A_UINT16 Command,
1133 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1135 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1136 struct ath_hal *ah = sc->sc_ah;
1138 sc->sc_imask = HAL_INT_RX | HAL_INT_TX
1139 | HAL_INT_RXEOL | HAL_INT_RXORN
1140 | HAL_INT_FATAL | HAL_INT_GLOBAL;
1142 sc->sc_imask |= HAL_INT_GTT;
1144 if (ath_hal_htsupported(ah))
1145 sc->sc_imask |= HAL_INT_CST;
1147 adf_os_setup_intr(sc->sc_dev, ath_intr);
1148 ath_hal_intrset(ah, sc->sc_imask);
1150 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1153 static void ath_int_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1154 A_UINT8 *data, a_int32_t datalen)
1156 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1158 struct fusion_stats {
1160 a_uint32_t ast_rxorn;
1161 a_uint32_t ast_rxeol;
1162 a_uint32_t ast_txurn;
1163 a_uint32_t ast_txto;
1167 struct fusion_stats stats;
1169 stats.ast_rx = sc->sc_int_stats.ast_rx;
1170 stats.ast_rxorn = sc->sc_int_stats.ast_rxorn;
1171 stats.ast_rxeol = sc->sc_int_stats.ast_rxeol;
1172 stats.ast_txurn = sc->sc_int_stats.ast_txurn;
1173 stats.ast_txto = sc->sc_int_stats.ast_txto;
1174 stats.ast_cst = sc->sc_int_stats.ast_cst;
1176 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1179 static void ath_tx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1180 A_UINT8 *data, a_int32_t datalen)
1182 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1184 struct fusion_stats {
1185 a_uint32_t ast_tx_xretries;
1186 a_uint32_t ast_tx_fifoerr;
1187 a_uint32_t ast_tx_filtered;
1188 a_uint32_t ast_tx_timer_exp;
1189 a_uint32_t ast_tx_shortretry;
1190 a_uint32_t ast_tx_longretry;
1192 a_uint32_t tx_qnull;
1193 a_uint32_t tx_noskbs;
1194 a_uint32_t tx_nobufs;
1197 struct fusion_stats stats;
1199 stats.ast_tx_xretries = sc->sc_tx_stats.ast_tx_xretries;
1200 stats.ast_tx_fifoerr = sc->sc_tx_stats.ast_tx_fifoerr;
1201 stats.ast_tx_filtered = sc->sc_tx_stats.ast_tx_filtered;
1202 stats.ast_tx_timer_exp = sc->sc_tx_stats.ast_tx_timer_exp;
1203 stats.ast_tx_shortretry = sc->sc_tx_stats.ast_tx_shortretry;
1204 stats.ast_tx_longretry = sc->sc_tx_stats.ast_tx_longretry;
1205 stats.tx_qnull = sc->sc_tx_stats.tx_qnull;
1206 stats.tx_noskbs = sc->sc_tx_stats.tx_noskbs;
1207 stats.tx_nobufs = sc->sc_tx_stats.tx_nobufs;
1209 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1212 static void ath_rx_stats_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1213 A_UINT8 *data, a_int32_t datalen)
1215 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1217 struct fusion_stats {
1218 a_uint32_t ast_rx_nobuf;
1219 a_uint32_t ast_rx_send;
1220 a_uint32_t ast_rx_done;
1223 struct fusion_stats stats;
1225 stats.ast_rx_nobuf = sc->sc_rx_stats.ast_rx_nobuf;
1226 stats.ast_rx_send = sc->sc_rx_stats.ast_rx_send;
1227 stats.ast_rx_done = sc->sc_rx_stats.ast_rx_done;
1229 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &stats, sizeof(stats));
1232 static void ath_get_tgt_version(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1233 A_UINT8 *data, a_int32_t datalen)
1235 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1236 struct wmi_fw_version ver;
1238 ver.major = ATH_VERSION_MAJOR;
1239 ver.minor = ATH_VERSION_MINOR;
1241 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &ver, sizeof(ver));
1244 static void ath_enable_aggr_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1245 A_UINT8 *data, a_int32_t datalen)
1247 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1248 struct ath_aggr_info *aggr = (struct ath_aggr_info *)data;
1249 a_uint8_t nodeindex = aggr->nodeindex;
1250 a_uint8_t tidno = aggr->tidno;
1251 struct ath_node_target *an = NULL ;
1252 struct ath_atx_tid *tid = NULL;
1254 if (nodeindex >= TARGET_NODE_MAX) {
1258 an = &sc->sc_sta[nodeindex];
1259 if (!an->an_valid) {
1263 if (tidno >= WME_NUM_TID) {
1264 adf_os_print("[%s] enable_aggr with invalid tid %d(node = %d)\n",
1265 __FUNCTION__, tidno, nodeindex);
1269 tid = ATH_AN_2_TID(an, tidno);
1271 if (aggr->aggr_enable) {
1272 tid->flag |= TID_AGGR_ENABLED;
1273 } else if ( tid->flag & TID_AGGR_ENABLED ) {
1274 tid->flag &= ~TID_AGGR_ENABLED;
1275 ath_tgt_tx_cleanup(sc, an, tid, 1);
1278 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1281 static void ath_ic_update_tgt(void *Context,A_UINT16 Command, A_UINT16 SeqNo,
1282 A_UINT8 *data, a_int32_t datalen)
1284 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1285 struct ieee80211com_target *ic = (struct ieee80211com_target * )data;
1286 struct ieee80211com_target *ictgt = &sc->sc_ic ;
1288 adf_os_mem_copy(ictgt, ic, sizeof(struct ieee80211com_target));
1290 ictgt->ic_ampdu_limit = adf_os_ntohl(ic->ic_ampdu_limit);
1292 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1295 static void ath_vap_create_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1296 A_UINT8 *data, a_int32_t datalen)
1298 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1299 struct ieee80211vap_target *vap;
1300 a_uint8_t vap_index;
1302 vap = (struct ieee80211vap_target *)data;
1304 vap->iv_rtsthreshold = adf_os_ntohs(vap->iv_rtsthreshold);
1305 vap->iv_opmode = adf_os_ntohl(vap->iv_opmode);
1307 vap_index = vap->iv_vapindex;
1309 adf_os_assert(sc->sc_vap[vap_index].av_valid == 0);
1311 adf_os_mem_copy(&(sc->sc_vap[vap_index].av_vap), vap,
1314 sc->sc_vap[vap_index].av_bcbuf = asf_tailq_first(&(sc->sc_bbuf));
1315 sc->sc_vap[vap_index].av_valid = 1;
1317 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1320 static void ath_node_create_tgt(void *Context, A_UINT16 Command,
1321 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1323 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1324 struct ieee80211_node_target *node;
1325 a_uint8_t vap_index;
1326 a_uint8_t node_index;
1328 node = (struct ieee80211_node_target *)data;
1330 node_index = node->ni_nodeindex;
1332 node->ni_htcap = adf_os_ntohs(node->ni_htcap);
1333 node->ni_flags = adf_os_ntohs(node->ni_flags);
1334 node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu);
1336 adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node,
1339 vap_index = sc->sc_sta[node_index].ni.ni_vapindex;
1340 sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap);
1341 if(sc->sc_sta[node_index].ni.ni_is_vapnode == 1)
1342 sc->sc_vap[vap_index].av_vap.iv_nodeindex = node_index;
1344 sc->sc_sta[node_index].an_valid = 1;
1345 sc->sc_sta[node_index].ni.ni_txseqmgmt = 0;
1346 sc->sc_sta[node_index].ni.ni_iv16 = 0;
1347 sc->sc_sta[node_index].ni.ni_iv32 = 0;
1349 owl_tgt_node_init(&sc->sc_sta[node_index]);
1351 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1354 static void ath_node_cleanup_tgt(void *Context, A_UINT16 Command,
1355 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1357 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1358 a_uint8_t node_index;
1359 a_uint8_t *nodedata;
1361 nodedata = (a_uint8_t *)data;
1362 node_index = *nodedata;
1363 sc->sc_sta[node_index].an_valid = 0;
1365 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1368 static void ath_node_update_tgt(void *Context, A_UINT16 Command,
1369 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1371 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1372 struct ieee80211_node_target *node;
1373 a_uint8_t vap_index;
1374 a_uint8_t node_index;
1376 node = (struct ieee80211_node_target *)data;
1378 node_index = node->ni_nodeindex;
1380 node->ni_htcap = adf_os_ntohs(node->ni_htcap);
1381 node->ni_flags = adf_os_ntohs(node->ni_flags);
1382 node->ni_maxampdu = adf_os_ntohs(node->ni_maxampdu);
1384 adf_os_mem_copy(&(sc->sc_sta[node_index].ni), node,
1387 vap_index = sc->sc_sta[node_index].ni.ni_vapindex;
1388 sc->sc_sta[node_index].ni.ni_vap = &(sc->sc_vap[vap_index].av_vap);
1390 sc->sc_sta[node_index].ni.ni_txseqmgmt = 0;
1391 sc->sc_sta[node_index].ni.ni_iv16 = 0;
1392 sc->sc_sta[node_index].ni.ni_iv32 = 0;
1394 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1397 static void ath_hal_reg_read_tgt(void *Context, A_UINT16 Command,
1398 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1400 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1401 struct ath_hal *ah = sc->sc_ah;
1406 for (i = 0; i < datalen; i += sizeof(a_int32_t)) {
1407 addr = *(a_uint32_t *)(data + i);
1408 addr = adf_os_ntohl(addr);
1410 if ((addr & 0xffffe000) == 0x2000) {
1412 ath_hal_reg_read_target(ah, addr);
1413 if (!ath_hal_wait(ah, 0x407c, 0x00030000, 0)) {
1414 adf_os_print("SEEPROM Read fail: 0x%08x\n", addr);
1416 val[i/sizeof(a_int32_t)] = (ath_hal_reg_read_target(ah, 0x407c) & 0x0000ffff);
1417 } else if (addr > 0xffff) {
1418 val[i/sizeof(a_int32_t)] = *(a_uint32_t *)addr;
1420 val[i/sizeof(a_int32_t)] = ath_hal_reg_read_target(ah, addr);
1422 val[i/sizeof(a_int32_t)] = adf_os_ntohl(val[i/sizeof(a_int32_t)]);
1425 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, &val[0], datalen);
1428 static void ath_hal_reg_write_tgt(void *Context, A_UINT16 Command,
1429 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1431 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1432 struct ath_hal *ah = sc->sc_ah;
1434 struct registerWrite {
1439 for (i = 0; i < datalen; i += sizeof(struct registerWrite)) {
1440 t = (struct registerWrite *)(data+i);
1442 if( t->reg > 0xffff ) {
1443 a_uint32_t *pReg = (a_uint32_t *)t->reg;
1447 #if defined(PROJECT_K2)
1448 if( t->reg == 0x50040 ) {
1449 static uint8_t flg=0;
1453 A_UART_HWINIT(117*1000*1000, 19200);
1459 #if defined(PROJECT_K2)
1460 if( t->reg == 0x7014 ) {
1461 static uint8_t resetPLL = 0;
1464 if( resetPLL == 0 ) {
1466 pReg = (a_uint32_t *)t->reg;
1468 ath_hal_reg_write_target(ah, 0x786c,
1469 ath_hal_reg_read_target(ah,0x786c) | 0x6000000);
1470 ath_hal_reg_write_target(ah, 0x786c,
1471 ath_hal_reg_read_target(ah,0x786c) & (~0x6000000));
1477 #elif defined(PROJECT_MAGPIE) && !defined (FPGA)
1478 if( t->reg == 0x7014 ){
1479 static uint8_t resetPLL = 0;
1481 if( resetPLL == 0 ) {
1482 ath_hal_reg_write_target(ah, 0x7890,
1483 ath_hal_reg_read_target(ah,0x7890) | 0x1800000);
1484 ath_hal_reg_write_target(ah, 0x7890,
1485 ath_hal_reg_read_target(ah,0x7890) & (~0x1800000));
1490 ath_hal_reg_write_target(ah,t->reg,t->val);
1494 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1497 static void ath_vap_delete_tgt(void *Context, A_UINT16 Command,
1498 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1500 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1501 a_uint8_t vap_index;
1503 vap_index = *(a_uint8_t *)data;
1505 sc->sc_vap[vap_index].av_valid = 0;
1506 sc->sc_vap[vap_index].av_bcbuf = NULL;
1507 ath_node_vdelete_tgt(sc, vap_index);
1508 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1511 static void ath_disable_intr_tgt(void *Context, A_UINT16 Command,
1512 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1514 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1515 struct ath_hal *ah = sc->sc_ah;
1517 ath_hal_intrset(ah, 0);
1518 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo,NULL, 0);
1521 static void ath_flushrecv_tgt(void *Context, A_UINT16 Command,
1522 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1524 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1525 struct ath_rx_buf *bf;
1527 asf_tailq_foreach(bf, &sc->sc_rxbuf, bf_list)
1528 if (bf->bf_skb != NULL) {
1529 adf_nbuf_unmap(sc->sc_dev, bf->bf_dmamap,
1530 ADF_OS_DMA_FROM_DEVICE);
1531 ath_free_rx_skb(sc, adf_nbuf_queue_remove(&bf->bf_skbhead));
1535 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1538 static void ath_tx_draintxq_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1539 A_UINT8 *data, a_int32_t datalen)
1541 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1542 a_uint32_t q = *(a_uint32_t *)data;
1543 struct ath_txq *txq = NULL;
1545 q = adf_os_ntohl(q);
1546 txq = ATH_TXQ(sc, q);
1548 ath_tx_draintxq(sc, txq);
1549 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1552 static void ath_draintxq_tgt(void *Context, A_UINT16 Command,
1553 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1555 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1556 HAL_BOOL b = (HAL_BOOL) *(a_int32_t *)data;
1558 ath_draintxq(Context, b);
1559 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1562 static void ath_aborttx_dma_tgt(void *Context, A_UINT16 Command,
1563 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1565 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1567 ath_hal_aborttxdma(sc->sc_ah);
1568 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1571 static void ath_aborttxq_tgt(void *Context, A_UINT16 Command,
1572 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1575 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1578 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
1579 if (ATH_TXQ_SETUP(sc, i))
1580 ath_tx_draintxq(sc, ATH_TXQ(sc,i));
1583 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1586 static void ath_stop_tx_dma_tgt(void *Context, A_UINT16 Command,
1587 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1589 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1590 struct ath_hal *ah = sc->sc_ah;
1594 q = *(a_uint32_t *)data;
1596 q = adf_os_ntohl(q);
1597 ath_hal_stoptxdma(ah, q);
1598 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1601 static void ath_startrecv_tgt(void *Context, A_UINT16 Command,
1602 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1605 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1608 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1611 static void ath_stoprecv_tgt(void *Context, A_UINT16 Command,
1612 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1614 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1615 struct ath_hal *ah = sc->sc_ah;
1617 ath_hal_stoppcurecv(ah);
1618 ath_hal_setrxfilter(ah, 0);
1619 ath_hal_stopdmarecv(ah);
1621 sc->sc_rxlink = NULL;
1622 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1625 static void ath_setcurmode_tgt(void *Context, A_UINT16 Command,
1626 A_UINT16 SeqNo, A_UINT8 *data, a_int32_t datalen)
1628 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1631 mode= *((a_uint16_t *)data);
1632 mode = adf_os_ntohs(mode);
1634 ath_setcurmode(sc, mode);
1636 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1639 static void ath_detach_tgt(void *Context, A_UINT16 Command, A_UINT16 SeqNo,
1640 A_UINT8 *data, a_int32_t datalen)
1642 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1643 struct ath_hal *ah = sc->sc_ah;
1647 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1648 adf_os_mem_free(sc);
1651 static void handle_echo_command(void *pContext, A_UINT16 Command,
1652 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1654 wmi_cmd_rsp(pContext, WMI_ECHO_CMDID, SeqNo, buffer, Length);
1657 static void handle_rc_state_change_cmd(void *Context, A_UINT16 Command,
1658 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1661 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1662 struct wmi_rc_state_change_cmd *wmi_data = (struct wmi_rc_state_change_cmd *)buffer;
1664 a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag);
1666 ath_rate_newstate(sc, &sc->sc_vap[wmi_data->vap_index].av_vap,
1667 wmi_data->vap_state,
1671 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1674 static void handle_rc_rate_update_cmd(void *Context, A_UINT16 Command,
1675 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1677 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1678 struct wmi_rc_rate_update_cmd *wmi_data = (struct wmi_rc_rate_update_cmd *)buffer;
1680 a_uint32_t capflag = adf_os_ntohl(wmi_data->capflag);
1682 ath_rate_node_update(sc, &sc->sc_sta[wmi_data->node_index],
1687 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1690 static void dispatch_magpie_sys_cmds(void *pContext, A_UINT16 Command,
1691 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1696 static void ath_rc_mask_tgt(void *Context, A_UINT16 Command,
1697 A_UINT16 SeqNo, A_UINT8 *buffer, a_int32_t Length)
1699 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)Context;
1700 struct wmi_rc_rate_mask_cmd *wmi_data = (struct wmi_rc_rate_mask_cmd *)buffer;
1703 idx = wmi_data->vap_index;
1704 band = wmi_data->band;
1706 sc->sc_vap[idx].av_rate_mask[band] = adf_os_ntohl(wmi_data->mask);
1708 if (sc->sc_vap[idx].av_rate_mask[band]) {
1709 for (i = 0; i < RATE_TABLE_SIZE; i++) {
1710 if ((1 << i) & sc->sc_vap[idx].av_rate_mask[band]) {
1711 sc->sc_vap[idx].av_minrateidx[band] = i;
1716 sc->sc_vap[idx].av_minrateidx[band] = 0;
1719 wmi_cmd_rsp(sc->tgt_wmi_handle, Command, SeqNo, NULL, 0);
1722 static WMI_DISPATCH_ENTRY Magpie_Sys_DispatchEntries[] =
1724 {handle_echo_command, WMI_ECHO_CMDID, 0},
1725 {dispatch_magpie_sys_cmds, WMI_ACCESS_MEMORY_CMDID, 0},
1726 {ath_get_tgt_version, WMI_GET_FW_VERSION, 0},
1727 {ath_disable_intr_tgt, WMI_DISABLE_INTR_CMDID, 0},
1728 {ath_enable_intr_tgt, WMI_ENABLE_INTR_CMDID, 0},
1729 {ath_init_tgt, WMI_ATH_INIT_CMDID, 0},
1730 {ath_aborttxq_tgt, WMI_ABORT_TXQ_CMDID, 0},
1731 {ath_stop_tx_dma_tgt, WMI_STOP_TX_DMA_CMDID, 0},
1732 {ath_aborttx_dma_tgt, WMI_ABORT_TX_DMA_CMDID, 0},
1733 {ath_tx_draintxq_tgt, WMI_DRAIN_TXQ_CMDID, 0},
1734 {ath_draintxq_tgt, WMI_DRAIN_TXQ_ALL_CMDID, 0},
1735 {ath_startrecv_tgt, WMI_START_RECV_CMDID, 0},
1736 {ath_stoprecv_tgt, WMI_STOP_RECV_CMDID, 0},
1737 {ath_flushrecv_tgt, WMI_FLUSH_RECV_CMDID, 0},
1738 {ath_setcurmode_tgt, WMI_SET_MODE_CMDID, 0},
1739 {ath_node_create_tgt, WMI_NODE_CREATE_CMDID, 0},
1740 {ath_node_cleanup_tgt, WMI_NODE_REMOVE_CMDID, 0},
1741 {ath_vap_delete_tgt, WMI_VAP_REMOVE_CMDID, 0},
1742 {ath_vap_create_tgt, WMI_VAP_CREATE_CMDID, 0},
1743 {ath_hal_reg_read_tgt, WMI_REG_READ_CMDID, 0},
1744 {ath_hal_reg_write_tgt, WMI_REG_WRITE_CMDID, 0},
1745 {handle_rc_state_change_cmd, WMI_RC_STATE_CHANGE_CMDID, 0},
1746 {handle_rc_rate_update_cmd, WMI_RC_RATE_UPDATE_CMDID, 0},
1747 {ath_ic_update_tgt, WMI_TARGET_IC_UPDATE_CMDID, 0},
1748 {ath_enable_aggr_tgt, WMI_TX_AGGR_ENABLE_CMDID, 0},
1749 {ath_detach_tgt, WMI_TGT_DETACH_CMDID, 0},
1750 {ath_node_update_tgt, WMI_NODE_UPDATE_CMDID, 0},
1751 {ath_int_stats_tgt, WMI_INT_STATS_CMDID, 0},
1752 {ath_tx_stats_tgt, WMI_TX_STATS_CMDID, 0},
1753 {ath_rx_stats_tgt, WMI_RX_STATS_CMDID, 0},
1754 {ath_rc_mask_tgt, WMI_BITRATE_MASK_CMDID, 0},
1761 static void htc_setup_comp(void)
1765 static A_UINT8 tgt_ServiceConnect(HTC_SERVICE *pService,
1766 HTC_ENDPOINT_ID eid,
1770 a_int32_t *pLengthOut)
1772 struct ath_softc_tgt *sc = (struct ath_softc_tgt *)pService->ServiceCtx;
1774 switch(pService->ServiceID) {
1775 case WMI_CONTROL_SVC:
1776 sc->wmi_command_ep= eid;
1778 case WMI_BEACON_SVC:
1790 case WMI_DATA_VO_SVC:
1791 sc->data_VO_ep = eid;
1793 case WMI_DATA_VI_SVC:
1794 sc->data_VI_ep = eid;
1796 case WMI_DATA_BE_SVC:
1797 sc->data_BE_ep = eid;
1799 case WMI_DATA_BK_SVC:
1800 sc->data_BK_ep = eid;
1806 return HTC_SERVICE_SUCCESS;
1809 static void tgt_reg_service(struct ath_softc_tgt *sc, HTC_SERVICE *svc,
1810 int svcId, HTC_SERVICE_ProcessRecvMsg recvMsg)
1812 svc->ProcessRecvMsg = recvMsg;
1813 svc->ProcessSendBufferComplete = tgt_HTCSendCompleteHandler;
1814 svc->ProcessConnect = tgt_ServiceConnect;
1815 svc->MaxSvcMsgSize = 1600;
1816 svc->TrailerSpcCheckLimit = 0;
1817 svc->ServiceID = svcId;
1818 svc->ServiceCtx = sc;
1819 HTC_RegisterService(sc->tgt_htc_handle, svc);
1822 static void tgt_hif_htc_wmi_init(struct ath_softc_tgt *sc)
1824 HTC_CONFIG htc_conf;
1825 WMI_SVC_CONFIG wmiConfig;
1826 WMI_DISPATCH_TABLE *Magpie_Sys_Commands_Tbl;
1828 /* Init dynamic buf pool */
1829 sc->pool_handle = BUF_Pool_init(sc->sc_hdl);
1831 /* Init target-side HIF */
1832 sc->tgt_hif_handle = HIF_init(0);
1834 /* Init target-side HTC */
1835 htc_conf.HIFHandle = sc->tgt_hif_handle;
1836 htc_conf.CreditSize = 320;
1837 htc_conf.CreditNumber = ATH_TXBUF;
1838 htc_conf.OSHandle = sc->sc_hdl;
1839 htc_conf.PoolHandle = sc->pool_handle;
1840 sc->tgt_htc_handle = HTC_init(htc_setup_comp, &htc_conf);
1841 #if defined(PROJECT_MAGPIE)
1842 init_htc_handle = sc->tgt_htc_handle;
1845 tgt_reg_service(sc, &sc->htc_beacon_service, WMI_BEACON_SVC, tgt_HTCRecv_beaconhandler);
1846 tgt_reg_service(sc, &sc->htc_cab_service, WMI_CAB_SVC, tgt_HTCRecv_cabhandler);
1847 tgt_reg_service(sc, &sc->htc_uapsd_service, WMI_UAPSD_SVC, tgt_HTCRecv_uapsdhandler);
1848 tgt_reg_service(sc, &sc->htc_mgmt_service, WMI_MGMT_SVC, tgt_HTCRecv_mgmthandler);
1849 tgt_reg_service(sc, &sc->htc_data_BE_service, WMI_DATA_BE_SVC, tgt_HTCRecvMessageHandler);
1850 tgt_reg_service(sc, &sc->htc_data_BK_service, WMI_DATA_BK_SVC, tgt_HTCRecvMessageHandler);
1851 tgt_reg_service(sc, &sc->htc_data_VI_service, WMI_DATA_VI_SVC, tgt_HTCRecvMessageHandler);
1852 tgt_reg_service(sc, &sc->htc_data_VO_service, WMI_DATA_VO_SVC, tgt_HTCRecvMessageHandler);
1854 /* Init target-side WMI */
1855 Magpie_Sys_Commands_Tbl = (WMI_DISPATCH_TABLE *)adf_os_mem_alloc(sizeof(WMI_DISPATCH_TABLE));
1856 adf_os_mem_zero(Magpie_Sys_Commands_Tbl, sizeof(WMI_DISPATCH_TABLE));
1857 Magpie_Sys_Commands_Tbl->NumberOfEntries = WMI_DISPATCH_ENTRY_COUNT(Magpie_Sys_DispatchEntries);
1858 Magpie_Sys_Commands_Tbl->pTable = Magpie_Sys_DispatchEntries;
1860 adf_os_mem_zero(&wmiConfig, sizeof(WMI_SVC_CONFIG));
1861 wmiConfig.HtcHandle = sc->tgt_htc_handle;
1862 wmiConfig.PoolHandle = sc->pool_handle;
1863 wmiConfig.MaxCmdReplyEvts = ATH_WMI_MAX_CMD_REPLY;
1864 wmiConfig.MaxEventEvts = ATH_WMI_MAX_EVENTS;
1866 sc->tgt_wmi_handle = WMI_Init(&wmiConfig);
1867 Magpie_Sys_Commands_Tbl->pContext = sc;
1868 WMI_RegisterDispatchTable(sc->tgt_wmi_handle, Magpie_Sys_Commands_Tbl);
1870 HTC_NotifyTargetInserted(sc->tgt_htc_handle);
1872 /* Start HTC messages exchange */
1873 HTC_Ready(sc->tgt_htc_handle);
1876 a_int32_t ath_tgt_attach(a_uint32_t devid, struct ath_softc_tgt *sc, adf_os_device_t osdev)
1880 a_int32_t error = 0, i, flags = 0;
1883 adf_os_pci_config_read8(osdev, ATH_PCI_CACHE_LINE_SIZE, &csz);
1887 sc->sc_cachelsz = csz << 2;
1892 ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_rxtq, ath_tgt_rx_tasklet, sc);
1893 ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_txtq, owl_tgt_tx_tasklet, sc);
1894 ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_bmisstq, ath_bmiss_tasklet, sc);
1895 ATH_INIT_TQUEUE(sc->sc_dev, &sc->sc_fataltq, ath_fatal_tasklet, sc);
1897 flags |= AH_USE_EEPROM;
1898 ah = _ath_hal_attach_tgt(devid, sc, sc->sc_dev, flags, &status);
1905 tgt_hif_htc_wmi_init(sc);
1907 sc->sc_bhalq = HAL_NUM_TX_QUEUES - 1;
1909 ath_rate_setup(sc, IEEE80211_MODE_11NA);
1910 ath_rate_setup(sc, IEEE80211_MODE_11NG);
1912 sc->sc_rc = ath_rate_attach(sc);
1913 if (sc->sc_rc == NULL) {
1918 for (i=0; i < TARGET_NODE_MAX; i++) {
1919 sc->sc_sta[i].an_rcnode = adf_os_mem_alloc(sc->sc_rc->arc_space);
1922 error = ath_desc_alloc(sc);
1927 BUF_Pool_create_pool(sc->pool_handle, POOL_ID_WLAN_RX_BUF, ath_numrxdescs, 1664);
1929 ath_tgt_txq_setup(sc);
1931 ath_hal_intrset(ah,0);
1941 static void tgt_hif_htc_wmi_shutdown(struct ath_softc_tgt *sc)
1943 HTC_NotifyTargetDetached(sc->tgt_htc_handle);
1945 WMI_Shutdown(sc->tgt_wmi_handle);
1946 HTC_Shutdown(sc->tgt_htc_handle);
1947 HIF_shutdown(sc->tgt_hif_handle);
1948 BUF_Pool_shutdown(sc->pool_handle);
1951 a_int32_t ath_detach(struct ath_softc_tgt *sc)
1953 tgt_hif_htc_wmi_shutdown(sc);