2 * This file contains idle entry/exit functions for POWER7,
3 * POWER8 and POWER9 CPUs.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
11 #include <linux/threads.h>
12 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/thread_info.h>
16 #include <asm/ppc_asm.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/ppc-opcode.h>
19 #include <asm/hw_irq.h>
20 #include <asm/kvm_book3s_asm.h>
22 #include <asm/cpuidle.h>
23 #include <asm/exception-64s.h>
24 #include <asm/book3s/64/mmu-hash.h>
26 #include <asm/asm-compat.h>
27 #include <asm/feature-fixups.h>
32 * Use unused space in the interrupt stack to save and restore
33 * registers for winkle support.
48 #define PSSCR_EC_ESL_MASK_SHIFTED (PSSCR_EC | PSSCR_ESL) >> 16
53 * Used by threads before entering deep idle states. Saves SPRs
54 * in interrupt stack frame
58 * Note all register i.e per-core, per-subcore or per-thread is saved
59 * here since any thread in the core might wake up first
63 * Note - SDR1 is dropped in Power ISA v3. Hence not restoring
73 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
91 * On POWER9, there are idle states such as stop4, invoked via cpuidle,
92 * that lose hypervisor resources. In such cases, we need to save
93 * additional SPRs before entering those idle states so that they can
94 * be restored to their older values on wakeup from the idle state.
96 * On POWER8, the only such deep idle state is winkle which is used
97 * only in the context of CPU-Hotplug, where these additional SPRs are
98 * reinitiazed to a sane value. Hence there is no need to save/restore
103 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
105 power9_save_additional_sprs:
108 std r3, STOP_PID(r13)
109 std r4, STOP_LDBAR(r13)
113 std r3, STOP_FSCR(r13)
114 std r4, STOP_HFSCR(r13)
118 std r3, STOP_MMCRA(r13)
123 std r3, STOP_MMCR1(r13)
124 std r4, STOP_MMCR2(r13)
127 power9_restore_additional_sprs:
133 ld r3, STOP_LDBAR(r13)
134 ld r4, STOP_FSCR(r13)
138 ld r3, STOP_HFSCR(r13)
139 ld r4, STOP_MMCRA(r13)
144 ld r4, STOP_MMCR1(r13)
148 ld r3, STOP_MMCR2(r13)
149 ld r4, PACA_SPRG_VDSO(r13)
155 * Used by threads when the lock bit of core_idle_state is set.
156 * Threads will spin in HMT_LOW until the lock bit is cleared.
157 * r14 - pointer to core_idle_state
158 * r15 - used to load contents of core_idle_state
159 * r9 - used as a temporary variable
165 andis. r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
169 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
170 bne- core_idle_lock_held
173 /* Reuse some unused pt_regs slots for AMR/IAMR/UAMOR/UAMOR */
174 #define PNV_POWERSAVE_AMR _TRAP
175 #define PNV_POWERSAVE_IAMR _DAR
176 #define PNV_POWERSAVE_UAMOR _DSISR
177 #define PNV_POWERSAVE_AMOR RESULT
180 * Pass requested state in r3:
181 * r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8
182 * - Requested PSSCR value in POWER9
184 * Address of idle handler to branch to in realmode in r4
186 pnv_powersave_common:
187 /* Use r3 to pass state nap/sleep/winkle */
188 /* NAP is a state loss, we create a regs frame on the
189 * stack, fill it up with the state we care about and
190 * stick a pointer to it in PACAR1. We really only
191 * need to save PC, some CR bits and the NV GPRs,
192 * but for now an interrupt frame will do.
198 stdu r1,-INT_FRAME_SIZE(r1)
202 /* We haven't lost state ... yet */
204 stb r0,PACA_NAPSTATELOST(r13)
206 /* Continue saving state */
214 std r4, PNV_POWERSAVE_AMR(r1)
215 std r5, PNV_POWERSAVE_IAMR(r1)
216 std r6, PNV_POWERSAVE_UAMOR(r1)
217 BEGIN_FTR_SECTION_NESTED(42)
219 std r7, PNV_POWERSAVE_AMOR(r1)
220 END_FTR_SECTION_NESTED_IFSET(CPU_FTR_HVMODE, 42)
221 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
229 * POWER9 does not require real mode to stop, and presently does not
230 * set hwthread_state for KVM (threads don't share MMU context), so
231 * we can remain in virtual mode for this.
234 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
237 * Go to real mode to do the nap, as required by the architecture.
238 * Also, we need to be in real mode before setting hwthread_state,
239 * because as soon as we do that, another thread can switch
240 * the MMU context to the guest.
242 LOAD_REG_IMMEDIATE(r7, MSR_IDLE)
247 * This is the sequence required to execute idle instructions, as
248 * specified in ISA v2.07 (and earlier). MSR[IR] and MSR[DR] must be 0.
250 #define IDLE_STATE_ENTER_SEQ_NORET(IDLE_INST) \
251 /* Magic NAP/SLEEP/WINKLE mode enter sequence */ \
255 236: cmpd cr0,r0,r0; \
260 .globl pnv_enter_arch207_idle_mode
261 pnv_enter_arch207_idle_mode:
262 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
263 /* Tell KVM we're entering idle */
264 li r4,KVM_HWTHREAD_IN_IDLE
265 /******************************************************/
266 /* N O T E W E L L ! ! ! N O T E W E L L */
267 /* The following store to HSTATE_HWTHREAD_STATE(r13) */
268 /* MUST occur in real mode, i.e. with the MMU off, */
269 /* and the MMU must stay off until we clear this flag */
270 /* and test HSTATE_HWTHREAD_REQ(r13) in */
271 /* pnv_powersave_wakeup in this file. */
272 /* The reason is that another thread can switch the */
273 /* MMU to a guest context whenever this flag is set */
274 /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */
275 /* that would potentially cause this thread to start */
276 /* executing instructions from guest memory in */
277 /* hypervisor mode, leading to a host crash or data */
278 /* corruption, or worse. */
279 /******************************************************/
280 stb r4,HSTATE_HWTHREAD_STATE(r13)
282 stb r3,PACA_THREAD_IDLE_STATE(r13)
283 cmpwi cr3,r3,PNV_THREAD_SLEEP
285 IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP)
288 /* Sleep or winkle */
289 lbz r7,PACA_THREAD_MASK(r13)
290 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
293 lis r5,PNV_CORE_IDLE_WINKLE_COUNT@h
298 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
299 bnel- core_idle_lock_held
301 add r15,r15,r5 /* Add if winkle */
302 andc r15,r15,r7 /* Clear thread bit */
304 andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS
307 * If cr0 = 0, then current thread is the last thread of the core entering
308 * sleep. Last thread needs to execute the hardware bug workaround code if
309 * required by the platform.
310 * Make the workaround call unconditionally here. The below branch call is
311 * patched out when the idle states are discovered if the platform does not
314 .global pnv_fastsleep_workaround_at_entry
315 pnv_fastsleep_workaround_at_entry:
316 beq fastsleep_workaround_at_entry
322 common_enter: /* common code for all the threads entering sleep or winkle */
324 IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP)
326 fastsleep_workaround_at_entry:
327 oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
332 /* Fast sleep workaround */
335 bl opal_config_cpu_idle_state
338 xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
344 bl save_sprs_to_stack
346 IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE)
349 * r3 - PSSCR value corresponding to the requested stop state.
353 * Check if we are executing the lite variant with ESL=EC=0
355 andis. r4,r3,PSSCR_EC_ESL_MASK_SHIFTED
356 clrldi r3,r3,60 /* r3 = Bits[60:63] = Requested Level (RL) */
357 bne .Lhandle_esl_ec_set
359 li r3,0 /* Since we didn't lose state, return 0 */
360 std r3, PACA_REQ_PSSCR(r13)
363 * pnv_wakeup_noloss() expects r12 to contain the SRR1 value so
364 * it can determine if the wakeup reason is an HMI in
365 * CHECK_HMI_INTERRUPT.
367 * However, when we wakeup with ESL=0, SRR1 will not contain the wakeup
368 * reason, so there is no point setting r12 to SRR1.
370 * Further, we clear r12 here, so that we don't accidentally enter the
371 * HMI in pnv_wakeup_noloss() if the value of r12[42:45] == WAKE_HMI.
379 * POWER9 DD2.0 or earlier can incorrectly set PMAO when waking up after
380 * a state-loss idle. Saving and restoring MMCR0 over idle is a
385 END_FTR_SECTION_IFCLR(CPU_FTR_POWER9_DD2_1)
388 * Check if the requested state is a deep idle state.
390 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
391 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
393 bge .Lhandle_deep_stop
394 PPC_STOP /* Does not return (system reset interrupt) */
398 * Entering deep idle state.
399 * Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to
400 * stack and enter stop
402 lbz r7,PACA_THREAD_MASK(r13)
403 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
407 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
408 bnel- core_idle_lock_held
409 andc r15,r15,r7 /* Clear thread bit */
415 bl save_sprs_to_stack
417 PPC_STOP /* Does not return (system reset interrupt) */
420 * Entered with MSR[EE]=0 and no soft-masked interrupts pending.
421 * r3 contains desired idle state (PNV_THREAD_NAP/SLEEP/WINKLE).
423 _GLOBAL(power7_idle_insn)
424 /* Now check if user or arch enabled NAP mode */
425 LOAD_REG_ADDR(r4, pnv_enter_arch207_idle_mode)
426 b pnv_powersave_common
428 #define CHECK_HMI_INTERRUPT \
429 BEGIN_FTR_SECTION_NESTED(66); \
430 rlwinm r0,r12,45-31,0xf; /* extract wake reason field (P8) */ \
431 FTR_SECTION_ELSE_NESTED(66); \
432 rlwinm r0,r12,45-31,0xe; /* P7 wake reason field is 3 bits */ \
433 ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
434 cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
436 /* Invoke opal call to handle hmi */ \
437 ld r2,PACATOC(r13); \
439 std r3,ORIG_GPR3(r1); /* Save original r3 */ \
440 li r3,0; /* NULL argument */ \
441 bl hmi_exception_realmode; \
443 ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
447 * Entered with MSR[EE]=0 and no soft-masked interrupts pending.
448 * r3 contains desired PSSCR register value.
450 * Offline (CPU unplug) case also must notify KVM that the CPU is
453 _GLOBAL(power9_offline_stop)
454 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
456 * Tell KVM we're entering idle.
457 * This does not have to be done in real mode because the P9 MMU
458 * is independent per-thread. Some steppings share radix/hash mode
459 * between threads, but in that case KVM has a barrier sync in real
460 * mode before and after switching between radix and hash.
462 li r4,KVM_HWTHREAD_IN_IDLE
463 stb r4,HSTATE_HWTHREAD_STATE(r13)
467 _GLOBAL(power9_idle_stop)
468 std r3, PACA_REQ_PSSCR(r13)
469 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
472 lwz r5, PACA_DONT_STOP(r13)
475 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
478 LOAD_REG_ADDR(r4,power_enter_stop)
479 b pnv_powersave_common
481 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
484 * We get here when TM / thread reconfiguration bug workaround
485 * code wants to get the CPU into SMT4 mode, and therefore
486 * we are being asked not to stop.
489 std r3, PACA_REQ_PSSCR(r13)
490 blr /* return 0 for wakeup cause / SRR1 value */
494 * Called from machine check handler for powersave wakeups.
495 * Low level machine check processing has already been done. Now just
496 * go through the wake up path to get everything in order.
498 * r3 - The original SRR1 value.
499 * Original SRR[01] have been clobbered.
502 .global pnv_powersave_wakeup_mce
503 pnv_powersave_wakeup_mce:
504 /* Set cr3 for pnv_powersave_wakeup */
505 rlwinm r11,r3,47-31,30,31
509 * Now put the original SRR1 with SRR1_WAKEMCE_RESVD as the wake
510 * reason into r12, which allows reuse of the system reset wakeup
511 * code without being mistaken for another type of wakeup.
513 oris r12,r3,SRR1_WAKEMCE_RESVD@h
515 b pnv_powersave_wakeup
518 * Called from reset vector for powersave wakeups.
519 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
522 .global pnv_powersave_wakeup
523 pnv_powersave_wakeup:
527 bl pnv_restore_hyp_resource_arch300
529 bl pnv_restore_hyp_resource_arch207
530 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
532 li r0,PNV_THREAD_RUNNING
533 stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */
537 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
538 lbz r0,HSTATE_HWTHREAD_STATE(r13)
539 cmpwi r0,KVM_HWTHREAD_IN_KERNEL
541 li r0,KVM_HWTHREAD_IN_KERNEL
542 stb r0,HSTATE_HWTHREAD_STATE(r13)
543 /* Order setting hwthread_state vs. testing hwthread_req */
545 0: lbz r0,HSTATE_HWTHREAD_REQ(r13)
552 /* Return SRR1 from power7_nap() */
553 blt cr3,pnv_wakeup_noloss
557 * Check whether we have woken up with hypervisor state loss.
558 * If yes, restore hypervisor state and return back to link.
560 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
562 pnv_restore_hyp_resource_arch300:
564 * Workaround for POWER9, if we lost resources, the ERAT
565 * might have been mixed up and needs flushing. We also need
566 * to reload MMCR0 (see comment above). We also need to set
567 * then clear bit 60 in MMCRA to ensure the PMU starts running.
575 END_FTR_SECTION_IFCLR(CPU_FTR_POWER9_DD2_1)
577 ori r4,r4,(1 << (63-60))
579 xori r4,r4,(1 << (63-60))
583 * POWER ISA 3. Use PSSCR to determine if we
584 * are waking up from deep idle state
586 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
587 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
590 * 0-3 bits correspond to Power-Saving Level Status
591 * which indicates the idle state we are waking up from
595 li r0, 0 /* clear requested_psscr to say we're awake */
596 std r0, PACA_REQ_PSSCR(r13)
598 bge cr4,pnv_wakeup_tb_loss /* returns to caller */
600 blr /* Waking up without hypervisor state loss. */
602 /* Same calling convention as arch300 */
603 pnv_restore_hyp_resource_arch207:
605 * POWER ISA 2.07 or less.
606 * Check if we slept with sleep or winkle.
608 lbz r4,PACA_THREAD_IDLE_STATE(r13)
609 cmpwi cr2,r4,PNV_THREAD_NAP
610 bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */
613 * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
614 * up from nap. At this stage CR3 shouldn't contains 'gt' since that
615 * indicates we are waking with hypervisor state loss from nap.
619 blr /* Waking up without hypervisor state loss */
622 * Called if waking up from idle state which can cause either partial or
623 * complete hyp state loss.
624 * In POWER8, called if waking up from fastsleep or winkle
625 * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state
628 * cr3 - gt if waking up with partial/complete hypervisor state loss
631 * cr4 - gt or eq if waking up from complete hypervisor state loss.
634 * r4 - PACA_THREAD_IDLE_STATE
639 * Before entering any idle state, the NVGPRs are saved in the stack.
640 * If there was a state loss, or PACA_NAPSTATELOST was set, then the
641 * NVGPRs are restored. If we are here, it is likely that state is lost,
642 * but not guaranteed -- neither ISA207 nor ISA300 tests to reach
643 * here are the same as the test to restore NVGPRS:
644 * PACA_THREAD_IDLE_STATE test for ISA207, PSSCR test for ISA300,
645 * and SRR1 test for restoring NVGPRs.
647 * We are about to clobber NVGPRs now, so set NAPSTATELOST to
648 * guarantee they will always be restored. This might be tightened
649 * with careful reading of specs (particularly for ISA300) but this
650 * is already a slow wakeup path and it's simpler to be safe.
653 stb r0,PACA_NAPSTATELOST(r13)
657 * Save SRR1 and LR in NVGPRs as they might be clobbered in
658 * opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required
659 * to determine the wakeup reason if we branch to kvm_start_guest. LR
660 * is required to return back to reset vector after hypervisor state
661 * restore is complete.
668 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
670 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
671 lbz r7,PACA_THREAD_MASK(r13)
674 * Take the core lock to synchronize against other threads.
676 * Lock bit is set in one of the 2 cases-
677 * a. In the sleep/winkle enter path, the last thread is executing
678 * fastsleep workaround code.
679 * b. In the wake up path, another thread is executing fastsleep
680 * workaround undo code or resyncing timebase or restoring context
681 * In either case loop until the lock bit is cleared.
685 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
686 bnel- core_idle_lock_held
687 oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
692 andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS
697 * cr2 - eq if first thread to wakeup in core
698 * cr3- gt if waking up with partial/complete hypervisor state loss
700 * cr4 - gt or eq if waking up from complete hypervisor state loss.
706 * If yes, check if all threads were in winkle, decrement our
707 * winkle count, set all thread winkle bits if all were in winkle.
708 * Check if our thread has a winkle bit set, and set cr4 accordingly
709 * (to match ISA300, above). Pseudo-code for core idle state
710 * transitions for ISA207 is as follows (everything happens atomically
711 * due to store conditional and/or lock bit):
718 * core_idle_state &= ~thread_in_core
723 * bool first_in_core, first_in_subcore;
725 * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;
726 * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;
728 * core_idle_state |= thread_in_core;
733 * core_idle_state &= ~thread_in_core;
734 * core_idle_state += 1 << WINKLE_COUNT_SHIFT;
739 * bool first_in_core, first_in_subcore, winkle_state_lost;
741 * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;
742 * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;
744 * core_idle_state |= thread_in_core;
746 * if ((core_idle_state & WINKLE_MASK) == (8 << WINKLE_COUNT_SIHFT))
747 * core_idle_state |= THREAD_WINKLE_BITS;
748 * core_idle_state -= 1 << WINKLE_COUNT_SHIFT;
750 * winkle_state_lost = core_idle_state &
751 * (thread_in_core << WINKLE_THREAD_SHIFT);
752 * core_idle_state &= ~(thread_in_core << WINKLE_THREAD_SHIFT);
756 cmpwi r18,PNV_THREAD_WINKLE
758 andis. r9,r15,PNV_CORE_IDLE_WINKLE_COUNT_ALL_BIT@h
759 subis r15,r15,PNV_CORE_IDLE_WINKLE_COUNT@h
761 ori r15,r15,PNV_CORE_IDLE_THREAD_WINKLE_BITS /* all were winkle */
763 /* Shift thread bit to winkle mask, then test if this thread is set,
764 * and remove it from the winkle bits */
768 cmpwi cr4,r8,1 /* cr4 will be gt if our bit is set, lt if not */
770 lbz r4,PACA_SUBCORE_SIBLING_MASK(r13)
772 cmpwi r4,0 /* Check if first in subcore */
774 or r15,r15,r7 /* Set thread bit */
775 beq first_thread_in_subcore
776 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
778 or r15,r15,r7 /* Set thread bit */
779 beq cr2,first_thread_in_core
781 /* Not first thread in core or subcore to wake up */
784 first_thread_in_subcore:
786 * If waking up from sleep, subcore state is not lost. Hence
787 * skip subcore state restore
789 blt cr4,subcore_state_restored
791 /* Restore per-subcore state */
800 subcore_state_restored:
802 * Check if the thread is also the first thread in the core. If not,
803 * skip to clear_lock.
807 first_thread_in_core:
810 * First thread in the core waking up from any state which can cause
811 * partial or complete hypervisor state loss. It needs to
812 * call the fastsleep workaround code if the platform requires it.
813 * Call it unconditionally here. The below branch instruction will
814 * be patched out if the platform does not have fastsleep or does not
815 * require the workaround. Patching will be performed during the
816 * discovery of idle-states.
818 .global pnv_fastsleep_workaround_at_exit
819 pnv_fastsleep_workaround_at_exit:
820 b fastsleep_workaround_at_exit
824 * Use cr3 which indicates that we are waking up with atleast partial
825 * hypervisor state loss to determine if TIMEBASE RESYNC is needed.
827 ble cr3,.Ltb_resynced
828 /* Time base re-sync */
829 bl opal_resync_timebase;
831 * If waking up from sleep (POWER8), per core state
832 * is not lost, skip to clear_lock.
838 * First thread in the core to wake up and its waking up with
839 * complete hypervisor state loss. Restore per core hypervisor
849 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
857 xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
863 * Common to all threads.
865 * If waking up from sleep, hypervisor state is not lost. Hence
866 * skip hypervisor state restore.
868 blt cr4,hypervisor_state_restored
870 /* Waking up from winkle */
872 BEGIN_MMU_FTR_SECTION
874 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
875 /* Restore SLB from PACA */
876 ld r8,PACA_SLBSHADOWPTR(r13)
879 li r3, SLBSHADOW_SAVEAREA
883 andis. r7,r5,SLB_ESID_V@h
890 /* Restore per thread state */
901 /* Call cur_cpu_spec->cpu_restore() */
902 LOAD_REG_ADDR(r4, cur_cpu_spec)
904 ld r12,CPU_SPEC_RESTORE(r4)
905 #ifdef PPC64_ELF_ABI_v1
912 * On POWER9, we can come here on wakeup from a cpuidle stop state.
913 * Hence restore the additional SPRs to the saved value.
915 * On POWER8, we come here only on winkle. Since winkle is used
916 * only in the case of CPU-Hotplug, we don't need to restore
917 * the additional SPRs.
920 bl power9_restore_additional_sprs
921 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
922 hypervisor_state_restored:
926 blr /* return to pnv_powersave_wakeup */
928 fastsleep_workaround_at_exit:
931 bl opal_config_cpu_idle_state
935 * R3 here contains the value that will be returned to the caller
937 * R12 contains SRR1 for CHECK_HMI_INTERRUPT.
939 .global pnv_wakeup_loss
944 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
949 /* These regs were saved in pnv_powersave_common() */
950 ld r4, PNV_POWERSAVE_AMR(r1)
951 ld r5, PNV_POWERSAVE_IAMR(r1)
952 ld r6, PNV_POWERSAVE_UAMOR(r1)
956 BEGIN_FTR_SECTION_NESTED(42)
957 ld r7, PNV_POWERSAVE_AMOR(r1)
959 END_FTR_SECTION_NESTED_IFSET(CPU_FTR_HVMODE, 42)
961 * We don't need an isync here after restoring IAMR because the upcoming
962 * mtmsrd is execution synchronizing.
964 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
969 addi r1,r1,INT_FRAME_SIZE
976 * R3 here contains the value that will be returned to the caller
978 * R12 contains SRR1 for CHECK_HMI_INTERRUPT.
981 lbz r0,PACA_NAPSTATELOST(r13)
987 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
991 addi r1,r1,INT_FRAME_SIZE