i915_gpu_error.c

   1 /*
   2  * Copyright (c) 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *    Mika Kuoppala <mika.kuoppala@intel.com>
  27  *
  28  */
  29
  30 #include <linux/ascii85.h>
  31 #include <linux/nmi.h>
  32 #include <linux/pagevec.h>
  33 #include <linux/scatterlist.h>
  34 #include <linux/utsname.h>
  35 #include <linux/zlib.h>
  36
  37 #include <drm/drm_print.h>
  38
  39 #include "display/intel_atomic.h"
  40 #include "display/intel_csr.h"
  41 #include "display/intel_overlay.h"
  42
  43 #include "gem/i915_gem_context.h"
  44 #include "gem/i915_gem_lmem.h"
  45 #include "gt/intel_gt.h"
  46 #include "gt/intel_gt_pm.h"
  47
  48 #include "i915_drv.h"
  49 #include "i915_gpu_error.h"
  50 #include "i915_memcpy.h"
  51 #include "i915_scatterlist.h"
  52
  53 #define ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
  54 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN)
  55
  56 static void __sg_set_buf(struct scatterlist *sg,
  57                          void *addr, unsigned int len, loff_t it)
  58 {
  59         sg->page_link = (unsigned long)virt_to_page(addr);
  60         sg->offset = offset_in_page(addr);
  61         sg->length = len;
  62         sg->dma_address = it;
  63 }
  64
  65 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len)
  66 {
  67         if (!len)
  68                 return false;
  69
  70         if (e->bytes + len + 1 <= e->size)
  71                 return true;
  72
  73         if (e->bytes) {
  74                 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter);
  75                 e->iter += e->bytes;
  76                 e->buf = NULL;
  77                 e->bytes = 0;
  78         }
  79
  80         if (e->cur == e->end) {
  81                 struct scatterlist *sgl;
  82
  83                 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL);
  84                 if (!sgl) {
  85                         e->err = -ENOMEM;
  86                         return false;
  87                 }
  88
  89                 if (e->cur) {
  90                         e->cur->offset = 0;
  91                         e->cur->length = 0;
  92                         e->cur->page_link =
  93                                 (unsigned long)sgl | SG_CHAIN;
  94                 } else {
  95                         e->sgl = sgl;
  96                 }
  97
  98                 e->cur = sgl;
  99                 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1;
 100         }
 101
 102         e->size = ALIGN(len + 1, SZ_64K);
 103         e->buf = kmalloc(e->size, ALLOW_FAIL);
 104         if (!e->buf) {
 105                 e->size = PAGE_ALIGN(len + 1);
 106                 e->buf = kmalloc(e->size, GFP_KERNEL);
 107         }
 108         if (!e->buf) {
 109                 e->err = -ENOMEM;
 110                 return false;
 111         }
 112
 113         return true;
 114 }
 115
 116 __printf(2, 0)
 117 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
 118                                const char *fmt, va_list args)
 119 {
 120         va_list ap;
 121         int len;
 122
 123         if (e->err)
 124                 return;
 125
 126         va_copy(ap, args);
 127         len = vsnprintf(NULL, 0, fmt, ap);
 128         va_end(ap);
 129         if (len <= 0) {
 130                 e->err = len;
 131                 return;
 132         }
 133
 134         if (!__i915_error_grow(e, len))
 135                 return;
 136
 137         GEM_BUG_ON(e->bytes >= e->size);
 138         len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args);
 139         if (len < 0) {
 140                 e->err = len;
 141                 return;
 142         }
 143         e->bytes += len;
 144 }
 145
 146 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str)
 147 {
 148         unsigned len;
 149
 150         if (e->err || !str)
 151                 return;
 152
 153         len = strlen(str);
 154         if (!__i915_error_grow(e, len))
 155                 return;
 156
 157         GEM_BUG_ON(e->bytes + len > e->size);
 158         memcpy(e->buf + e->bytes, str, len);
 159         e->bytes += len;
 160 }
 161
 162 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
 163 #define err_puts(e, s) i915_error_puts(e, s)
 164
 165 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf)
 166 {
 167         i915_error_vprintf(p->arg, vaf->fmt, *vaf->va);
 168 }
 169
 170 static inline struct drm_printer
 171 i915_error_printer(struct drm_i915_error_state_buf *e)
 172 {
 173         struct drm_printer p = {
 174                 .printfn = __i915_printfn_error,
 175                 .arg = e,
 176         };
 177         return p;
 178 }
 179
 180 /* single threaded page allocator with a reserved stash for emergencies */
 181 static void pool_fini(struct pagevec *pv)
 182 {
 183         pagevec_release(pv);
 184 }
 185
 186 static int pool_refill(struct pagevec *pv, gfp_t gfp)
 187 {
 188         while (pagevec_space(pv)) {
 189                 struct page *p;
 190
 191                 p = alloc_page(gfp);
 192                 if (!p)
 193                         return -ENOMEM;
 194
 195                 pagevec_add(pv, p);
 196         }
 197
 198         return 0;
 199 }
 200
 201 static int pool_init(struct pagevec *pv, gfp_t gfp)
 202 {
 203         int err;
 204
 205         pagevec_init(pv);
 206
 207         err = pool_refill(pv, gfp);
 208         if (err)
 209                 pool_fini(pv);
 210
 211         return err;
 212 }
 213
 214 static void *pool_alloc(struct pagevec *pv, gfp_t gfp)
 215 {
 216         struct page *p;
 217
 218         p = alloc_page(gfp);
 219         if (!p && pagevec_count(pv))
 220                 p = pv->pages[--pv->nr];
 221
 222         return p ? page_address(p) : NULL;
 223 }
 224
 225 static void pool_free(struct pagevec *pv, void *addr)
 226 {
 227         struct page *p = virt_to_page(addr);
 228
 229         if (pagevec_space(pv))
 230                 pagevec_add(pv, p);
 231         else
 232                 __free_page(p);
 233 }
 234
 235 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
 236
 237 struct i915_vma_compress {
 238         struct pagevec pool;
 239         struct z_stream_s zstream;
 240         void *tmp;
 241 };
 242
 243 static bool compress_init(struct i915_vma_compress *c)
 244 {
 245         struct z_stream_s *zstream = &c->zstream;
 246
 247         if (pool_init(&c->pool, ALLOW_FAIL))
 248                 return false;
 249
 250         zstream->workspace =
 251                 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
 252                         ALLOW_FAIL);
 253         if (!zstream->workspace) {
 254                 pool_fini(&c->pool);
 255                 return false;
 256         }
 257
 258         c->tmp = NULL;
 259         if (i915_has_memcpy_from_wc())
 260                 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL);
 261
 262         return true;
 263 }
 264
 265 static bool compress_start(struct i915_vma_compress *c)
 266 {
 267         struct z_stream_s *zstream = &c->zstream;
 268         void *workspace = zstream->workspace;
 269
 270         memset(zstream, 0, sizeof(*zstream));
 271         zstream->workspace = workspace;
 272
 273         return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK;
 274 }
 275
 276 static void *compress_next_page(struct i915_vma_compress *c,
 277                                 struct i915_vma_coredump *dst)
 278 {
 279         void *page;
 280
 281         if (dst->page_count >= dst->num_pages)
 282                 return ERR_PTR(-ENOSPC);
 283
 284         page = pool_alloc(&c->pool, ALLOW_FAIL);
 285         if (!page)
 286                 return ERR_PTR(-ENOMEM);
 287
 288         return dst->pages[dst->page_count++] = page;
 289 }
 290
 291 static int compress_page(struct i915_vma_compress *c,
 292                          void *src,
 293                          struct i915_vma_coredump *dst,
 294                          bool wc)
 295 {
 296         struct z_stream_s *zstream = &c->zstream;
 297
 298         zstream->next_in = src;
 299         if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
 300                 zstream->next_in = c->tmp;
 301         zstream->avail_in = PAGE_SIZE;
 302
 303         do {
 304                 if (zstream->avail_out == 0) {
 305                         zstream->next_out = compress_next_page(c, dst);
 306                         if (IS_ERR(zstream->next_out))
 307                                 return PTR_ERR(zstream->next_out);
 308
 309                         zstream->avail_out = PAGE_SIZE;
 310                 }
 311
 312                 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK)
 313                         return -EIO;
 314
 315                 cond_resched();
 316         } while (zstream->avail_in);
 317
 318         /* Fallback to uncompressed if we increase size? */
 319         if (0 && zstream->total_out > zstream->total_in)
 320                 return -E2BIG;
 321
 322         return 0;
 323 }
 324
 325 static int compress_flush(struct i915_vma_compress *c,
 326                           struct i915_vma_coredump *dst)
 327 {
 328         struct z_stream_s *zstream = &c->zstream;
 329
 330         do {
 331                 switch (zlib_deflate(zstream, Z_FINISH)) {
 332                 case Z_OK: /* more space requested */
 333                         zstream->next_out = compress_next_page(c, dst);
 334                         if (IS_ERR(zstream->next_out))
 335                                 return PTR_ERR(zstream->next_out);
 336
 337                         zstream->avail_out = PAGE_SIZE;
 338                         break;
 339
 340                 case Z_STREAM_END:
 341                         goto end;
 342
 343                 default: /* any error */
 344                         return -EIO;
 345                 }
 346         } while (1);
 347
 348 end:
 349         memset(zstream->next_out, 0, zstream->avail_out);
 350         dst->unused = zstream->avail_out;
 351         return 0;
 352 }
 353
 354 static void compress_finish(struct i915_vma_compress *c)
 355 {
 356         zlib_deflateEnd(&c->zstream);
 357 }
 358
 359 static void compress_fini(struct i915_vma_compress *c)
 360 {
 361         kfree(c->zstream.workspace);
 362         if (c->tmp)
 363                 pool_free(&c->pool, c->tmp);
 364         pool_fini(&c->pool);
 365 }
 366
 367 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 368 {
 369         err_puts(m, ":");
 370 }
 371
 372 #else
 373
 374 struct i915_vma_compress {
 375         struct pagevec pool;
 376 };
 377
 378 static bool compress_init(struct i915_vma_compress *c)
 379 {
 380         return pool_init(&c->pool, ALLOW_FAIL) == 0;
 381 }
 382
 383 static bool compress_start(struct i915_vma_compress *c)
 384 {
 385         return true;
 386 }
 387
 388 static int compress_page(struct i915_vma_compress *c,
 389                          void *src,
 390                          struct i915_vma_coredump *dst,
 391                          bool wc)
 392 {
 393         void *ptr;
 394
 395         ptr = pool_alloc(&c->pool, ALLOW_FAIL);
 396         if (!ptr)
 397                 return -ENOMEM;
 398
 399         if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE)))
 400                 memcpy(ptr, src, PAGE_SIZE);
 401         dst->pages[dst->page_count++] = ptr;
 402         cond_resched();
 403
 404         return 0;
 405 }
 406
 407 static int compress_flush(struct i915_vma_compress *c,
 408                           struct i915_vma_coredump *dst)
 409 {
 410         return 0;
 411 }
 412
 413 static void compress_finish(struct i915_vma_compress *c)
 414 {
 415 }
 416
 417 static void compress_fini(struct i915_vma_compress *c)
 418 {
 419         pool_fini(&c->pool);
 420 }
 421
 422 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 423 {
 424         err_puts(m, "~");
 425 }
 426
 427 #endif
 428
 429 static void error_print_instdone(struct drm_i915_error_state_buf *m,
 430                                  const struct intel_engine_coredump *ee)
 431 {
 432         const struct sseu_dev_info *sseu = &ee->engine->gt->info.sseu;
 433         int slice;
 434         int subslice;
 435
 436         err_printf(m, "  INSTDONE: 0x%08x\n",
 437                    ee->instdone.instdone);
 438
 439         if (ee->engine->class != RENDER_CLASS || INTEL_GEN(m->i915) <= 3)
 440                 return;
 441
 442         err_printf(m, "  SC_INSTDONE: 0x%08x\n",
 443                    ee->instdone.slice_common);
 444
 445         if (INTEL_GEN(m->i915) <= 6)
 446                 return;
 447
 448         for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
 449                 err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
 450                            slice, subslice,
 451                            ee->instdone.sampler[slice][subslice]);
 452
 453         for_each_instdone_slice_subslice(m->i915, sseu, slice, subslice)
 454                 err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
 455                            slice, subslice,
 456                            ee->instdone.row[slice][subslice]);
 457
 458         if (INTEL_GEN(m->i915) < 12)
 459                 return;
 460
 461         err_printf(m, "  SC_INSTDONE_EXTRA: 0x%08x\n",
 462                    ee->instdone.slice_common_extra[0]);
 463         err_printf(m, "  SC_INSTDONE_EXTRA2: 0x%08x\n",
 464                    ee->instdone.slice_common_extra[1]);
 465 }
 466
 467 static void error_print_request(struct drm_i915_error_state_buf *m,
 468                                 const char *prefix,
 469                                 const struct i915_request_coredump *erq)
 470 {
 471         if (!erq->seqno)
 472                 return;
 473
 474         err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, head %08x, tail %08x\n",
 475                    prefix, erq->pid, erq->context, erq->seqno,
 476                    test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
 477                             &erq->flags) ? "!" : "",
 478                    test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
 479                             &erq->flags) ? "+" : "",
 480                    erq->sched_attr.priority,
 481                    erq->head, erq->tail);
 482 }
 483
 484 static void error_print_context(struct drm_i915_error_state_buf *m,
 485                                 const char *header,
 486                                 const struct i915_gem_context_coredump *ctx)
 487 {
 488         const u32 period = RUNTIME_INFO(m->i915)->cs_timestamp_period_ns;
 489
 490         err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n",
 491                    header, ctx->comm, ctx->pid, ctx->sched_attr.priority,
 492                    ctx->guilty, ctx->active,
 493                    ctx->total_runtime * period,
 494                    mul_u32_u32(ctx->avg_runtime, period));
 495 }
 496
 497 static struct i915_vma_coredump *
 498 __find_vma(struct i915_vma_coredump *vma, const char *name)
 499 {
 500         while (vma) {
 501                 if (strcmp(vma->name, name) == 0)
 502                         return vma;
 503                 vma = vma->next;
 504         }
 505
 506         return NULL;
 507 }
 508
 509 static struct i915_vma_coredump *
 510 find_batch(const struct intel_engine_coredump *ee)
 511 {
 512         return __find_vma(ee->vma, "batch");
 513 }
 514
 515 static void error_print_engine(struct drm_i915_error_state_buf *m,
 516                                const struct intel_engine_coredump *ee)
 517 {
 518         struct i915_vma_coredump *batch;
 519         int n;
 520
 521         err_printf(m, "%s command stream:\n", ee->engine->name);
 522         err_printf(m, "  CCID:  0x%08x\n", ee->ccid);
 523         err_printf(m, "  START: 0x%08x\n", ee->start);
 524         err_printf(m, "  HEAD:  0x%08x [0x%08x]\n", ee->head, ee->rq_head);
 525         err_printf(m, "  TAIL:  0x%08x [0x%08x, 0x%08x]\n",
 526                    ee->tail, ee->rq_post, ee->rq_tail);
 527         err_printf(m, "  CTL:   0x%08x\n", ee->ctl);
 528         err_printf(m, "  MODE:  0x%08x\n", ee->mode);
 529         err_printf(m, "  HWS:   0x%08x\n", ee->hws);
 530         err_printf(m, "  ACTHD: 0x%08x %08x\n",
 531                    (u32)(ee->acthd>>32), (u32)ee->acthd);
 532         err_printf(m, "  IPEIR: 0x%08x\n", ee->ipeir);
 533         err_printf(m, "  IPEHR: 0x%08x\n", ee->ipehr);
 534         err_printf(m, "  ESR:   0x%08x\n", ee->esr);
 535
 536         error_print_instdone(m, ee);
 537
 538         batch = find_batch(ee);
 539         if (batch) {
 540                 u64 start = batch->gtt_offset;
 541                 u64 end = start + batch->gtt_size;
 542
 543                 err_printf(m, "  batch: [0x%08x_%08x, 0x%08x_%08x]\n",
 544                            upper_32_bits(start), lower_32_bits(start),
 545                            upper_32_bits(end), lower_32_bits(end));
 546         }
 547         if (INTEL_GEN(m->i915) >= 4) {
 548                 err_printf(m, "  BBADDR: 0x%08x_%08x\n",
 549                            (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
 550                 err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
 551                 err_printf(m, "  INSTPS: 0x%08x\n", ee->instps);
 552         }
 553         err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
 554         err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
 555                    lower_32_bits(ee->faddr));
 556         if (INTEL_GEN(m->i915) >= 6) {
 557                 err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
 558                 err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
 559         }
 560         if (HAS_PPGTT(m->i915)) {
 561                 err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
 562
 563                 if (INTEL_GEN(m->i915) >= 8) {
 564                         int i;
 565                         for (i = 0; i < 4; i++)
 566                                 err_printf(m, "  PDP%d: 0x%016llx\n",
 567                                            i, ee->vm_info.pdp[i]);
 568                 } else {
 569                         err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
 570                                    ee->vm_info.pp_dir_base);
 571                 }
 572         }
 573         err_printf(m, "  engine reset count: %u\n", ee->reset_count);
 574
 575         for (n = 0; n < ee->num_ports; n++) {
 576                 err_printf(m, "  ELSP[%d]:", n);
 577                 error_print_request(m, " ", &ee->execlist[n]);
 578         }
 579
 580         error_print_context(m, "  Active context: ", &ee->context);
 581 }
 582
 583 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
 584 {
 585         va_list args;
 586
 587         va_start(args, f);
 588         i915_error_vprintf(e, f, args);
 589         va_end(args);
 590 }
 591
 592 static void print_error_vma(struct drm_i915_error_state_buf *m,
 593                             const struct intel_engine_cs *engine,
 594                             const struct i915_vma_coredump *vma)
 595 {
 596         char out[ASCII85_BUFSZ];
 597         int page;
 598
 599         if (!vma)
 600                 return;
 601
 602         err_printf(m, "%s --- %s = 0x%08x %08x\n",
 603                    engine ? engine->name : "global", vma->name,
 604                    upper_32_bits(vma->gtt_offset),
 605                    lower_32_bits(vma->gtt_offset));
 606
 607         if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K)
 608                 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes);
 609
 610         err_compression_marker(m);
 611         for (page = 0; page < vma->page_count; page++) {
 612                 int i, len;
 613
 614                 len = PAGE_SIZE;
 615                 if (page == vma->page_count - 1)
 616                         len -= vma->unused;
 617                 len = ascii85_encode_len(len);
 618
 619                 for (i = 0; i < len; i++)
 620                         err_puts(m, ascii85_encode(vma->pages[page][i], out));
 621         }
 622         err_puts(m, "\n");
 623 }
 624
 625 static void err_print_capabilities(struct drm_i915_error_state_buf *m,
 626                                    struct i915_gpu_coredump *error)
 627 {
 628         struct drm_printer p = i915_error_printer(m);
 629
 630         intel_device_info_print_static(&error->device_info, &p);
 631         intel_device_info_print_runtime(&error->runtime_info, &p);
 632         intel_driver_caps_print(&error->driver_caps, &p);
 633 }
 634
 635 static void err_print_params(struct drm_i915_error_state_buf *m,
 636                              const struct i915_params *params)
 637 {
 638         struct drm_printer p = i915_error_printer(m);
 639
 640         i915_params_dump(params, &p);
 641 }
 642
 643 static void err_print_pciid(struct drm_i915_error_state_buf *m,
 644                             struct drm_i915_private *i915)
 645 {
 646         struct pci_dev *pdev = i915->drm.pdev;
 647
 648         err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
 649         err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
 650         err_printf(m, "PCI Subsystem: %04x:%04x\n",
 651                    pdev->subsystem_vendor,
 652                    pdev->subsystem_device);
 653 }
 654
 655 static void err_print_uc(struct drm_i915_error_state_buf *m,
 656                          const struct intel_uc_coredump *error_uc)
 657 {
 658         struct drm_printer p = i915_error_printer(m);
 659
 660         intel_uc_fw_dump(&error_uc->guc_fw, &p);
 661         intel_uc_fw_dump(&error_uc->huc_fw, &p);
 662         print_error_vma(m, NULL, error_uc->guc_log);
 663 }
 664
 665 static void err_free_sgl(struct scatterlist *sgl)
 666 {
 667         while (sgl) {
 668                 struct scatterlist *sg;
 669
 670                 for (sg = sgl; !sg_is_chain(sg); sg++) {
 671                         kfree(sg_virt(sg));
 672                         if (sg_is_last(sg))
 673                                 break;
 674                 }
 675
 676                 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg);
 677                 free_page((unsigned long)sgl);
 678                 sgl = sg;
 679         }
 680 }
 681
 682 static void err_print_gt_info(struct drm_i915_error_state_buf *m,
 683                               struct intel_gt_coredump *gt)
 684 {
 685         struct drm_printer p = i915_error_printer(m);
 686
 687         intel_gt_info_print(&gt->info, &p);
 688         intel_sseu_print_topology(&gt->info.sseu, &p);
 689 }
 690
 691 static void err_print_gt(struct drm_i915_error_state_buf *m,
 692                          struct intel_gt_coredump *gt)
 693 {
 694         const struct intel_engine_coredump *ee;
 695         int i;
 696
 697         err_printf(m, "GT awake: %s\n", yesno(gt->awake));
 698         err_printf(m, "EIR: 0x%08x\n", gt->eir);
 699         err_printf(m, "IER: 0x%08x\n", gt->ier);
 700         for (i = 0; i < gt->ngtier; i++)
 701                 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]);
 702         err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er);
 703         err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake);
 704         err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr);
 705
 706         for (i = 0; i < gt->nfence; i++)
 707                 err_printf(m, "  fence[%d] = %08llx\n", i, gt->fence[i]);
 708
 709         if (IS_GEN_RANGE(m->i915, 6, 11)) {
 710                 err_printf(m, "ERROR: 0x%08x\n", gt->error);
 711                 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg);
 712         }
 713
 714         if (INTEL_GEN(m->i915) >= 8)
 715                 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
 716                            gt->fault_data1, gt->fault_data0);
 717
 718         if (IS_GEN(m->i915, 7))
 719                 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int);
 720
 721         if (IS_GEN_RANGE(m->i915, 8, 11))
 722                 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache);
 723
 724         if (IS_GEN(m->i915, 12))
 725                 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err);
 726
 727         if (INTEL_GEN(m->i915) >= 12) {
 728                 int i;
 729
 730                 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) {
 731                         /*
 732                          * SFC_DONE resides in the VD forcewake domain, so it
 733                          * only exists if the corresponding VCS engine is
 734                          * present.
 735                          */
 736                         if (!HAS_ENGINE(gt->_gt, _VCS(i * 2)))
 737                                 continue;
 738
 739                         err_printf(m, "  SFC_DONE[%d]: 0x%08x\n", i,
 740                                    gt->sfc_done[i]);
 741                 }
 742
 743                 err_printf(m, "  GAM_DONE: 0x%08x\n", gt->gam_done);
 744         }
 745
 746         for (ee = gt->engine; ee; ee = ee->next) {
 747                 const struct i915_vma_coredump *vma;
 748
 749                 error_print_engine(m, ee);
 750                 for (vma = ee->vma; vma; vma = vma->next)
 751                         print_error_vma(m, ee->engine, vma);
 752         }
 753
 754         if (gt->uc)
 755                 err_print_uc(m, gt->uc);
 756
 757         err_print_gt_info(m, gt);
 758 }
 759
 760 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
 761                                struct i915_gpu_coredump *error)
 762 {
 763         const struct intel_engine_coredump *ee;
 764         struct timespec64 ts;
 765
 766         if (*error->error_msg)
 767                 err_printf(m, "%s\n", error->error_msg);
 768         err_printf(m, "Kernel: %s %s\n",
 769                    init_utsname()->release,
 770                    init_utsname()->machine);
 771         err_printf(m, "Driver: %s\n", DRIVER_DATE);
 772         ts = ktime_to_timespec64(error->time);
 773         err_printf(m, "Time: %lld s %ld us\n",
 774                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 775         ts = ktime_to_timespec64(error->boottime);
 776         err_printf(m, "Boottime: %lld s %ld us\n",
 777                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 778         ts = ktime_to_timespec64(error->uptime);
 779         err_printf(m, "Uptime: %lld s %ld us\n",
 780                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 781         err_printf(m, "Capture: %lu jiffies; %d ms ago\n",
 782                    error->capture, jiffies_to_msecs(jiffies - error->capture));
 783
 784         for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next)
 785                 err_printf(m, "Active process (on ring %s): %s [%d]\n",
 786                            ee->engine->name,
 787                            ee->context.comm,
 788                            ee->context.pid);
 789
 790         err_printf(m, "Reset count: %u\n", error->reset_count);
 791         err_printf(m, "Suspend count: %u\n", error->suspend_count);
 792         err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
 793         err_printf(m, "Subplatform: 0x%x\n",
 794                    intel_subplatform(&error->runtime_info,
 795                                      error->device_info.platform));
 796         err_print_pciid(m, m->i915);
 797
 798         err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
 799
 800         if (HAS_CSR(m->i915)) {
 801                 struct intel_csr *csr = &m->i915->csr;
 802
 803                 err_printf(m, "DMC loaded: %s\n",
 804                            yesno(csr->dmc_payload != NULL));
 805                 err_printf(m, "DMC fw version: %d.%d\n",
 806                            CSR_VERSION_MAJOR(csr->version),
 807                            CSR_VERSION_MINOR(csr->version));
 808         }
 809
 810         err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
 811         err_printf(m, "PM suspended: %s\n", yesno(error->suspended));
 812
 813         if (error->gt)
 814                 err_print_gt(m, error->gt);
 815
 816         if (error->overlay)
 817                 intel_overlay_print_error_state(m, error->overlay);
 818
 819         if (error->display)
 820                 intel_display_print_error_state(m, error->display);
 821
 822         err_print_capabilities(m, error);
 823         err_print_params(m, &error->params);
 824 }
 825
 826 static int err_print_to_sgl(struct i915_gpu_coredump *error)
 827 {
 828         struct drm_i915_error_state_buf m;
 829
 830         if (IS_ERR(error))
 831                 return PTR_ERR(error);
 832
 833         if (READ_ONCE(error->sgl))
 834                 return 0;
 835
 836         memset(&m, 0, sizeof(m));
 837         m.i915 = error->i915;
 838
 839         __err_print_to_sgl(&m, error);
 840
 841         if (m.buf) {
 842                 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter);
 843                 m.bytes = 0;
 844                 m.buf = NULL;
 845         }
 846         if (m.cur) {
 847                 GEM_BUG_ON(m.end < m.cur);
 848                 sg_mark_end(m.cur - 1);
 849         }
 850         GEM_BUG_ON(m.sgl && !m.cur);
 851
 852         if (m.err) {
 853                 err_free_sgl(m.sgl);
 854                 return m.err;
 855         }
 856
 857         if (cmpxchg(&error->sgl, NULL, m.sgl))
 858                 err_free_sgl(m.sgl);
 859
 860         return 0;
 861 }
 862
 863 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error,
 864                                          char *buf, loff_t off, size_t rem)
 865 {
 866         struct scatterlist *sg;
 867         size_t count;
 868         loff_t pos;
 869         int err;
 870
 871         if (!error || !rem)
 872                 return 0;
 873
 874         err = err_print_to_sgl(error);
 875         if (err)
 876                 return err;
 877
 878         sg = READ_ONCE(error->fit);
 879         if (!sg || off < sg->dma_address)
 880                 sg = error->sgl;
 881         if (!sg)
 882                 return 0;
 883
 884         pos = sg->dma_address;
 885         count = 0;
 886         do {
 887                 size_t len, start;
 888
 889                 if (sg_is_chain(sg)) {
 890                         sg = sg_chain_ptr(sg);
 891                         GEM_BUG_ON(sg_is_chain(sg));
 892                 }
 893
 894                 len = sg->length;
 895                 if (pos + len <= off) {
 896                         pos += len;
 897                         continue;
 898                 }
 899
 900                 start = sg->offset;
 901                 if (pos < off) {
 902                         GEM_BUG_ON(off - pos > len);
 903                         len -= off - pos;
 904                         start += off - pos;
 905                         pos = off;
 906                 }
 907
 908                 len = min(len, rem);
 909                 GEM_BUG_ON(!len || len > sg->length);
 910
 911                 memcpy(buf, page_address(sg_page(sg)) + start, len);
 912
 913                 count += len;
 914                 pos += len;
 915
 916                 buf += len;
 917                 rem -= len;
 918                 if (!rem) {
 919                         WRITE_ONCE(error->fit, sg);
 920                         break;
 921                 }
 922         } while (!sg_is_last(sg++));
 923
 924         return count;
 925 }
 926
 927 static void i915_vma_coredump_free(struct i915_vma_coredump *vma)
 928 {
 929         while (vma) {
 930                 struct i915_vma_coredump *next = vma->next;
 931                 int page;
 932
 933                 for (page = 0; page < vma->page_count; page++)
 934                         free_page((unsigned long)vma->pages[page]);
 935
 936                 kfree(vma);
 937                 vma = next;
 938         }
 939 }
 940
 941 static void cleanup_params(struct i915_gpu_coredump *error)
 942 {
 943         i915_params_free(&error->params);
 944 }
 945
 946 static void cleanup_uc(struct intel_uc_coredump *uc)
 947 {
 948         kfree(uc->guc_fw.path);
 949         kfree(uc->huc_fw.path);
 950         i915_vma_coredump_free(uc->guc_log);
 951
 952         kfree(uc);
 953 }
 954
 955 static void cleanup_gt(struct intel_gt_coredump *gt)
 956 {
 957         while (gt->engine) {
 958                 struct intel_engine_coredump *ee = gt->engine;
 959
 960                 gt->engine = ee->next;
 961
 962                 i915_vma_coredump_free(ee->vma);
 963                 kfree(ee);
 964         }
 965
 966         if (gt->uc)
 967                 cleanup_uc(gt->uc);
 968
 969         kfree(gt);
 970 }
 971
 972 void __i915_gpu_coredump_free(struct kref *error_ref)
 973 {
 974         struct i915_gpu_coredump *error =
 975                 container_of(error_ref, typeof(*error), ref);
 976
 977         while (error->gt) {
 978                 struct intel_gt_coredump *gt = error->gt;
 979
 980                 error->gt = gt->next;
 981                 cleanup_gt(gt);
 982         }
 983
 984         kfree(error->overlay);
 985         kfree(error->display);
 986
 987         cleanup_params(error);
 988
 989         err_free_sgl(error->sgl);
 990         kfree(error);
 991 }
 992
 993 static struct i915_vma_coredump *
 994 i915_vma_coredump_create(const struct intel_gt *gt,
 995                          const struct i915_vma *vma,
 996                          const char *name,
 997                          struct i915_vma_compress *compress)
 998 {
 999         struct i915_ggtt *ggtt = gt->ggtt;
1000         const u64 slot = ggtt->error_capture.start;
1001         struct i915_vma_coredump *dst;
1002         unsigned long num_pages;
1003         struct sgt_iter iter;
1004         int ret;
1005
1006         might_sleep();
1007
1008         if (!vma || !vma->pages || !compress)
1009                 return NULL;
1010
1011         num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
1012         num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
1013         dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), ALLOW_FAIL);
1014         if (!dst)
1015                 return NULL;
1016
1017         if (!compress_start(compress)) {
1018                 kfree(dst);
1019                 return NULL;
1020         }
1021
1022         strcpy(dst->name, name);
1023         dst->next = NULL;
1024
1025         dst->gtt_offset = vma->node.start;
1026         dst->gtt_size = vma->node.size;
1027         dst->gtt_page_sizes = vma->page_sizes.gtt;
1028         dst->num_pages = num_pages;
1029         dst->page_count = 0;
1030         dst->unused = 0;
1031
1032         ret = -EINVAL;
1033         if (drm_mm_node_allocated(&ggtt->error_capture)) {
1034                 void __iomem *s;
1035                 dma_addr_t dma;
1036
1037                 for_each_sgt_daddr(dma, iter, vma->pages) {
1038                         ggtt->vm.insert_page(&ggtt->vm, dma, slot,
1039                                              I915_CACHE_NONE, 0);
1040                         mb();
1041
1042                         s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
1043                         ret = compress_page(compress,
1044                                             (void  __force *)s, dst,
1045                                             true);
1046                         io_mapping_unmap(s);
1047                         if (ret)
1048                                 break;
1049                 }
1050         } else if (i915_gem_object_is_lmem(vma->obj)) {
1051                 struct intel_memory_region *mem = vma->obj->mm.region;
1052                 dma_addr_t dma;
1053
1054                 for_each_sgt_daddr(dma, iter, vma->pages) {
1055                         void __iomem *s;
1056
1057                         s = io_mapping_map_wc(&mem->iomap, dma, PAGE_SIZE);
1058                         ret = compress_page(compress,
1059                                             (void __force *)s, dst,
1060                                             true);
1061                         io_mapping_unmap(s);
1062                         if (ret)
1063                                 break;
1064                 }
1065         } else {
1066                 struct page *page;
1067
1068                 for_each_sgt_page(page, iter, vma->pages) {
1069                         void *s;
1070
1071                         drm_clflush_pages(&page, 1);
1072
1073                         s = kmap(page);
1074                         ret = compress_page(compress, s, dst, false);
1075                         kunmap(page);
1076
1077                         drm_clflush_pages(&page, 1);
1078
1079                         if (ret)
1080                                 break;
1081                 }
1082         }
1083
1084         if (ret || compress_flush(compress, dst)) {
1085                 while (dst->page_count--)
1086                         pool_free(&compress->pool, dst->pages[dst->page_count]);
1087                 kfree(dst);
1088                 dst = NULL;
1089         }
1090         compress_finish(compress);
1091
1092         return dst;
1093 }
1094
1095 static void gt_record_fences(struct intel_gt_coredump *gt)
1096 {
1097         struct i915_ggtt *ggtt = gt->_gt->ggtt;
1098         struct intel_uncore *uncore = gt->_gt->uncore;
1099         int i;
1100
1101         if (INTEL_GEN(uncore->i915) >= 6) {
1102                 for (i = 0; i < ggtt->num_fences; i++)
1103                         gt->fence[i] =
1104                                 intel_uncore_read64(uncore,
1105                                                     FENCE_REG_GEN6_LO(i));
1106         } else if (INTEL_GEN(uncore->i915) >= 4) {
1107                 for (i = 0; i < ggtt->num_fences; i++)
1108                         gt->fence[i] =
1109                                 intel_uncore_read64(uncore,
1110                                                     FENCE_REG_965_LO(i));
1111         } else {
1112                 for (i = 0; i < ggtt->num_fences; i++)
1113                         gt->fence[i] =
1114                                 intel_uncore_read(uncore, FENCE_REG(i));
1115         }
1116         gt->nfence = i;
1117 }
1118
1119 static void engine_record_registers(struct intel_engine_coredump *ee)
1120 {
1121         const struct intel_engine_cs *engine = ee->engine;
1122         struct drm_i915_private *i915 = engine->i915;
1123
1124         if (INTEL_GEN(i915) >= 6) {
1125                 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);
1126
1127                 if (INTEL_GEN(i915) >= 12)
1128                         ee->fault_reg = intel_uncore_read(engine->uncore,
1129                                                           GEN12_RING_FAULT_REG);
1130                 else if (INTEL_GEN(i915) >= 8)
1131                         ee->fault_reg = intel_uncore_read(engine->uncore,
1132                                                           GEN8_RING_FAULT_REG);
1133                 else
1134                         ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);
1135         }
1136
1137         if (INTEL_GEN(i915) >= 4) {
1138                 ee->esr = ENGINE_READ(engine, RING_ESR);
1139                 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD);
1140                 ee->ipeir = ENGINE_READ(engine, RING_IPEIR);
1141                 ee->ipehr = ENGINE_READ(engine, RING_IPEHR);
1142                 ee->instps = ENGINE_READ(engine, RING_INSTPS);
1143                 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR);
1144                 ee->ccid = ENGINE_READ(engine, CCID);
1145                 if (INTEL_GEN(i915) >= 8) {
1146                         ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32;
1147                         ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32;
1148                 }
1149                 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE);
1150         } else {
1151                 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX);
1152                 ee->ipeir = ENGINE_READ(engine, IPEIR);
1153                 ee->ipehr = ENGINE_READ(engine, IPEHR);
1154         }
1155
1156         intel_engine_get_instdone(engine, &ee->instdone);
1157
1158         ee->instpm = ENGINE_READ(engine, RING_INSTPM);
1159         ee->acthd = intel_engine_get_active_head(engine);
1160         ee->start = ENGINE_READ(engine, RING_START);
1161         ee->head = ENGINE_READ(engine, RING_HEAD);
1162         ee->tail = ENGINE_READ(engine, RING_TAIL);
1163         ee->ctl = ENGINE_READ(engine, RING_CTL);
1164         if (INTEL_GEN(i915) > 2)
1165                 ee->mode = ENGINE_READ(engine, RING_MI_MODE);
1166
1167         if (!HWS_NEEDS_PHYSICAL(i915)) {
1168                 i915_reg_t mmio;
1169
1170                 if (IS_GEN(i915, 7)) {
1171                         switch (engine->id) {
1172                         default:
1173                                 MISSING_CASE(engine->id);
1174                                 fallthrough;
1175                         case RCS0:
1176                                 mmio = RENDER_HWS_PGA_GEN7;
1177                                 break;
1178                         case BCS0:
1179                                 mmio = BLT_HWS_PGA_GEN7;
1180                                 break;
1181                         case VCS0:
1182                                 mmio = BSD_HWS_PGA_GEN7;
1183                                 break;
1184                         case VECS0:
1185                                 mmio = VEBOX_HWS_PGA_GEN7;
1186                                 break;
1187                         }
1188                 } else if (IS_GEN(engine->i915, 6)) {
1189                         mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1190                 } else {
1191                         /* XXX: gen8 returns to sanity */
1192                         mmio = RING_HWS_PGA(engine->mmio_base);
1193                 }
1194
1195                 ee->hws = intel_uncore_read(engine->uncore, mmio);
1196         }
1197
1198         ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine);
1199
1200         if (HAS_PPGTT(i915)) {
1201                 int i;
1202
1203                 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7);
1204
1205                 if (IS_GEN(i915, 6)) {
1206                         ee->vm_info.pp_dir_base =
1207                                 ENGINE_READ(engine, RING_PP_DIR_BASE_READ);
1208                 } else if (IS_GEN(i915, 7)) {
1209                         ee->vm_info.pp_dir_base =
1210                                 ENGINE_READ(engine, RING_PP_DIR_BASE);
1211                 } else if (INTEL_GEN(i915) >= 8) {
1212                         u32 base = engine->mmio_base;
1213
1214                         for (i = 0; i < 4; i++) {
1215                                 ee->vm_info.pdp[i] =
1216                                         intel_uncore_read(engine->uncore,
1217                                                           GEN8_RING_PDP_UDW(base, i));
1218                                 ee->vm_info.pdp[i] <<= 32;
1219                                 ee->vm_info.pdp[i] |=
1220                                         intel_uncore_read(engine->uncore,
1221                                                           GEN8_RING_PDP_LDW(base, i));
1222                         }
1223                 }
1224         }
1225 }
1226
1227 static void record_request(const struct i915_request *request,
1228                            struct i915_request_coredump *erq)
1229 {
1230         erq->flags = request->fence.flags;
1231         erq->context = request->fence.context;
1232         erq->seqno = request->fence.seqno;
1233         erq->sched_attr = request->sched.attr;
1234         erq->head = request->head;
1235         erq->tail = request->tail;
1236
1237         erq->pid = 0;
1238         rcu_read_lock();
1239         if (!intel_context_is_closed(request->context)) {
1240                 const struct i915_gem_context *ctx;
1241
1242                 ctx = rcu_dereference(request->context->gem_context);
1243                 if (ctx)
1244                         erq->pid = pid_nr(ctx->pid);
1245         }
1246         rcu_read_unlock();
1247 }
1248
1249 static void engine_record_execlists(struct intel_engine_coredump *ee)
1250 {
1251         const struct intel_engine_execlists * const el = &ee->engine->execlists;
1252         struct i915_request * const *port = el->active;
1253         unsigned int n = 0;
1254
1255         while (*port)
1256                 record_request(*port++, &ee->execlist[n++]);
1257
1258         ee->num_ports = n;
1259 }
1260
1261 static bool record_context(struct i915_gem_context_coredump *e,
1262                            const struct i915_request *rq)
1263 {
1264         struct i915_gem_context *ctx;
1265         struct task_struct *task;
1266         bool simulated;
1267
1268         rcu_read_lock();
1269         ctx = rcu_dereference(rq->context->gem_context);
1270         if (ctx && !kref_get_unless_zero(&ctx->ref))
1271                 ctx = NULL;
1272         rcu_read_unlock();
1273         if (!ctx)
1274                 return true;
1275
1276         rcu_read_lock();
1277         task = pid_task(ctx->pid, PIDTYPE_PID);
1278         if (task) {
1279                 strcpy(e->comm, task->comm);
1280                 e->pid = task->pid;
1281         }
1282         rcu_read_unlock();
1283
1284         e->sched_attr = ctx->sched;
1285         e->guilty = atomic_read(&ctx->guilty_count);
1286         e->active = atomic_read(&ctx->active_count);
1287
1288         e->total_runtime = rq->context->runtime.total;
1289         e->avg_runtime = ewma_runtime_read(&rq->context->runtime.avg);
1290
1291         simulated = i915_gem_context_no_error_capture(ctx);
1292
1293         i915_gem_context_put(ctx);
1294         return simulated;
1295 }
1296
1297 struct intel_engine_capture_vma {
1298         struct intel_engine_capture_vma *next;
1299         struct i915_vma *vma;
1300         char name[16];
1301 };
1302
1303 static struct intel_engine_capture_vma *
1304 capture_vma(struct intel_engine_capture_vma *next,
1305             struct i915_vma *vma,
1306             const char *name,
1307             gfp_t gfp)
1308 {
1309         struct intel_engine_capture_vma *c;
1310
1311         if (!vma)
1312                 return next;
1313
1314         c = kmalloc(sizeof(*c), gfp);
1315         if (!c)
1316                 return next;
1317
1318         if (!i915_active_acquire_if_busy(&vma->active)) {
1319                 kfree(c);
1320                 return next;
1321         }
1322
1323         strcpy(c->name, name);
1324         c->vma = vma; /* reference held while active */
1325
1326         c->next = next;
1327         return c;
1328 }
1329
1330 static struct intel_engine_capture_vma *
1331 capture_user(struct intel_engine_capture_vma *capture,
1332              const struct i915_request *rq,
1333              gfp_t gfp)
1334 {
1335         struct i915_capture_list *c;
1336
1337         for (c = rq->capture_list; c; c = c->next)
1338                 capture = capture_vma(capture, c->vma, "user", gfp);
1339
1340         return capture;
1341 }
1342
1343 static void add_vma(struct intel_engine_coredump *ee,
1344                     struct i915_vma_coredump *vma)
1345 {
1346         if (vma) {
1347                 vma->next = ee->vma;
1348                 ee->vma = vma;
1349         }
1350 }
1351
1352 struct intel_engine_coredump *
1353 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp)
1354 {
1355         struct intel_engine_coredump *ee;
1356
1357         ee = kzalloc(sizeof(*ee), gfp);
1358         if (!ee)
1359                 return NULL;
1360
1361         ee->engine = engine;
1362
1363         engine_record_registers(ee);
1364         engine_record_execlists(ee);
1365
1366         return ee;
1367 }
1368
1369 struct intel_engine_capture_vma *
1370 intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
1371                                   struct i915_request *rq,
1372                                   gfp_t gfp)
1373 {
1374         struct intel_engine_capture_vma *vma = NULL;
1375
1376         ee->simulated |= record_context(&ee->context, rq);
1377         if (ee->simulated)
1378                 return NULL;
1379
1380         /*
1381          * We need to copy these to an anonymous buffer
1382          * as the simplest method to avoid being overwritten
1383          * by userspace.
1384          */
1385         vma = capture_vma(vma, rq->batch, "batch", gfp);
1386         vma = capture_user(vma, rq, gfp);
1387         vma = capture_vma(vma, rq->ring->vma, "ring", gfp);
1388         vma = capture_vma(vma, rq->context->state, "HW context", gfp);
1389
1390         ee->rq_head = rq->head;
1391         ee->rq_post = rq->postfix;
1392         ee->rq_tail = rq->tail;
1393
1394         return vma;
1395 }
1396
1397 void
1398 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
1399                               struct intel_engine_capture_vma *capture,
1400                               struct i915_vma_compress *compress)
1401 {
1402         const struct intel_engine_cs *engine = ee->engine;
1403
1404         while (capture) {
1405                 struct intel_engine_capture_vma *this = capture;
1406                 struct i915_vma *vma = this->vma;
1407
1408                 add_vma(ee,
1409                         i915_vma_coredump_create(engine->gt,
1410                                                  vma, this->name,
1411                                                  compress));
1412
1413                 i915_active_release(&vma->active);
1414
1415                 capture = this->next;
1416                 kfree(this);
1417         }
1418
1419         add_vma(ee,
1420                 i915_vma_coredump_create(engine->gt,
1421                                          engine->status_page.vma,
1422                                          "HW Status",
1423                                          compress));
1424
1425         add_vma(ee,
1426                 i915_vma_coredump_create(engine->gt,
1427                                          engine->wa_ctx.vma,
1428                                          "WA context",
1429                                          compress));
1430 }
1431
1432 static struct intel_engine_coredump *
1433 capture_engine(struct intel_engine_cs *engine,
1434                struct i915_vma_compress *compress)
1435 {
1436         struct intel_engine_capture_vma *capture = NULL;
1437         struct intel_engine_coredump *ee;
1438         struct i915_request *rq;
1439         unsigned long flags;
1440
1441         ee = intel_engine_coredump_alloc(engine, GFP_KERNEL);
1442         if (!ee)
1443                 return NULL;
1444
1445         spin_lock_irqsave(&engine->active.lock, flags);
1446         rq = intel_engine_find_active_request(engine);
1447         if (rq)
1448                 capture = intel_engine_coredump_add_request(ee, rq,
1449                                                             ATOMIC_MAYFAIL);
1450         spin_unlock_irqrestore(&engine->active.lock, flags);
1451         if (!capture) {
1452                 kfree(ee);
1453                 return NULL;
1454         }
1455
1456         intel_engine_coredump_add_vma(ee, capture, compress);
1457
1458         return ee;
1459 }
1460
1461 static void
1462 gt_record_engines(struct intel_gt_coredump *gt,
1463                   struct i915_vma_compress *compress)
1464 {
1465         struct intel_engine_cs *engine;
1466         enum intel_engine_id id;
1467
1468         for_each_engine(engine, gt->_gt, id) {
1469                 struct intel_engine_coredump *ee;
1470
1471                 /* Refill our page pool before entering atomic section */
1472                 pool_refill(&compress->pool, ALLOW_FAIL);
1473
1474                 ee = capture_engine(engine, compress);
1475                 if (!ee)
1476                         continue;
1477
1478                 gt->simulated |= ee->simulated;
1479                 if (ee->simulated) {
1480                         kfree(ee);
1481                         continue;
1482                 }
1483
1484                 ee->next = gt->engine;
1485                 gt->engine = ee;
1486         }
1487 }
1488
1489 static struct intel_uc_coredump *
1490 gt_record_uc(struct intel_gt_coredump *gt,
1491              struct i915_vma_compress *compress)
1492 {
1493         const struct intel_uc *uc = &gt->_gt->uc;
1494         struct intel_uc_coredump *error_uc;
1495
1496         error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL);
1497         if (!error_uc)
1498                 return NULL;
1499
1500         memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw));
1501         memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw));
1502
1503         /* Non-default firmware paths will be specified by the modparam.
1504          * As modparams are generally accesible from the userspace make
1505          * explicit copies of the firmware paths.
1506          */
1507         error_uc->guc_fw.path = kstrdup(uc->guc.fw.path, ALLOW_FAIL);
1508         error_uc->huc_fw.path = kstrdup(uc->huc.fw.path, ALLOW_FAIL);
1509         error_uc->guc_log =
1510                 i915_vma_coredump_create(gt->_gt,
1511                                          uc->guc.log.vma, "GuC log buffer",
1512                                          compress);
1513
1514         return error_uc;
1515 }
1516
1517 static void gt_capture_prepare(struct intel_gt_coredump *gt)
1518 {
1519         struct i915_ggtt *ggtt = gt->_gt->ggtt;
1520
1521         mutex_lock(&ggtt->error_mutex);
1522 }
1523
1524 static void gt_capture_finish(struct intel_gt_coredump *gt)
1525 {
1526         struct i915_ggtt *ggtt = gt->_gt->ggtt;
1527
1528         if (drm_mm_node_allocated(&ggtt->error_capture))
1529                 ggtt->vm.clear_range(&ggtt->vm,
1530                                      ggtt->error_capture.start,
1531                                      PAGE_SIZE);
1532
1533         mutex_unlock(&ggtt->error_mutex);
1534 }
1535
1536 /* Capture all registers which don't fit into another category. */
1537 static void gt_record_regs(struct intel_gt_coredump *gt)
1538 {
1539         struct intel_uncore *uncore = gt->_gt->uncore;
1540         struct drm_i915_private *i915 = uncore->i915;
1541         int i;
1542
1543         /*
1544          * General organization
1545          * 1. Registers specific to a single generation
1546          * 2. Registers which belong to multiple generations
1547          * 3. Feature specific registers.
1548          * 4. Everything else
1549          * Please try to follow the order.
1550          */
1551
1552         /* 1: Registers specific to a single generation */
1553         if (IS_VALLEYVIEW(i915)) {
1554                 gt->gtier[0] = intel_uncore_read(uncore, GTIER);
1555                 gt->ier = intel_uncore_read(uncore, VLV_IER);
1556                 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV);
1557         }
1558
1559         if (IS_GEN(i915, 7))
1560                 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);
1561
1562         if (INTEL_GEN(i915) >= 12) {
1563                 gt->fault_data0 = intel_uncore_read(uncore,
1564                                                     GEN12_FAULT_TLB_DATA0);
1565                 gt->fault_data1 = intel_uncore_read(uncore,
1566                                                     GEN12_FAULT_TLB_DATA1);
1567         } else if (INTEL_GEN(i915) >= 8) {
1568                 gt->fault_data0 = intel_uncore_read(uncore,
1569                                                     GEN8_FAULT_TLB_DATA0);
1570                 gt->fault_data1 = intel_uncore_read(uncore,
1571                                                     GEN8_FAULT_TLB_DATA1);
1572         }
1573
1574         if (IS_GEN(i915, 6)) {
1575                 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE);
1576                 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL);
1577                 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE);
1578         }
1579
1580         /* 2: Registers which belong to multiple generations */
1581         if (INTEL_GEN(i915) >= 7)
1582                 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
1583
1584         if (INTEL_GEN(i915) >= 6) {
1585                 gt->derrmr = intel_uncore_read(uncore, DERRMR);
1586                 if (INTEL_GEN(i915) < 12) {
1587                         gt->error = intel_uncore_read(uncore, ERROR_GEN6);
1588                         gt->done_reg = intel_uncore_read(uncore, DONE_REG);
1589                 }
1590         }
1591
1592         /* 3: Feature specific registers */
1593         if (IS_GEN_RANGE(i915, 6, 7)) {
1594                 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
1595                 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS);
1596         }
1597
1598         if (IS_GEN_RANGE(i915, 8, 11))
1599                 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN);
1600
1601         if (IS_GEN(i915, 12))
1602                 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG);
1603
1604         if (INTEL_GEN(i915) >= 12) {
1605                 for (i = 0; i < GEN12_SFC_DONE_MAX; i++) {
1606                         /*
1607                          * SFC_DONE resides in the VD forcewake domain, so it
1608                          * only exists if the corresponding VCS engine is
1609                          * present.
1610                          */
1611                         if (!HAS_ENGINE(gt->_gt, _VCS(i * 2)))
1612                                 continue;
1613
1614                         gt->sfc_done[i] =
1615                                 intel_uncore_read(uncore, GEN12_SFC_DONE(i));
1616                 }
1617
1618                 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE);
1619         }
1620
1621         /* 4: Everything else */
1622         if (INTEL_GEN(i915) >= 11) {
1623                 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);
1624                 gt->gtier[0] =
1625                         intel_uncore_read(uncore,
1626                                           GEN11_RENDER_COPY_INTR_ENABLE);
1627                 gt->gtier[1] =
1628                         intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE);
1629                 gt->gtier[2] =
1630                         intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE);
1631                 gt->gtier[3] =
1632                         intel_uncore_read(uncore,
1633                                           GEN11_GPM_WGBOXPERF_INTR_ENABLE);
1634                 gt->gtier[4] =
1635                         intel_uncore_read(uncore,
1636                                           GEN11_CRYPTO_RSVD_INTR_ENABLE);
1637                 gt->gtier[5] =
1638                         intel_uncore_read(uncore,
1639                                           GEN11_GUNIT_CSME_INTR_ENABLE);
1640                 gt->ngtier = 6;
1641         } else if (INTEL_GEN(i915) >= 8) {
1642                 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);
1643                 for (i = 0; i < 4; i++)
1644                         gt->gtier[i] =
1645                                 intel_uncore_read(uncore, GEN8_GT_IER(i));
1646                 gt->ngtier = 4;
1647         } else if (HAS_PCH_SPLIT(i915)) {
1648                 gt->ier = intel_uncore_read(uncore, DEIER);
1649                 gt->gtier[0] = intel_uncore_read(uncore, GTIER);
1650                 gt->ngtier = 1;
1651         } else if (IS_GEN(i915, 2)) {
1652                 gt->ier = intel_uncore_read16(uncore, GEN2_IER);
1653         } else if (!IS_VALLEYVIEW(i915)) {
1654                 gt->ier = intel_uncore_read(uncore, GEN2_IER);
1655         }
1656         gt->eir = intel_uncore_read(uncore, EIR);
1657         gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER);
1658 }
1659
1660 static void gt_record_info(struct intel_gt_coredump *gt)
1661 {
1662         memcpy(&gt->info, &gt->_gt->info, sizeof(struct intel_gt_info));
1663 }
1664
1665 /*
1666  * Generate a semi-unique error code. The code is not meant to have meaning, The
1667  * code's only purpose is to try to prevent false duplicated bug reports by
1668  * grossly estimating a GPU error state.
1669  *
1670  * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
1671  * the hang if we could strip the GTT offset information from it.
1672  *
1673  * It's only a small step better than a random number in its current form.
1674  */
1675 static u32 generate_ecode(const struct intel_engine_coredump *ee)
1676 {
1677         /*
1678          * IPEHR would be an ideal way to detect errors, as it's the gross
1679          * measure of "the command that hung." However, has some very common
1680          * synchronization commands which almost always appear in the case
1681          * strictly a client bug. Use instdone to differentiate those some.
1682          */
1683         return ee ? ee->ipehr ^ ee->instdone.instdone : 0;
1684 }
1685
1686 static const char *error_msg(struct i915_gpu_coredump *error)
1687 {
1688         struct intel_engine_coredump *first = NULL;
1689         struct intel_gt_coredump *gt;
1690         intel_engine_mask_t engines;
1691         int len;
1692
1693         engines = 0;
1694         for (gt = error->gt; gt; gt = gt->next) {
1695                 struct intel_engine_coredump *cs;
1696
1697                 if (gt->engine && !first)
1698                         first = gt->engine;
1699
1700                 for (cs = gt->engine; cs; cs = cs->next)
1701                         engines |= cs->engine->mask;
1702         }
1703
1704         len = scnprintf(error->error_msg, sizeof(error->error_msg),
1705                         "GPU HANG: ecode %d:%x:%08x",
1706                         INTEL_GEN(error->i915), engines,
1707                         generate_ecode(first));
1708         if (first && first->context.pid) {
1709                 /* Just show the first executing process, more is confusing */
1710                 len += scnprintf(error->error_msg + len,
1711                                  sizeof(error->error_msg) - len,
1712                                  ", in %s [%d]",
1713                                  first->context.comm, first->context.pid);
1714         }
1715
1716         return error->error_msg;
1717 }
1718
1719 static void capture_gen(struct i915_gpu_coredump *error)
1720 {
1721         struct drm_i915_private *i915 = error->i915;
1722
1723         error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count);
1724         error->suspended = i915->runtime_pm.suspended;
1725
1726         error->iommu = -1;
1727 #ifdef CONFIG_INTEL_IOMMU
1728         error->iommu = intel_iommu_gfx_mapped;
1729 #endif
1730         error->reset_count = i915_reset_count(&i915->gpu_error);
1731         error->suspend_count = i915->suspend_count;
1732
1733         i915_params_copy(&error->params, &i915->params);
1734         memcpy(&error->device_info,
1735                INTEL_INFO(i915),
1736                sizeof(error->device_info));
1737         memcpy(&error->runtime_info,
1738                RUNTIME_INFO(i915),
1739                sizeof(error->runtime_info));
1740         error->driver_caps = i915->caps;
1741 }
1742
1743 struct i915_gpu_coredump *
1744 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp)
1745 {
1746         struct i915_gpu_coredump *error;
1747
1748         if (!i915->params.error_capture)
1749                 return NULL;
1750
1751         error = kzalloc(sizeof(*error), gfp);
1752         if (!error)
1753                 return NULL;
1754
1755         kref_init(&error->ref);
1756         error->i915 = i915;
1757
1758         error->time = ktime_get_real();
1759         error->boottime = ktime_get_boottime();
1760         error->uptime = ktime_sub(ktime_get(), i915->gt.last_init_time);
1761         error->capture = jiffies;
1762
1763         capture_gen(error);
1764
1765         return error;
1766 }
1767
1768 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
1769
1770 struct intel_gt_coredump *
1771 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp)
1772 {
1773         struct intel_gt_coredump *gc;
1774
1775         gc = kzalloc(sizeof(*gc), gfp);
1776         if (!gc)
1777                 return NULL;
1778
1779         gc->_gt = gt;
1780         gc->awake = intel_gt_pm_is_awake(gt);
1781
1782         gt_record_regs(gc);
1783         gt_record_fences(gc);
1784
1785         return gc;
1786 }
1787
1788 struct i915_vma_compress *
1789 i915_vma_capture_prepare(struct intel_gt_coredump *gt)
1790 {
1791         struct i915_vma_compress *compress;
1792
1793         compress = kmalloc(sizeof(*compress), ALLOW_FAIL);
1794         if (!compress)
1795                 return NULL;
1796
1797         if (!compress_init(compress)) {
1798                 kfree(compress);
1799                 return NULL;
1800         }
1801
1802         gt_capture_prepare(gt);
1803
1804         return compress;
1805 }
1806
1807 void i915_vma_capture_finish(struct intel_gt_coredump *gt,
1808                              struct i915_vma_compress *compress)
1809 {
1810         if (!compress)
1811                 return;
1812
1813         gt_capture_finish(gt);
1814
1815         compress_fini(compress);
1816         kfree(compress);
1817 }
1818
1819 struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915)
1820 {
1821         struct i915_gpu_coredump *error;
1822
1823         /* Check if GPU capture has been disabled */
1824         error = READ_ONCE(i915->gpu_error.first_error);
1825         if (IS_ERR(error))
1826                 return error;
1827
1828         error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL);
1829         if (!error)
1830                 return ERR_PTR(-ENOMEM);
1831
1832         error->gt = intel_gt_coredump_alloc(&i915->gt, ALLOW_FAIL);
1833         if (error->gt) {
1834                 struct i915_vma_compress *compress;
1835
1836                 compress = i915_vma_capture_prepare(error->gt);
1837                 if (!compress) {
1838                         kfree(error->gt);
1839                         kfree(error);
1840                         return ERR_PTR(-ENOMEM);
1841                 }
1842
1843                 gt_record_info(error->gt);
1844                 gt_record_engines(error->gt, compress);
1845
1846                 if (INTEL_INFO(i915)->has_gt_uc)
1847                         error->gt->uc = gt_record_uc(error->gt, compress);
1848
1849                 i915_vma_capture_finish(error->gt, compress);
1850
1851                 error->simulated |= error->gt->simulated;
1852         }
1853
1854         error->overlay = intel_overlay_capture_error_state(i915);
1855         error->display = intel_display_capture_error_state(i915);
1856
1857         return error;
1858 }
1859
1860 void i915_error_state_store(struct i915_gpu_coredump *error)
1861 {
1862         struct drm_i915_private *i915;
1863         static bool warned;
1864
1865         if (IS_ERR_OR_NULL(error))
1866                 return;
1867
1868         i915 = error->i915;
1869         drm_info(&i915->drm, "%s\n", error_msg(error));
1870
1871         if (error->simulated ||
1872             cmpxchg(&i915->gpu_error.first_error, NULL, error))
1873                 return;
1874
1875         i915_gpu_coredump_get(error);
1876
1877         if (!xchg(&warned, true) &&
1878             ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
1879                 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1880                 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n");
1881                 pr_info("Please see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.\n");
1882                 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1883                 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n");
1884                 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1885                         i915->drm.primary->index);
1886         }
1887 }
1888
1889 /**
1890  * i915_capture_error_state - capture an error record for later analysis
1891  * @i915: i915 device
1892  *
1893  * Should be called when an error is detected (either a hang or an error
1894  * interrupt) to capture error state from the time of the error.  Fills
1895  * out a structure which becomes available in debugfs for user level tools
1896  * to pick up.
1897  */
1898 void i915_capture_error_state(struct drm_i915_private *i915)
1899 {
1900         struct i915_gpu_coredump *error;
1901
1902         error = i915_gpu_coredump(i915);
1903         if (IS_ERR(error)) {
1904                 cmpxchg(&i915->gpu_error.first_error, NULL, error);
1905                 return;
1906         }
1907
1908         i915_error_state_store(error);
1909         i915_gpu_coredump_put(error);
1910 }
1911
1912 struct i915_gpu_coredump *
1913 i915_first_error_state(struct drm_i915_private *i915)
1914 {
1915         struct i915_gpu_coredump *error;
1916
1917         spin_lock_irq(&i915->gpu_error.lock);
1918         error = i915->gpu_error.first_error;
1919         if (!IS_ERR_OR_NULL(error))
1920                 i915_gpu_coredump_get(error);
1921         spin_unlock_irq(&i915->gpu_error.lock);
1922
1923         return error;
1924 }
1925
1926 void i915_reset_error_state(struct drm_i915_private *i915)
1927 {
1928         struct i915_gpu_coredump *error;
1929
1930         spin_lock_irq(&i915->gpu_error.lock);
1931         error = i915->gpu_error.first_error;
1932         if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */
1933                 i915->gpu_error.first_error = NULL;
1934         spin_unlock_irq(&i915->gpu_error.lock);
1935
1936         if (!IS_ERR_OR_NULL(error))
1937                 i915_gpu_coredump_put(error);
1938 }
1939
1940 void i915_disable_error_state(struct drm_i915_private *i915, int err)
1941 {
1942         spin_lock_irq(&i915->gpu_error.lock);
1943         if (!i915->gpu_error.first_error)
1944                 i915->gpu_error.first_error = ERR_PTR(err);
1945         spin_unlock_irq(&i915->gpu_error.lock);
1946 }