1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2014, Sony Mobile Communications AB.
8 #include <linux/acpi.h>
9 #include <linux/atomic.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/dmaengine.h>
13 #include <linux/dmapool.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
16 #include <linux/i2c.h>
17 #include <linux/interrupt.h>
19 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/scatterlist.h>
26 #define QUP_CONFIG 0x000
27 #define QUP_STATE 0x004
28 #define QUP_IO_MODE 0x008
29 #define QUP_SW_RESET 0x00c
30 #define QUP_OPERATIONAL 0x018
31 #define QUP_ERROR_FLAGS 0x01c
32 #define QUP_ERROR_FLAGS_EN 0x020
33 #define QUP_OPERATIONAL_MASK 0x028
34 #define QUP_HW_VERSION 0x030
35 #define QUP_MX_OUTPUT_CNT 0x100
36 #define QUP_OUT_FIFO_BASE 0x110
37 #define QUP_MX_WRITE_CNT 0x150
38 #define QUP_MX_INPUT_CNT 0x200
39 #define QUP_MX_READ_CNT 0x208
40 #define QUP_IN_FIFO_BASE 0x218
41 #define QUP_I2C_CLK_CTL 0x400
42 #define QUP_I2C_STATUS 0x404
43 #define QUP_I2C_MASTER_GEN 0x408
45 /* QUP States and reset values */
46 #define QUP_RESET_STATE 0
47 #define QUP_RUN_STATE 1
48 #define QUP_PAUSE_STATE 3
49 #define QUP_STATE_MASK 3
51 #define QUP_STATE_VALID BIT(2)
52 #define QUP_I2C_MAST_GEN BIT(4)
53 #define QUP_I2C_FLUSH BIT(6)
55 #define QUP_OPERATIONAL_RESET 0x000ff0
56 #define QUP_I2C_STATUS_RESET 0xfffffc
58 /* QUP OPERATIONAL FLAGS */
59 #define QUP_I2C_NACK_FLAG BIT(3)
60 #define QUP_OUT_NOT_EMPTY BIT(4)
61 #define QUP_IN_NOT_EMPTY BIT(5)
62 #define QUP_OUT_FULL BIT(6)
63 #define QUP_OUT_SVC_FLAG BIT(8)
64 #define QUP_IN_SVC_FLAG BIT(9)
65 #define QUP_MX_OUTPUT_DONE BIT(10)
66 #define QUP_MX_INPUT_DONE BIT(11)
67 #define OUT_BLOCK_WRITE_REQ BIT(12)
68 #define IN_BLOCK_READ_REQ BIT(13)
70 /* I2C mini core related values */
71 #define QUP_NO_INPUT BIT(7)
72 #define QUP_CLOCK_AUTO_GATE BIT(13)
73 #define I2C_MINI_CORE (2 << 8)
75 #define I2C_N_VAL_V2 7
77 /* Most significant word offset in FIFO port */
78 #define QUP_MSW_SHIFT (I2C_N_VAL + 1)
80 /* Packing/Unpacking words in FIFOs, and IO modes */
81 #define QUP_OUTPUT_BLK_MODE (1 << 10)
82 #define QUP_OUTPUT_BAM_MODE (3 << 10)
83 #define QUP_INPUT_BLK_MODE (1 << 12)
84 #define QUP_INPUT_BAM_MODE (3 << 12)
85 #define QUP_BAM_MODE (QUP_OUTPUT_BAM_MODE | QUP_INPUT_BAM_MODE)
86 #define QUP_UNPACK_EN BIT(14)
87 #define QUP_PACK_EN BIT(15)
89 #define QUP_REPACK_EN (QUP_UNPACK_EN | QUP_PACK_EN)
90 #define QUP_V2_TAGS_EN 1
92 #define QUP_OUTPUT_BLOCK_SIZE(x)(((x) >> 0) & 0x03)
93 #define QUP_OUTPUT_FIFO_SIZE(x) (((x) >> 2) & 0x07)
94 #define QUP_INPUT_BLOCK_SIZE(x) (((x) >> 5) & 0x03)
95 #define QUP_INPUT_FIFO_SIZE(x) (((x) >> 7) & 0x07)
98 #define QUP_TAG_START (1 << 8)
99 #define QUP_TAG_DATA (2 << 8)
100 #define QUP_TAG_STOP (3 << 8)
101 #define QUP_TAG_REC (4 << 8)
102 #define QUP_BAM_INPUT_EOT 0x93
103 #define QUP_BAM_FLUSH_STOP 0x96
106 #define QUP_TAG_V2_START 0x81
107 #define QUP_TAG_V2_DATAWR 0x82
108 #define QUP_TAG_V2_DATAWR_STOP 0x83
109 #define QUP_TAG_V2_DATARD 0x85
110 #define QUP_TAG_V2_DATARD_NACK 0x86
111 #define QUP_TAG_V2_DATARD_STOP 0x87
113 /* Status, Error flags */
114 #define I2C_STATUS_WR_BUFFER_FULL BIT(0)
115 #define I2C_STATUS_BUS_ACTIVE BIT(8)
116 #define I2C_STATUS_ERROR_MASK 0x38000fc
117 #define QUP_STATUS_ERROR_FLAGS 0x7c
119 #define QUP_READ_LIMIT 256
121 #define RESET_BIT 0x0
123 #define QUP_I2C_MX_CONFIG_DURING_RUN BIT(31)
125 /* Maximum transfer length for single DMA descriptor */
126 #define MX_TX_RX_LEN SZ_64K
127 #define MX_BLOCKS (MX_TX_RX_LEN / QUP_READ_LIMIT)
128 /* Maximum transfer length for all DMA descriptors */
129 #define MX_DMA_TX_RX_LEN (2 * MX_TX_RX_LEN)
130 #define MX_DMA_BLOCKS (MX_DMA_TX_RX_LEN / QUP_READ_LIMIT)
133 * Minimum transfer timeout for i2c transfers in seconds. It will be added on
134 * the top of maximum transfer time calculated from i2c bus speed to compensate
139 /* I2C Frequency Modes */
140 #define I2C_STANDARD_FREQ 100000
141 #define I2C_FAST_MODE_FREQ 400000
142 #define I2C_FAST_MODE_PLUS_FREQ 1000000
144 /* Default values. Use these if FW query fails */
145 #define DEFAULT_CLK_FREQ I2C_STANDARD_FREQ
146 #define DEFAULT_SRC_CLK 20000000
149 * Max tags length (start, stop and maximum 2 bytes address) for each QUP
152 #define QUP_MAX_TAGS_LEN 4
153 /* Max data length for each DATARD tags */
154 #define RECV_MAX_DATA_LEN 254
155 /* TAG length for DATA READ in RX FIFO */
156 #define READ_RX_TAGS_LEN 2
158 static unsigned int scl_freq;
159 module_param_named(scl_freq, scl_freq, uint, 0444);
160 MODULE_PARM_DESC(scl_freq, "SCL frequency override");
163 * count: no of blocks
164 * pos: current block number
165 * tx_tag_len: tx tag length for current block
166 * rx_tag_len: rx tag length for current block
167 * data_len: remaining data length for current message
168 * cur_blk_len: data length for current block
169 * total_tx_len: total tx length including tag bytes for current QUP transfer
170 * total_rx_len: total rx length including tag bytes for current QUP transfer
171 * tx_fifo_data_pos: current byte number in TX FIFO word
172 * tx_fifo_free: number of free bytes in current QUP block write.
173 * rx_fifo_data_pos: current byte number in RX FIFO word
174 * fifo_available: number of available bytes in RX FIFO for current
176 * tx_fifo_data: QUP TX FIFO write works on word basis (4 bytes). New byte write
177 * to TX FIFO will be appended in this data and will be written to
178 * TX FIFO when all the 4 bytes are available.
179 * rx_fifo_data: QUP RX FIFO read works on word basis (4 bytes). This will
180 * contains the 4 bytes of RX data.
181 * cur_data: pointer to tell cur data position for current message
182 * cur_tx_tags: pointer to tell cur position in tags
183 * tx_tags_sent: all tx tag bytes have been written in FIFO word
184 * send_last_word: for tx FIFO, last word send is pending in current block
185 * rx_bytes_read: if all the bytes have been read from rx FIFO.
186 * rx_tags_fetched: all the rx tag bytes have been fetched from rx fifo word
187 * is_tx_blk_mode: whether tx uses block or FIFO mode in case of non BAM xfer.
188 * is_rx_blk_mode: whether rx uses block or FIFO mode in case of non BAM xfer.
189 * tags: contains tx tag bytes for current QUP transfer
191 struct qup_i2c_block {
200 int tx_fifo_data_pos;
202 int rx_fifo_data_pos;
210 bool rx_tags_fetched;
223 struct qup_i2c_tag tag;
224 struct dma_chan *dma;
225 struct scatterlist *sg;
235 struct i2c_adapter adap;
244 unsigned long one_byte_t;
245 unsigned long xfer_timeout;
246 struct qup_i2c_block blk;
249 /* Current posion in user message buffer */
251 /* I2C protocol errors */
253 /* QUP core errors */
256 /* To check if this is the last msg */
260 /* To configure when bus is in run state */
265 /* To check if the current transfer is using DMA */
267 unsigned int max_xfer_sg_len;
268 unsigned int tag_buf_pos;
269 /* The threshold length above which block mode will be used */
270 unsigned int blk_mode_threshold;
271 struct dma_pool *dpool;
272 struct qup_i2c_tag start_tag;
273 struct qup_i2c_bam brx;
274 struct qup_i2c_bam btx;
276 struct completion xfer;
277 /* function to write data in tx fifo */
278 void (*write_tx_fifo)(struct qup_i2c_dev *qup);
279 /* function to read data from rx fifo */
280 void (*read_rx_fifo)(struct qup_i2c_dev *qup);
281 /* function to write tags in tx fifo for i2c read transfer */
282 void (*write_rx_tags)(struct qup_i2c_dev *qup);
285 static irqreturn_t qup_i2c_interrupt(int irq, void *dev)
287 struct qup_i2c_dev *qup = dev;
288 struct qup_i2c_block *blk = &qup->blk;
293 bus_err = readl(qup->base + QUP_I2C_STATUS);
294 qup_err = readl(qup->base + QUP_ERROR_FLAGS);
295 opflags = readl(qup->base + QUP_OPERATIONAL);
298 /* Clear Error interrupt */
299 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
303 bus_err &= I2C_STATUS_ERROR_MASK;
304 qup_err &= QUP_STATUS_ERROR_FLAGS;
306 /* Clear the error bits in QUP_ERROR_FLAGS */
308 writel(qup_err, qup->base + QUP_ERROR_FLAGS);
310 /* Clear the error bits in QUP_I2C_STATUS */
312 writel(bus_err, qup->base + QUP_I2C_STATUS);
315 * Check for BAM mode and returns if already error has come for current
316 * transfer. In Error case, sometimes, QUP generates more than one
319 if (qup->use_dma && (qup->qup_err || qup->bus_err))
322 /* Reset the QUP State in case of error */
323 if (qup_err || bus_err) {
325 * Don’t reset the QUP state in case of BAM mode. The BAM
326 * flush operation needs to be scheduled in transfer function
327 * which will clear the remaining schedule descriptors in BAM
328 * HW FIFO and generates the BAM interrupt.
331 writel(QUP_RESET_STATE, qup->base + QUP_STATE);
335 if (opflags & QUP_OUT_SVC_FLAG) {
336 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
338 if (opflags & OUT_BLOCK_WRITE_REQ) {
339 blk->tx_fifo_free += qup->out_blk_sz;
340 if (qup->msg->flags & I2C_M_RD)
341 qup->write_rx_tags(qup);
343 qup->write_tx_fifo(qup);
347 if (opflags & QUP_IN_SVC_FLAG) {
348 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
350 if (!blk->is_rx_blk_mode) {
351 blk->fifo_available += qup->in_fifo_sz;
352 qup->read_rx_fifo(qup);
353 } else if (opflags & IN_BLOCK_READ_REQ) {
354 blk->fifo_available += qup->in_blk_sz;
355 qup->read_rx_fifo(qup);
359 if (qup->msg->flags & I2C_M_RD) {
360 if (!blk->rx_bytes_read)
364 * Ideally, QUP_MAX_OUTPUT_DONE_FLAG should be checked
365 * for FIFO mode also. But, QUP_MAX_OUTPUT_DONE_FLAG lags
366 * behind QUP_OUTPUT_SERVICE_FLAG sometimes. The only reason
367 * of interrupt for write message in FIFO mode is
368 * QUP_MAX_OUTPUT_DONE_FLAG condition.
370 if (blk->is_tx_blk_mode && !(opflags & QUP_MX_OUTPUT_DONE))
375 qup->qup_err = qup_err;
376 qup->bus_err = bus_err;
377 complete(&qup->xfer);
381 static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup,
382 u32 req_state, u32 req_mask)
388 * State transition takes 3 AHB clocks cycles + 3 I2C master clock
389 * cycles. So retry once after a 1uS delay.
392 state = readl(qup->base + QUP_STATE);
394 if (state & QUP_STATE_VALID &&
395 (state & req_mask) == req_state)
404 static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state)
406 return qup_i2c_poll_state_mask(qup, req_state, QUP_STATE_MASK);
409 static void qup_i2c_flush(struct qup_i2c_dev *qup)
411 u32 val = readl(qup->base + QUP_STATE);
413 val |= QUP_I2C_FLUSH;
414 writel(val, qup->base + QUP_STATE);
417 static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup)
419 return qup_i2c_poll_state_mask(qup, 0, 0);
422 static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup)
424 return qup_i2c_poll_state_mask(qup, QUP_I2C_MAST_GEN, QUP_I2C_MAST_GEN);
427 static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state)
429 if (qup_i2c_poll_state_valid(qup) != 0)
432 writel(state, qup->base + QUP_STATE);
434 if (qup_i2c_poll_state(qup, state) != 0)
439 /* Check if I2C bus returns to IDLE state */
440 static int qup_i2c_bus_active(struct qup_i2c_dev *qup, int len)
442 unsigned long timeout;
446 timeout = jiffies + len * 4;
448 status = readl(qup->base + QUP_I2C_STATUS);
449 if (!(status & I2C_STATUS_BUS_ACTIVE))
452 if (time_after(jiffies, timeout))
455 usleep_range(len, len * 2);
461 static void qup_i2c_write_tx_fifo_v1(struct qup_i2c_dev *qup)
463 struct qup_i2c_block *blk = &qup->blk;
464 struct i2c_msg *msg = qup->msg;
465 u32 addr = i2c_8bit_addr_from_msg(msg);
471 val = QUP_TAG_START | addr;
479 while (blk->tx_fifo_free && qup->pos < msg->len) {
480 if (qup->pos == msg->len - 1)
481 qup_tag = QUP_TAG_STOP;
483 qup_tag = QUP_TAG_DATA;
486 val |= (qup_tag | msg->buf[qup->pos]) << QUP_MSW_SHIFT;
488 val = qup_tag | msg->buf[qup->pos];
490 /* Write out the pair and the last odd value */
491 if (idx & 1 || qup->pos == msg->len - 1)
492 writel(val, qup->base + QUP_OUT_FIFO_BASE);
500 static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup,
504 qup->blk.data_len = msg->len;
505 qup->blk.count = DIV_ROUND_UP(msg->len, qup->blk_xfer_limit);
508 static int qup_i2c_get_data_len(struct qup_i2c_dev *qup)
512 if (qup->blk.data_len > qup->blk_xfer_limit)
513 data_len = qup->blk_xfer_limit;
515 data_len = qup->blk.data_len;
520 static bool qup_i2c_check_msg_len(struct i2c_msg *msg)
522 return ((msg->flags & I2C_M_RD) && (msg->flags & I2C_M_RECV_LEN));
525 static int qup_i2c_set_tags_smb(u16 addr, u8 *tags, struct qup_i2c_dev *qup,
530 if (qup->is_smbus_read) {
531 tags[len++] = QUP_TAG_V2_DATARD_STOP;
532 tags[len++] = qup_i2c_get_data_len(qup);
534 tags[len++] = QUP_TAG_V2_START;
535 tags[len++] = addr & 0xff;
537 if (msg->flags & I2C_M_TEN)
538 tags[len++] = addr >> 8;
540 tags[len++] = QUP_TAG_V2_DATARD;
541 /* Read 1 byte indicating the length of the SMBus message */
547 static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup,
550 u16 addr = i2c_8bit_addr_from_msg(msg);
554 int last = (qup->blk.pos == (qup->blk.count - 1)) && (qup->is_last);
556 /* Handle tags for SMBus block read */
557 if (qup_i2c_check_msg_len(msg))
558 return qup_i2c_set_tags_smb(addr, tags, qup, msg);
560 if (qup->blk.pos == 0) {
561 tags[len++] = QUP_TAG_V2_START;
562 tags[len++] = addr & 0xff;
564 if (msg->flags & I2C_M_TEN)
565 tags[len++] = addr >> 8;
568 /* Send _STOP commands for the last block */
570 if (msg->flags & I2C_M_RD)
571 tags[len++] = QUP_TAG_V2_DATARD_STOP;
573 tags[len++] = QUP_TAG_V2_DATAWR_STOP;
575 if (msg->flags & I2C_M_RD)
576 tags[len++] = qup->blk.pos == (qup->blk.count - 1) ?
577 QUP_TAG_V2_DATARD_NACK :
580 tags[len++] = QUP_TAG_V2_DATAWR;
583 data_len = qup_i2c_get_data_len(qup);
585 /* 0 implies 256 bytes */
586 if (data_len == QUP_READ_LIMIT)
589 tags[len++] = data_len;
595 static void qup_i2c_bam_cb(void *data)
597 struct qup_i2c_dev *qup = data;
599 complete(&qup->xfer);
602 static int qup_sg_set_buf(struct scatterlist *sg, void *buf,
603 unsigned int buflen, struct qup_i2c_dev *qup,
608 sg_set_buf(sg, buf, buflen);
609 ret = dma_map_sg(qup->dev, sg, 1, dir);
616 static void qup_i2c_rel_dma(struct qup_i2c_dev *qup)
619 dma_release_channel(qup->btx.dma);
621 dma_release_channel(qup->brx.dma);
626 static int qup_i2c_req_dma(struct qup_i2c_dev *qup)
631 qup->btx.dma = dma_request_slave_channel_reason(qup->dev, "tx");
632 if (IS_ERR(qup->btx.dma)) {
633 err = PTR_ERR(qup->btx.dma);
635 dev_err(qup->dev, "\n tx channel not available");
641 qup->brx.dma = dma_request_slave_channel_reason(qup->dev, "rx");
642 if (IS_ERR(qup->brx.dma)) {
643 dev_err(qup->dev, "\n rx channel not available");
644 err = PTR_ERR(qup->brx.dma);
646 qup_i2c_rel_dma(qup);
653 static int qup_i2c_bam_make_desc(struct qup_i2c_dev *qup, struct i2c_msg *msg)
655 int ret = 0, limit = QUP_READ_LIMIT;
656 u32 len = 0, blocks, rem;
657 u32 i = 0, tlen, tx_len = 0;
660 qup->blk_xfer_limit = QUP_READ_LIMIT;
661 qup_i2c_set_blk_data(qup, msg);
663 blocks = qup->blk.count;
664 rem = msg->len - (blocks - 1) * limit;
666 if (msg->flags & I2C_M_RD) {
667 while (qup->blk.pos < blocks) {
668 tlen = (i == (blocks - 1)) ? rem : limit;
669 tags = &qup->start_tag.start[qup->tag_buf_pos + len];
670 len += qup_i2c_set_tags(tags, qup, msg);
671 qup->blk.data_len -= tlen;
673 /* scratch buf to read the start and len tags */
674 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++],
675 &qup->brx.tag.start[0],
676 2, qup, DMA_FROM_DEVICE);
681 ret = qup_sg_set_buf(&qup->brx.sg[qup->brx.sg_cnt++],
682 &msg->buf[limit * i],
691 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
692 &qup->start_tag.start[qup->tag_buf_pos],
693 len, qup, DMA_TO_DEVICE);
697 qup->tag_buf_pos += len;
699 while (qup->blk.pos < blocks) {
700 tlen = (i == (blocks - 1)) ? rem : limit;
701 tags = &qup->start_tag.start[qup->tag_buf_pos + tx_len];
702 len = qup_i2c_set_tags(tags, qup, msg);
703 qup->blk.data_len -= tlen;
705 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
712 ret = qup_sg_set_buf(&qup->btx.sg[qup->btx.sg_cnt++],
713 &msg->buf[limit * i],
714 tlen, qup, DMA_TO_DEVICE);
721 qup->tag_buf_pos += tx_len;
727 static int qup_i2c_bam_schedule_desc(struct qup_i2c_dev *qup)
729 struct dma_async_tx_descriptor *txd, *rxd = NULL;
731 dma_cookie_t cookie_rx, cookie_tx;
733 u32 tx_cnt = qup->btx.sg_cnt, rx_cnt = qup->brx.sg_cnt;
735 /* schedule the EOT and FLUSH I2C tags */
738 qup->btx.tag.start[0] = QUP_BAM_INPUT_EOT;
741 /* scratch buf to read the BAM EOT FLUSH tags */
742 ret = qup_sg_set_buf(&qup->brx.sg[rx_cnt++],
743 &qup->brx.tag.start[0],
744 1, qup, DMA_FROM_DEVICE);
749 qup->btx.tag.start[len - 1] = QUP_BAM_FLUSH_STOP;
750 ret = qup_sg_set_buf(&qup->btx.sg[tx_cnt++], &qup->btx.tag.start[0],
751 len, qup, DMA_TO_DEVICE);
755 txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_cnt,
757 DMA_PREP_INTERRUPT | DMA_PREP_FENCE);
759 dev_err(qup->dev, "failed to get tx desc\n");
765 txd->callback = qup_i2c_bam_cb;
766 txd->callback_param = qup;
769 cookie_tx = dmaengine_submit(txd);
770 if (dma_submit_error(cookie_tx)) {
775 dma_async_issue_pending(qup->btx.dma);
778 rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg,
779 rx_cnt, DMA_DEV_TO_MEM,
782 dev_err(qup->dev, "failed to get rx desc\n");
785 /* abort TX descriptors */
786 dmaengine_terminate_all(qup->btx.dma);
790 rxd->callback = qup_i2c_bam_cb;
791 rxd->callback_param = qup;
792 cookie_rx = dmaengine_submit(rxd);
793 if (dma_submit_error(cookie_rx)) {
798 dma_async_issue_pending(qup->brx.dma);
801 if (!wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout)) {
802 dev_err(qup->dev, "normal trans timed out\n");
806 if (ret || qup->bus_err || qup->qup_err) {
807 reinit_completion(&qup->xfer);
809 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
811 dev_err(qup->dev, "change to run state timed out");
817 /* wait for remaining interrupts to occur */
818 if (!wait_for_completion_timeout(&qup->xfer, HZ))
819 dev_err(qup->dev, "flush timed out\n");
821 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO;
825 dma_unmap_sg(qup->dev, qup->btx.sg, tx_cnt, DMA_TO_DEVICE);
828 dma_unmap_sg(qup->dev, qup->brx.sg, rx_cnt,
834 static void qup_i2c_bam_clear_tag_buffers(struct qup_i2c_dev *qup)
838 qup->tag_buf_pos = 0;
841 static int qup_i2c_bam_xfer(struct i2c_adapter *adap, struct i2c_msg *msg,
844 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
848 enable_irq(qup->irq);
849 ret = qup_i2c_req_dma(qup);
854 writel(0, qup->base + QUP_MX_INPUT_CNT);
855 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
858 writel(QUP_REPACK_EN | QUP_BAM_MODE, qup->base + QUP_IO_MODE);
861 writel((0x3 << 8), qup->base + QUP_OPERATIONAL_MASK);
864 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
868 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
869 qup_i2c_bam_clear_tag_buffers(qup);
871 for (idx = 0; idx < num; idx++) {
872 qup->msg = msg + idx;
873 qup->is_last = idx == (num - 1);
875 ret = qup_i2c_bam_make_desc(qup, qup->msg);
880 * Make DMA descriptor and schedule the BAM transfer if its
881 * already crossed the maximum length. Since the memory for all
882 * tags buffers have been taken for 2 maximum possible
883 * transfers length so it will never cross the buffer actual
886 if (qup->btx.sg_cnt > qup->max_xfer_sg_len ||
887 qup->brx.sg_cnt > qup->max_xfer_sg_len ||
889 ret = qup_i2c_bam_schedule_desc(qup);
893 qup_i2c_bam_clear_tag_buffers(qup);
898 disable_irq(qup->irq);
904 static int qup_i2c_wait_for_complete(struct qup_i2c_dev *qup,
910 left = wait_for_completion_timeout(&qup->xfer, qup->xfer_timeout);
912 writel(1, qup->base + QUP_SW_RESET);
916 if (qup->bus_err || qup->qup_err)
917 ret = (qup->bus_err & QUP_I2C_NACK_FLAG) ? -ENXIO : -EIO;
922 static void qup_i2c_read_rx_fifo_v1(struct qup_i2c_dev *qup)
924 struct qup_i2c_block *blk = &qup->blk;
925 struct i2c_msg *msg = qup->msg;
929 while (blk->fifo_available && qup->pos < msg->len) {
930 if ((idx & 1) == 0) {
931 /* Reading 2 words at time */
932 val = readl(qup->base + QUP_IN_FIFO_BASE);
933 msg->buf[qup->pos++] = val & 0xFF;
935 msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT;
938 blk->fifo_available--;
941 if (qup->pos == msg->len)
942 blk->rx_bytes_read = true;
945 static void qup_i2c_write_rx_tags_v1(struct qup_i2c_dev *qup)
947 struct i2c_msg *msg = qup->msg;
950 addr = i2c_8bit_addr_from_msg(msg);
952 /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */
953 len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len;
955 val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr;
956 writel(val, qup->base + QUP_OUT_FIFO_BASE);
959 static void qup_i2c_conf_v1(struct qup_i2c_dev *qup)
961 struct qup_i2c_block *blk = &qup->blk;
962 u32 qup_config = I2C_MINI_CORE | I2C_N_VAL;
963 u32 io_mode = QUP_REPACK_EN;
965 blk->is_tx_blk_mode =
966 blk->total_tx_len > qup->out_fifo_sz ? true : false;
967 blk->is_rx_blk_mode =
968 blk->total_rx_len > qup->in_fifo_sz ? true : false;
970 if (blk->is_tx_blk_mode) {
971 io_mode |= QUP_OUTPUT_BLK_MODE;
972 writel(0, qup->base + QUP_MX_WRITE_CNT);
973 writel(blk->total_tx_len, qup->base + QUP_MX_OUTPUT_CNT);
975 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
976 writel(blk->total_tx_len, qup->base + QUP_MX_WRITE_CNT);
979 if (blk->total_rx_len) {
980 if (blk->is_rx_blk_mode) {
981 io_mode |= QUP_INPUT_BLK_MODE;
982 writel(0, qup->base + QUP_MX_READ_CNT);
983 writel(blk->total_rx_len, qup->base + QUP_MX_INPUT_CNT);
985 writel(0, qup->base + QUP_MX_INPUT_CNT);
986 writel(blk->total_rx_len, qup->base + QUP_MX_READ_CNT);
989 qup_config |= QUP_NO_INPUT;
992 writel(qup_config, qup->base + QUP_CONFIG);
993 writel(io_mode, qup->base + QUP_IO_MODE);
996 static void qup_i2c_clear_blk_v1(struct qup_i2c_block *blk)
998 blk->tx_fifo_free = 0;
999 blk->fifo_available = 0;
1000 blk->rx_bytes_read = false;
1003 static int qup_i2c_conf_xfer_v1(struct qup_i2c_dev *qup, bool is_rx)
1005 struct qup_i2c_block *blk = &qup->blk;
1008 qup_i2c_clear_blk_v1(blk);
1009 qup_i2c_conf_v1(qup);
1010 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1014 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1016 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1020 reinit_completion(&qup->xfer);
1021 enable_irq(qup->irq);
1022 if (!blk->is_tx_blk_mode) {
1023 blk->tx_fifo_free = qup->out_fifo_sz;
1026 qup_i2c_write_rx_tags_v1(qup);
1028 qup_i2c_write_tx_fifo_v1(qup);
1031 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1035 ret = qup_i2c_wait_for_complete(qup, qup->msg);
1039 ret = qup_i2c_bus_active(qup, ONE_BYTE);
1042 disable_irq(qup->irq);
1046 static int qup_i2c_write_one(struct qup_i2c_dev *qup)
1048 struct i2c_msg *msg = qup->msg;
1049 struct qup_i2c_block *blk = &qup->blk;
1052 blk->total_tx_len = msg->len + 1;
1053 blk->total_rx_len = 0;
1055 return qup_i2c_conf_xfer_v1(qup, false);
1058 static int qup_i2c_read_one(struct qup_i2c_dev *qup)
1060 struct qup_i2c_block *blk = &qup->blk;
1063 blk->total_tx_len = 2;
1064 blk->total_rx_len = qup->msg->len;
1066 return qup_i2c_conf_xfer_v1(qup, true);
1069 static int qup_i2c_xfer(struct i2c_adapter *adap,
1070 struct i2c_msg msgs[],
1073 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
1076 ret = pm_runtime_get_sync(qup->dev);
1083 writel(1, qup->base + QUP_SW_RESET);
1084 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1088 /* Configure QUP as I2C mini core */
1089 writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG);
1091 for (idx = 0; idx < num; idx++) {
1092 if (qup_i2c_poll_state_i2c_master(qup)) {
1097 if (qup_i2c_check_msg_len(&msgs[idx])) {
1102 qup->msg = &msgs[idx];
1103 if (msgs[idx].flags & I2C_M_RD)
1104 ret = qup_i2c_read_one(qup);
1106 ret = qup_i2c_write_one(qup);
1111 ret = qup_i2c_change_state(qup, QUP_RESET_STATE);
1120 pm_runtime_mark_last_busy(qup->dev);
1121 pm_runtime_put_autosuspend(qup->dev);
1127 * Configure registers related with reconfiguration during run and call it
1128 * before each i2c sub transfer.
1130 static void qup_i2c_conf_count_v2(struct qup_i2c_dev *qup)
1132 struct qup_i2c_block *blk = &qup->blk;
1133 u32 qup_config = I2C_MINI_CORE | I2C_N_VAL_V2;
1135 if (blk->is_tx_blk_mode)
1136 writel(qup->config_run | blk->total_tx_len,
1137 qup->base + QUP_MX_OUTPUT_CNT);
1139 writel(qup->config_run | blk->total_tx_len,
1140 qup->base + QUP_MX_WRITE_CNT);
1142 if (blk->total_rx_len) {
1143 if (blk->is_rx_blk_mode)
1144 writel(qup->config_run | blk->total_rx_len,
1145 qup->base + QUP_MX_INPUT_CNT);
1147 writel(qup->config_run | blk->total_rx_len,
1148 qup->base + QUP_MX_READ_CNT);
1150 qup_config |= QUP_NO_INPUT;
1153 writel(qup_config, qup->base + QUP_CONFIG);
1157 * Configure registers related with transfer mode (FIFO/Block)
1158 * before starting of i2c transfer. It will be called only once in
1161 static void qup_i2c_conf_mode_v2(struct qup_i2c_dev *qup)
1163 struct qup_i2c_block *blk = &qup->blk;
1164 u32 io_mode = QUP_REPACK_EN;
1166 if (blk->is_tx_blk_mode) {
1167 io_mode |= QUP_OUTPUT_BLK_MODE;
1168 writel(0, qup->base + QUP_MX_WRITE_CNT);
1170 writel(0, qup->base + QUP_MX_OUTPUT_CNT);
1173 if (blk->is_rx_blk_mode) {
1174 io_mode |= QUP_INPUT_BLK_MODE;
1175 writel(0, qup->base + QUP_MX_READ_CNT);
1177 writel(0, qup->base + QUP_MX_INPUT_CNT);
1180 writel(io_mode, qup->base + QUP_IO_MODE);
1183 /* Clear required variables before starting of any QUP v2 sub transfer. */
1184 static void qup_i2c_clear_blk_v2(struct qup_i2c_block *blk)
1186 blk->send_last_word = false;
1187 blk->tx_tags_sent = false;
1188 blk->tx_fifo_data = 0;
1189 blk->tx_fifo_data_pos = 0;
1190 blk->tx_fifo_free = 0;
1192 blk->rx_tags_fetched = false;
1193 blk->rx_bytes_read = false;
1194 blk->rx_fifo_data = 0;
1195 blk->rx_fifo_data_pos = 0;
1196 blk->fifo_available = 0;
1199 /* Receive data from RX FIFO for read message in QUP v2 i2c transfer. */
1200 static void qup_i2c_recv_data(struct qup_i2c_dev *qup)
1202 struct qup_i2c_block *blk = &qup->blk;
1205 for (j = blk->rx_fifo_data_pos;
1206 blk->cur_blk_len && blk->fifo_available;
1207 blk->cur_blk_len--, blk->fifo_available--) {
1209 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE);
1211 *(blk->cur_data++) = blk->rx_fifo_data;
1212 blk->rx_fifo_data >>= 8;
1220 blk->rx_fifo_data_pos = j;
1223 /* Receive tags for read message in QUP v2 i2c transfer. */
1224 static void qup_i2c_recv_tags(struct qup_i2c_dev *qup)
1226 struct qup_i2c_block *blk = &qup->blk;
1228 blk->rx_fifo_data = readl(qup->base + QUP_IN_FIFO_BASE);
1229 blk->rx_fifo_data >>= blk->rx_tag_len * 8;
1230 blk->rx_fifo_data_pos = blk->rx_tag_len;
1231 blk->fifo_available -= blk->rx_tag_len;
1235 * Read the data and tags from RX FIFO. Since in read case, the tags will be
1236 * preceded by received data bytes so
1237 * 1. Check if rx_tags_fetched is false i.e. the start of QUP block so receive
1238 * all tag bytes and discard that.
1239 * 2. Read the data from RX FIFO. When all the data bytes have been read then
1240 * set rx_bytes_read to true.
1242 static void qup_i2c_read_rx_fifo_v2(struct qup_i2c_dev *qup)
1244 struct qup_i2c_block *blk = &qup->blk;
1246 if (!blk->rx_tags_fetched) {
1247 qup_i2c_recv_tags(qup);
1248 blk->rx_tags_fetched = true;
1251 qup_i2c_recv_data(qup);
1252 if (!blk->cur_blk_len)
1253 blk->rx_bytes_read = true;
1257 * Write bytes in TX FIFO for write message in QUP v2 i2c transfer. QUP TX FIFO
1258 * write works on word basis (4 bytes). Append new data byte write for TX FIFO
1259 * in tx_fifo_data and write to TX FIFO when all the 4 bytes are present.
1262 qup_i2c_write_blk_data(struct qup_i2c_dev *qup, u8 **data, unsigned int *len)
1264 struct qup_i2c_block *blk = &qup->blk;
1267 for (j = blk->tx_fifo_data_pos; *len && blk->tx_fifo_free;
1268 (*len)--, blk->tx_fifo_free--) {
1269 blk->tx_fifo_data |= *(*data)++ << (j * 8);
1271 writel(blk->tx_fifo_data,
1272 qup->base + QUP_OUT_FIFO_BASE);
1273 blk->tx_fifo_data = 0x0;
1280 blk->tx_fifo_data_pos = j;
1283 /* Transfer tags for read message in QUP v2 i2c transfer. */
1284 static void qup_i2c_write_rx_tags_v2(struct qup_i2c_dev *qup)
1286 struct qup_i2c_block *blk = &qup->blk;
1288 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags, &blk->tx_tag_len);
1289 if (blk->tx_fifo_data_pos)
1290 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE);
1294 * Write the data and tags in TX FIFO. Since in write case, both tags and data
1295 * need to be written and QUP write tags can have maximum 256 data length, so
1297 * 1. Check if tx_tags_sent is false i.e. the start of QUP block so write the
1298 * tags to TX FIFO and set tx_tags_sent to true.
1299 * 2. Check if send_last_word is true. It will be set when last few data bytes
1300 * (less than 4 bytes) are reamining to be written in FIFO because of no FIFO
1301 * space. All this data bytes are available in tx_fifo_data so write this
1303 * 3. Write the data to TX FIFO and check for cur_blk_len. If it is non zero
1304 * then more data is pending otherwise following 3 cases can be possible
1305 * a. if tx_fifo_data_pos is zero i.e. all the data bytes in this block
1306 * have been written in TX FIFO so nothing else is required.
1307 * b. tx_fifo_free is non zero i.e tx FIFO is free so copy the remaining data
1308 * from tx_fifo_data to tx FIFO. Since, qup_i2c_write_blk_data do write
1309 * in 4 bytes and FIFO space is in multiple of 4 bytes so tx_fifo_free
1310 * will be always greater than or equal to 4 bytes.
1311 * c. tx_fifo_free is zero. In this case, last few bytes (less than 4
1312 * bytes) are copied to tx_fifo_data but couldn't be sent because of
1313 * FIFO full so make send_last_word true.
1315 static void qup_i2c_write_tx_fifo_v2(struct qup_i2c_dev *qup)
1317 struct qup_i2c_block *blk = &qup->blk;
1319 if (!blk->tx_tags_sent) {
1320 qup_i2c_write_blk_data(qup, &blk->cur_tx_tags,
1322 blk->tx_tags_sent = true;
1325 if (blk->send_last_word)
1326 goto send_last_word;
1328 qup_i2c_write_blk_data(qup, &blk->cur_data, &blk->cur_blk_len);
1329 if (!blk->cur_blk_len) {
1330 if (!blk->tx_fifo_data_pos)
1333 if (blk->tx_fifo_free)
1334 goto send_last_word;
1336 blk->send_last_word = true;
1342 writel(blk->tx_fifo_data, qup->base + QUP_OUT_FIFO_BASE);
1346 * Main transfer function which read or write i2c data.
1347 * The QUP v2 supports reconfiguration during run in which multiple i2c sub
1348 * transfers can be scheduled.
1351 qup_i2c_conf_xfer_v2(struct qup_i2c_dev *qup, bool is_rx, bool is_first,
1352 bool change_pause_state)
1354 struct qup_i2c_block *blk = &qup->blk;
1355 struct i2c_msg *msg = qup->msg;
1359 * Check if its SMBus Block read for which the top level read will be
1360 * done into 2 QUP reads. One with message length 1 while other one is
1361 * with actual length.
1363 if (qup_i2c_check_msg_len(msg)) {
1364 if (qup->is_smbus_read) {
1366 * If the message length is already read in
1367 * the first byte of the buffer, account for
1368 * that by setting the offset
1373 change_pause_state = false;
1377 qup->config_run = is_first ? 0 : QUP_I2C_MX_CONFIG_DURING_RUN;
1379 qup_i2c_clear_blk_v2(blk);
1380 qup_i2c_conf_count_v2(qup);
1382 /* If it is first sub transfer, then configure i2c bus clocks */
1384 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1388 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
1390 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1395 reinit_completion(&qup->xfer);
1396 enable_irq(qup->irq);
1398 * In FIFO mode, tx FIFO can be written directly while in block mode the
1399 * it will be written after getting OUT_BLOCK_WRITE_REQ interrupt
1401 if (!blk->is_tx_blk_mode) {
1402 blk->tx_fifo_free = qup->out_fifo_sz;
1405 qup_i2c_write_rx_tags_v2(qup);
1407 qup_i2c_write_tx_fifo_v2(qup);
1410 ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
1414 ret = qup_i2c_wait_for_complete(qup, msg);
1418 /* Move to pause state for all the transfers, except last one */
1419 if (change_pause_state) {
1420 ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
1426 disable_irq(qup->irq);
1431 * Transfer one read/write message in i2c transfer. It splits the message into
1432 * multiple of blk_xfer_limit data length blocks and schedule each
1433 * QUP block individually.
1435 static int qup_i2c_xfer_v2_msg(struct qup_i2c_dev *qup, int msg_id, bool is_rx)
1438 unsigned int data_len, i;
1439 struct i2c_msg *msg = qup->msg;
1440 struct qup_i2c_block *blk = &qup->blk;
1441 u8 *msg_buf = msg->buf;
1443 qup->blk_xfer_limit = is_rx ? RECV_MAX_DATA_LEN : QUP_READ_LIMIT;
1444 qup_i2c_set_blk_data(qup, msg);
1446 for (i = 0; i < blk->count; i++) {
1447 data_len = qup_i2c_get_data_len(qup);
1449 blk->cur_tx_tags = blk->tags;
1450 blk->cur_blk_len = data_len;
1452 qup_i2c_set_tags(blk->cur_tx_tags, qup, qup->msg);
1454 blk->cur_data = msg_buf;
1457 blk->total_tx_len = blk->tx_tag_len;
1458 blk->rx_tag_len = 2;
1459 blk->total_rx_len = blk->rx_tag_len + data_len;
1461 blk->total_tx_len = blk->tx_tag_len + data_len;
1462 blk->total_rx_len = 0;
1465 ret = qup_i2c_conf_xfer_v2(qup, is_rx, !msg_id && !i,
1466 !qup->is_last || i < blk->count - 1);
1470 /* Handle SMBus block read length */
1471 if (qup_i2c_check_msg_len(msg) && msg->len == 1 &&
1472 !qup->is_smbus_read) {
1473 if (msg->buf[0] > I2C_SMBUS_BLOCK_MAX)
1476 msg->len = msg->buf[0];
1477 qup->is_smbus_read = true;
1478 ret = qup_i2c_xfer_v2_msg(qup, msg_id, true);
1479 qup->is_smbus_read = false;
1486 msg_buf += data_len;
1487 blk->data_len -= qup->blk_xfer_limit;
1494 * QUP v2 supports 3 modes
1495 * Programmed IO using FIFO mode : Less than FIFO size
1496 * Programmed IO using Block mode : Greater than FIFO size
1497 * DMA using BAM : Appropriate for any transaction size but the address should
1500 * This function determines the mode which will be used for this transfer. An
1501 * i2c transfer contains multiple message. Following are the rules to determine
1503 * 1. Determine complete length, maximum tx and rx length for complete transfer.
1504 * 2. If complete transfer length is greater than fifo size then use the DMA
1506 * 3. In FIFO or block mode, tx and rx can operate in different mode so check
1507 * for maximum tx and rx length to determine mode.
1510 qup_i2c_determine_mode_v2(struct qup_i2c_dev *qup,
1511 struct i2c_msg msgs[], int num)
1514 bool no_dma = false;
1515 unsigned int max_tx_len = 0, max_rx_len = 0, total_len = 0;
1517 /* All i2c_msgs should be transferred using either dma or cpu */
1518 for (idx = 0; idx < num; idx++) {
1519 if (msgs[idx].flags & I2C_M_RD)
1520 max_rx_len = max_t(unsigned int, max_rx_len,
1523 max_tx_len = max_t(unsigned int, max_tx_len,
1526 if (is_vmalloc_addr(msgs[idx].buf))
1529 total_len += msgs[idx].len;
1532 if (!no_dma && qup->is_dma &&
1533 (total_len > qup->out_fifo_sz || total_len > qup->in_fifo_sz)) {
1534 qup->use_dma = true;
1536 qup->blk.is_tx_blk_mode = max_tx_len > qup->out_fifo_sz -
1537 QUP_MAX_TAGS_LEN ? true : false;
1538 qup->blk.is_rx_blk_mode = max_rx_len > qup->in_fifo_sz -
1539 READ_RX_TAGS_LEN ? true : false;
1545 static int qup_i2c_xfer_v2(struct i2c_adapter *adap,
1546 struct i2c_msg msgs[],
1549 struct qup_i2c_dev *qup = i2c_get_adapdata(adap);
1555 ret = pm_runtime_get_sync(qup->dev);
1559 ret = qup_i2c_determine_mode_v2(qup, msgs, num);
1563 writel(1, qup->base + QUP_SW_RESET);
1564 ret = qup_i2c_poll_state(qup, QUP_RESET_STATE);
1568 /* Configure QUP as I2C mini core */
1569 writel(I2C_MINI_CORE | I2C_N_VAL_V2, qup->base + QUP_CONFIG);
1570 writel(QUP_V2_TAGS_EN, qup->base + QUP_I2C_MASTER_GEN);
1572 if (qup_i2c_poll_state_i2c_master(qup)) {
1578 reinit_completion(&qup->xfer);
1579 ret = qup_i2c_bam_xfer(adap, &msgs[0], num);
1580 qup->use_dma = false;
1582 qup_i2c_conf_mode_v2(qup);
1584 for (idx = 0; idx < num; idx++) {
1585 qup->msg = &msgs[idx];
1586 qup->is_last = idx == (num - 1);
1588 ret = qup_i2c_xfer_v2_msg(qup, idx,
1589 !!(msgs[idx].flags & I2C_M_RD));
1597 ret = qup_i2c_bus_active(qup, ONE_BYTE);
1600 qup_i2c_change_state(qup, QUP_RESET_STATE);
1605 pm_runtime_mark_last_busy(qup->dev);
1606 pm_runtime_put_autosuspend(qup->dev);
1611 static u32 qup_i2c_func(struct i2c_adapter *adap)
1613 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
1616 static const struct i2c_algorithm qup_i2c_algo = {
1617 .master_xfer = qup_i2c_xfer,
1618 .functionality = qup_i2c_func,
1621 static const struct i2c_algorithm qup_i2c_algo_v2 = {
1622 .master_xfer = qup_i2c_xfer_v2,
1623 .functionality = qup_i2c_func,
1627 * The QUP block will issue a NACK and STOP on the bus when reaching
1628 * the end of the read, the length of the read is specified as one byte
1629 * which limits the possible read to 256 (QUP_READ_LIMIT) bytes.
1631 static const struct i2c_adapter_quirks qup_i2c_quirks = {
1632 .flags = I2C_AQ_NO_ZERO_LEN,
1633 .max_read_len = QUP_READ_LIMIT,
1636 static const struct i2c_adapter_quirks qup_i2c_quirks_v2 = {
1637 .flags = I2C_AQ_NO_ZERO_LEN,
1640 static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup)
1642 clk_prepare_enable(qup->clk);
1643 clk_prepare_enable(qup->pclk);
1646 static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup)
1650 qup_i2c_change_state(qup, QUP_RESET_STATE);
1651 clk_disable_unprepare(qup->clk);
1652 config = readl(qup->base + QUP_CONFIG);
1653 config |= QUP_CLOCK_AUTO_GATE;
1654 writel(config, qup->base + QUP_CONFIG);
1655 clk_disable_unprepare(qup->pclk);
1658 static const struct acpi_device_id qup_i2c_acpi_match[] = {
1662 MODULE_DEVICE_TABLE(acpi, qup_i2c_acpi_match);
1664 static int qup_i2c_probe(struct platform_device *pdev)
1666 static const int blk_sizes[] = {4, 16, 32};
1667 struct qup_i2c_dev *qup;
1668 unsigned long one_bit_t;
1669 struct resource *res;
1670 u32 io_mode, hw_ver, size;
1671 int ret, fs_div, hs_div;
1672 u32 src_clk_freq = DEFAULT_SRC_CLK;
1673 u32 clk_freq = DEFAULT_CLK_FREQ;
1677 qup = devm_kzalloc(&pdev->dev, sizeof(*qup), GFP_KERNEL);
1681 qup->dev = &pdev->dev;
1682 init_completion(&qup->xfer);
1683 platform_set_drvdata(pdev, qup);
1686 dev_notice(qup->dev, "Using override frequency of %u\n", scl_freq);
1687 clk_freq = scl_freq;
1689 ret = device_property_read_u32(qup->dev, "clock-frequency", &clk_freq);
1691 dev_notice(qup->dev, "using default clock-frequency %d",
1696 if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) {
1697 qup->adap.algo = &qup_i2c_algo;
1698 qup->adap.quirks = &qup_i2c_quirks;
1701 qup->adap.algo = &qup_i2c_algo_v2;
1702 qup->adap.quirks = &qup_i2c_quirks_v2;
1704 if (acpi_match_device(qup_i2c_acpi_match, qup->dev))
1707 ret = qup_i2c_req_dma(qup);
1709 if (ret == -EPROBE_DEFER)
1714 qup->max_xfer_sg_len = (MX_BLOCKS << 1);
1715 blocks = (MX_DMA_BLOCKS << 1) + 1;
1716 qup->btx.sg = devm_kcalloc(&pdev->dev,
1717 blocks, sizeof(*qup->btx.sg),
1723 sg_init_table(qup->btx.sg, blocks);
1725 qup->brx.sg = devm_kcalloc(&pdev->dev,
1726 blocks, sizeof(*qup->brx.sg),
1732 sg_init_table(qup->brx.sg, blocks);
1734 /* 2 tag bytes for each block + 5 for start, stop tags */
1735 size = blocks * 2 + 5;
1737 qup->start_tag.start = devm_kzalloc(&pdev->dev,
1739 if (!qup->start_tag.start) {
1744 qup->brx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);
1745 if (!qup->brx.tag.start) {
1750 qup->btx.tag.start = devm_kzalloc(&pdev->dev, 2, GFP_KERNEL);
1751 if (!qup->btx.tag.start) {
1759 /* We support frequencies up to FAST Mode Plus (1MHz) */
1760 if (!clk_freq || clk_freq > I2C_FAST_MODE_PLUS_FREQ) {
1761 dev_err(qup->dev, "clock frequency not supported %d\n",
1766 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1767 qup->base = devm_ioremap_resource(qup->dev, res);
1768 if (IS_ERR(qup->base))
1769 return PTR_ERR(qup->base);
1771 qup->irq = platform_get_irq(pdev, 0);
1773 dev_err(qup->dev, "No IRQ defined\n");
1777 if (has_acpi_companion(qup->dev)) {
1778 ret = device_property_read_u32(qup->dev,
1779 "src-clock-hz", &src_clk_freq);
1781 dev_notice(qup->dev, "using default src-clock-hz %d",
1784 ACPI_COMPANION_SET(&qup->adap.dev, ACPI_COMPANION(qup->dev));
1786 qup->clk = devm_clk_get(qup->dev, "core");
1787 if (IS_ERR(qup->clk)) {
1788 dev_err(qup->dev, "Could not get core clock\n");
1789 return PTR_ERR(qup->clk);
1792 qup->pclk = devm_clk_get(qup->dev, "iface");
1793 if (IS_ERR(qup->pclk)) {
1794 dev_err(qup->dev, "Could not get iface clock\n");
1795 return PTR_ERR(qup->pclk);
1797 qup_i2c_enable_clocks(qup);
1798 src_clk_freq = clk_get_rate(qup->clk);
1802 * Bootloaders might leave a pending interrupt on certain QUP's,
1803 * so we reset the core before registering for interrupts.
1805 writel(1, qup->base + QUP_SW_RESET);
1806 ret = qup_i2c_poll_state_valid(qup);
1810 ret = devm_request_irq(qup->dev, qup->irq, qup_i2c_interrupt,
1811 IRQF_TRIGGER_HIGH, "i2c_qup", qup);
1813 dev_err(qup->dev, "Request %d IRQ failed\n", qup->irq);
1816 disable_irq(qup->irq);
1818 hw_ver = readl(qup->base + QUP_HW_VERSION);
1819 dev_dbg(qup->dev, "Revision %x\n", hw_ver);
1821 io_mode = readl(qup->base + QUP_IO_MODE);
1824 * The block/fifo size w.r.t. 'actual data' is 1/2 due to 'tag'
1825 * associated with each byte written/received
1827 size = QUP_OUTPUT_BLOCK_SIZE(io_mode);
1828 if (size >= ARRAY_SIZE(blk_sizes)) {
1832 qup->out_blk_sz = blk_sizes[size];
1834 size = QUP_INPUT_BLOCK_SIZE(io_mode);
1835 if (size >= ARRAY_SIZE(blk_sizes)) {
1839 qup->in_blk_sz = blk_sizes[size];
1843 * in QUP v1, QUP_CONFIG uses N as 15 i.e 16 bits constitutes a
1844 * single transfer but the block size is in bytes so divide the
1845 * in_blk_sz and out_blk_sz by 2
1847 qup->in_blk_sz /= 2;
1848 qup->out_blk_sz /= 2;
1849 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v1;
1850 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v1;
1851 qup->write_rx_tags = qup_i2c_write_rx_tags_v1;
1853 qup->write_tx_fifo = qup_i2c_write_tx_fifo_v2;
1854 qup->read_rx_fifo = qup_i2c_read_rx_fifo_v2;
1855 qup->write_rx_tags = qup_i2c_write_rx_tags_v2;
1858 size = QUP_OUTPUT_FIFO_SIZE(io_mode);
1859 qup->out_fifo_sz = qup->out_blk_sz * (2 << size);
1861 size = QUP_INPUT_FIFO_SIZE(io_mode);
1862 qup->in_fifo_sz = qup->in_blk_sz * (2 << size);
1865 if (clk_freq <= I2C_STANDARD_FREQ) {
1866 fs_div = ((src_clk_freq / clk_freq) / 2) - 3;
1867 qup->clk_ctl = (hs_div << 8) | (fs_div & 0xff);
1869 /* 33%/66% duty cycle */
1870 fs_div = ((src_clk_freq / clk_freq) - 6) * 2 / 3;
1871 qup->clk_ctl = ((fs_div / 2) << 16) | (hs_div << 8) | (fs_div & 0xff);
1875 * Time it takes for a byte to be clocked out on the bus.
1876 * Each byte takes 9 clock cycles (8 bits + 1 ack).
1878 one_bit_t = (USEC_PER_SEC / clk_freq) + 1;
1879 qup->one_byte_t = one_bit_t * 9;
1880 qup->xfer_timeout = TOUT_MIN * HZ +
1881 usecs_to_jiffies(MX_DMA_TX_RX_LEN * qup->one_byte_t);
1883 dev_dbg(qup->dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
1884 qup->in_blk_sz, qup->in_fifo_sz,
1885 qup->out_blk_sz, qup->out_fifo_sz);
1887 i2c_set_adapdata(&qup->adap, qup);
1888 qup->adap.dev.parent = qup->dev;
1889 qup->adap.dev.of_node = pdev->dev.of_node;
1890 qup->is_last = true;
1892 strlcpy(qup->adap.name, "QUP I2C adapter", sizeof(qup->adap.name));
1894 pm_runtime_set_autosuspend_delay(qup->dev, MSEC_PER_SEC);
1895 pm_runtime_use_autosuspend(qup->dev);
1896 pm_runtime_set_active(qup->dev);
1897 pm_runtime_enable(qup->dev);
1899 ret = i2c_add_adapter(&qup->adap);
1906 pm_runtime_disable(qup->dev);
1907 pm_runtime_set_suspended(qup->dev);
1909 qup_i2c_disable_clocks(qup);
1912 dma_release_channel(qup->btx.dma);
1914 dma_release_channel(qup->brx.dma);
1918 static int qup_i2c_remove(struct platform_device *pdev)
1920 struct qup_i2c_dev *qup = platform_get_drvdata(pdev);
1923 dma_release_channel(qup->btx.dma);
1924 dma_release_channel(qup->brx.dma);
1927 disable_irq(qup->irq);
1928 qup_i2c_disable_clocks(qup);
1929 i2c_del_adapter(&qup->adap);
1930 pm_runtime_disable(qup->dev);
1931 pm_runtime_set_suspended(qup->dev);
1936 static int qup_i2c_pm_suspend_runtime(struct device *device)
1938 struct qup_i2c_dev *qup = dev_get_drvdata(device);
1940 dev_dbg(device, "pm_runtime: suspending...\n");
1941 qup_i2c_disable_clocks(qup);
1945 static int qup_i2c_pm_resume_runtime(struct device *device)
1947 struct qup_i2c_dev *qup = dev_get_drvdata(device);
1949 dev_dbg(device, "pm_runtime: resuming...\n");
1950 qup_i2c_enable_clocks(qup);
1955 #ifdef CONFIG_PM_SLEEP
1956 static int qup_i2c_suspend(struct device *device)
1958 if (!pm_runtime_suspended(device))
1959 return qup_i2c_pm_suspend_runtime(device);
1963 static int qup_i2c_resume(struct device *device)
1965 qup_i2c_pm_resume_runtime(device);
1966 pm_runtime_mark_last_busy(device);
1967 pm_request_autosuspend(device);
1972 static const struct dev_pm_ops qup_i2c_qup_pm_ops = {
1973 SET_SYSTEM_SLEEP_PM_OPS(
1977 qup_i2c_pm_suspend_runtime,
1978 qup_i2c_pm_resume_runtime,
1982 static const struct of_device_id qup_i2c_dt_match[] = {
1983 { .compatible = "qcom,i2c-qup-v1.1.1" },
1984 { .compatible = "qcom,i2c-qup-v2.1.1" },
1985 { .compatible = "qcom,i2c-qup-v2.2.1" },
1988 MODULE_DEVICE_TABLE(of, qup_i2c_dt_match);
1990 static struct platform_driver qup_i2c_driver = {
1991 .probe = qup_i2c_probe,
1992 .remove = qup_i2c_remove,
1995 .pm = &qup_i2c_qup_pm_ops,
1996 .of_match_table = qup_i2c_dt_match,
1997 .acpi_match_table = ACPI_PTR(qup_i2c_acpi_match),
2001 module_platform_driver(qup_i2c_driver);
2003 MODULE_LICENSE("GPL v2");
2004 MODULE_ALIAS("platform:i2c_qup");