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[releases.git] / i2c / busses / i2c-mpc.c
1 /*
2  * (C) Copyright 2003-2004
3  * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
4
5  * This is a combined i2c adapter and algorithm driver for the
6  * MPC107/Tsi107 PowerPC northbridge and processors that include
7  * the same I2C unit (8240, 8245, 85xx).
8  *
9  * Release 0.8
10  *
11  * This file is licensed under the terms of the GNU General Public
12  * License version 2. This program is licensed "as is" without any
13  * warranty of any kind, whether express or implied.
14  */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/sched/signal.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_platform.h>
22 #include <linux/slab.h>
23
24 #include <linux/clk.h>
25 #include <linux/io.h>
26 #include <linux/iopoll.h>
27 #include <linux/fsl_devices.h>
28 #include <linux/i2c.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31
32 #include <asm/mpc52xx.h>
33 #include <asm/mpc85xx.h>
34 #include <sysdev/fsl_soc.h>
35
36 #define DRV_NAME "mpc-i2c"
37
38 #define MPC_I2C_CLOCK_LEGACY   0
39 #define MPC_I2C_CLOCK_PRESERVE (~0U)
40
41 #define MPC_I2C_FDR   0x04
42 #define MPC_I2C_CR    0x08
43 #define MPC_I2C_SR    0x0c
44 #define MPC_I2C_DR    0x10
45 #define MPC_I2C_DFSRR 0x14
46
47 #define CCR_MEN  0x80
48 #define CCR_MIEN 0x40
49 #define CCR_MSTA 0x20
50 #define CCR_MTX  0x10
51 #define CCR_TXAK 0x08
52 #define CCR_RSTA 0x04
53 #define CCR_RSVD 0x02
54
55 #define CSR_MCF  0x80
56 #define CSR_MAAS 0x40
57 #define CSR_MBB  0x20
58 #define CSR_MAL  0x10
59 #define CSR_SRW  0x04
60 #define CSR_MIF  0x02
61 #define CSR_RXAK 0x01
62
63 struct mpc_i2c {
64         struct device *dev;
65         void __iomem *base;
66         u32 interrupt;
67         wait_queue_head_t queue;
68         struct i2c_adapter adap;
69         int irq;
70         u32 real_clk;
71 #ifdef CONFIG_PM_SLEEP
72         u8 fdr, dfsrr;
73 #endif
74         struct clk *clk_per;
75         bool has_errata_A004447;
76 };
77
78 struct mpc_i2c_divider {
79         u16 divider;
80         u16 fdr;        /* including dfsrr */
81 };
82
83 struct mpc_i2c_data {
84         void (*setup)(struct device_node *node, struct mpc_i2c *i2c, u32 clock);
85 };
86
87 static inline void writeccr(struct mpc_i2c *i2c, u32 x)
88 {
89         writeb(x, i2c->base + MPC_I2C_CR);
90 }
91
92 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
93 {
94         struct mpc_i2c *i2c = dev_id;
95         if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
96                 /* Read again to allow register to stabilise */
97                 i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
98                 writeb(0, i2c->base + MPC_I2C_SR);
99                 wake_up(&i2c->queue);
100                 return IRQ_HANDLED;
101         }
102         return IRQ_NONE;
103 }
104
105 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
106  * the bus, because it wants to send ACK.
107  * Following sequence of enabling/disabling and sending start/stop generates
108  * the 9 pulses, so it's all OK.
109  */
110 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
111 {
112         int k;
113         u32 delay_val = 1000000 / i2c->real_clk + 1;
114
115         if (delay_val < 2)
116                 delay_val = 2;
117
118         for (k = 9; k; k--) {
119                 writeccr(i2c, 0);
120                 writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
121                 readb(i2c->base + MPC_I2C_DR);
122                 writeccr(i2c, CCR_MEN);
123                 udelay(delay_val << 1);
124         }
125 }
126
127 static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
128 {
129         unsigned long orig_jiffies = jiffies;
130         u32 cmd_err;
131         int result = 0;
132
133         if (!i2c->irq) {
134                 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
135                         schedule();
136                         if (time_after(jiffies, orig_jiffies + timeout)) {
137                                 dev_dbg(i2c->dev, "timeout\n");
138                                 writeccr(i2c, 0);
139                                 result = -ETIMEDOUT;
140                                 break;
141                         }
142                 }
143                 cmd_err = readb(i2c->base + MPC_I2C_SR);
144                 writeb(0, i2c->base + MPC_I2C_SR);
145         } else {
146                 /* Interrupt mode */
147                 result = wait_event_timeout(i2c->queue,
148                         (i2c->interrupt & CSR_MIF), timeout);
149
150                 if (unlikely(!(i2c->interrupt & CSR_MIF))) {
151                         dev_dbg(i2c->dev, "wait timeout\n");
152                         writeccr(i2c, 0);
153                         result = -ETIMEDOUT;
154                 }
155
156                 cmd_err = i2c->interrupt;
157                 i2c->interrupt = 0;
158         }
159
160         if (result < 0)
161                 return result;
162
163         if (!(cmd_err & CSR_MCF)) {
164                 dev_dbg(i2c->dev, "unfinished\n");
165                 return -EIO;
166         }
167
168         if (cmd_err & CSR_MAL) {
169                 dev_dbg(i2c->dev, "MAL\n");
170                 return -EAGAIN;
171         }
172
173         if (writing && (cmd_err & CSR_RXAK)) {
174                 dev_dbg(i2c->dev, "No RXAK\n");
175                 /* generate stop */
176                 writeccr(i2c, CCR_MEN);
177                 return -ENXIO;
178         }
179         return 0;
180 }
181
182 static int i2c_mpc_wait_sr(struct mpc_i2c *i2c, int mask)
183 {
184         void __iomem *addr = i2c->base + MPC_I2C_SR;
185         u8 val;
186
187         return readb_poll_timeout(addr, val, val & mask, 0, 100);
188 }
189
190 /*
191  * Workaround for Erratum A004447. From the P2040CE Rev Q
192  *
193  * 1.  Set up the frequency divider and sampling rate.
194  * 2.  I2CCR - a0h
195  * 3.  Poll for I2CSR[MBB] to get set.
196  * 4.  If I2CSR[MAL] is set (an indication that SDA is stuck low), then go to
197  *     step 5. If MAL is not set, then go to step 13.
198  * 5.  I2CCR - 00h
199  * 6.  I2CCR - 22h
200  * 7.  I2CCR - a2h
201  * 8.  Poll for I2CSR[MBB] to get set.
202  * 9.  Issue read to I2CDR.
203  * 10. Poll for I2CSR[MIF] to be set.
204  * 11. I2CCR - 82h
205  * 12. Workaround complete. Skip the next steps.
206  * 13. Issue read to I2CDR.
207  * 14. Poll for I2CSR[MIF] to be set.
208  * 15. I2CCR - 80h
209  */
210 static void mpc_i2c_fixup_A004447(struct mpc_i2c *i2c)
211 {
212         int ret;
213         u32 val;
214
215         writeccr(i2c, CCR_MEN | CCR_MSTA);
216         ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
217         if (ret) {
218                 dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
219                 return;
220         }
221
222         val = readb(i2c->base + MPC_I2C_SR);
223
224         if (val & CSR_MAL) {
225                 writeccr(i2c, 0x00);
226                 writeccr(i2c, CCR_MSTA | CCR_RSVD);
227                 writeccr(i2c, CCR_MEN | CCR_MSTA | CCR_RSVD);
228                 ret = i2c_mpc_wait_sr(i2c, CSR_MBB);
229                 if (ret) {
230                         dev_err(i2c->dev, "timeout waiting for CSR_MBB\n");
231                         return;
232                 }
233                 val = readb(i2c->base + MPC_I2C_DR);
234                 ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
235                 if (ret) {
236                         dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
237                         return;
238                 }
239                 writeccr(i2c, CCR_MEN | CCR_RSVD);
240         } else {
241                 val = readb(i2c->base + MPC_I2C_DR);
242                 ret = i2c_mpc_wait_sr(i2c, CSR_MIF);
243                 if (ret) {
244                         dev_err(i2c->dev, "timeout waiting for CSR_MIF\n");
245                         return;
246                 }
247                 writeccr(i2c, CCR_MEN);
248         }
249 }
250
251 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
252 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
253         {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
254         {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
255         {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
256         {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
257         {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
258         {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
259         {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
260         {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
261         {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
262         {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
263         {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
264         {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
265         {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
266         {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
267         {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
268         {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
269         {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
270         {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
271 };
272
273 static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
274                                           u32 *real_clk)
275 {
276         const struct mpc_i2c_divider *div = NULL;
277         unsigned int pvr = mfspr(SPRN_PVR);
278         u32 divider;
279         int i;
280
281         if (clock == MPC_I2C_CLOCK_LEGACY) {
282                 /* see below - default fdr = 0x3f -> div = 2048 */
283                 *real_clk = mpc5xxx_get_bus_frequency(node) / 2048;
284                 return -EINVAL;
285         }
286
287         /* Determine divider value */
288         divider = mpc5xxx_get_bus_frequency(node) / clock;
289
290         /*
291          * We want to choose an FDR/DFSR that generates an I2C bus speed that
292          * is equal to or lower than the requested speed.
293          */
294         for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
295                 div = &mpc_i2c_dividers_52xx[i];
296                 /* Old MPC5200 rev A CPUs do not support the high bits */
297                 if (div->fdr & 0xc0 && pvr == 0x80822011)
298                         continue;
299                 if (div->divider >= divider)
300                         break;
301         }
302
303         *real_clk = mpc5xxx_get_bus_frequency(node) / div->divider;
304         return (int)div->fdr;
305 }
306
307 static void mpc_i2c_setup_52xx(struct device_node *node,
308                                          struct mpc_i2c *i2c,
309                                          u32 clock)
310 {
311         int ret, fdr;
312
313         if (clock == MPC_I2C_CLOCK_PRESERVE) {
314                 dev_dbg(i2c->dev, "using fdr %d\n",
315                         readb(i2c->base + MPC_I2C_FDR));
316                 return;
317         }
318
319         ret = mpc_i2c_get_fdr_52xx(node, clock, &i2c->real_clk);
320         fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
321
322         writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
323
324         if (ret >= 0)
325                 dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk,
326                          fdr);
327 }
328 #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
329 static void mpc_i2c_setup_52xx(struct device_node *node,
330                                          struct mpc_i2c *i2c,
331                                          u32 clock)
332 {
333 }
334 #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
335
336 #ifdef CONFIG_PPC_MPC512x
337 static void mpc_i2c_setup_512x(struct device_node *node,
338                                          struct mpc_i2c *i2c,
339                                          u32 clock)
340 {
341         struct device_node *node_ctrl;
342         void __iomem *ctrl;
343         const u32 *pval;
344         u32 idx;
345
346         /* Enable I2C interrupts for mpc5121 */
347         node_ctrl = of_find_compatible_node(NULL, NULL,
348                                             "fsl,mpc5121-i2c-ctrl");
349         if (node_ctrl) {
350                 ctrl = of_iomap(node_ctrl, 0);
351                 if (ctrl) {
352                         /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
353                         pval = of_get_property(node, "reg", NULL);
354                         idx = (*pval & 0xff) / 0x20;
355                         setbits32(ctrl, 1 << (24 + idx * 2));
356                         iounmap(ctrl);
357                 }
358                 of_node_put(node_ctrl);
359         }
360
361         /* The clock setup for the 52xx works also fine for the 512x */
362         mpc_i2c_setup_52xx(node, i2c, clock);
363 }
364 #else /* CONFIG_PPC_MPC512x */
365 static void mpc_i2c_setup_512x(struct device_node *node,
366                                          struct mpc_i2c *i2c,
367                                          u32 clock)
368 {
369 }
370 #endif /* CONFIG_PPC_MPC512x */
371
372 #ifdef CONFIG_FSL_SOC
373 static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
374         {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
375         {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
376         {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
377         {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
378         {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
379         {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
380         {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
381         {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
382         {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
383         {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
384         {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
385         {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
386         {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
387         {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
388         {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
389         {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
390         {49152, 0x011e}, {61440, 0x011f}
391 };
392
393 static u32 mpc_i2c_get_sec_cfg_8xxx(void)
394 {
395         struct device_node *node;
396         u32 __iomem *reg;
397         u32 val = 0;
398
399         node = of_find_node_by_name(NULL, "global-utilities");
400         if (node) {
401                 const u32 *prop = of_get_property(node, "reg", NULL);
402                 if (prop) {
403                         /*
404                          * Map and check POR Device Status Register 2
405                          * (PORDEVSR2) at 0xE0014. Note than while MPC8533
406                          * and MPC8544 indicate SEC frequency ratio
407                          * configuration as bit 26 in PORDEVSR2, other MPC8xxx
408                          * parts may store it differently or may not have it
409                          * at all.
410                          */
411                         reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
412                         if (!reg)
413                                 printk(KERN_ERR
414                                        "Error: couldn't map PORDEVSR2\n");
415                         else
416                                 val = in_be32(reg) & 0x00000020; /* sec-cfg */
417                         iounmap(reg);
418                 }
419         }
420         of_node_put(node);
421
422         return val;
423 }
424
425 static u32 mpc_i2c_get_prescaler_8xxx(void)
426 {
427         /*
428          * According to the AN2919 all MPC824x have prescaler 1, while MPC83xx
429          * may have prescaler 1, 2, or 3, depending on the power-on
430          * configuration.
431          */
432         u32 prescaler = 1;
433
434         /* mpc85xx */
435         if (pvr_version_is(PVR_VER_E500V1) || pvr_version_is(PVR_VER_E500V2)
436                 || pvr_version_is(PVR_VER_E500MC)
437                 || pvr_version_is(PVR_VER_E5500)
438                 || pvr_version_is(PVR_VER_E6500)) {
439                 unsigned int svr = mfspr(SPRN_SVR);
440
441                 if ((SVR_SOC_VER(svr) == SVR_8540)
442                         || (SVR_SOC_VER(svr) == SVR_8541)
443                         || (SVR_SOC_VER(svr) == SVR_8560)
444                         || (SVR_SOC_VER(svr) == SVR_8555)
445                         || (SVR_SOC_VER(svr) == SVR_8610))
446                         /* the above 85xx SoCs have prescaler 1 */
447                         prescaler = 1;
448                 else if ((SVR_SOC_VER(svr) == SVR_8533)
449                         || (SVR_SOC_VER(svr) == SVR_8544))
450                         /* the above 85xx SoCs have prescaler 3 or 2 */
451                         prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
452                 else
453                         /* all the other 85xx have prescaler 2 */
454                         prescaler = 2;
455         }
456
457         return prescaler;
458 }
459
460 static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
461                                           u32 *real_clk)
462 {
463         const struct mpc_i2c_divider *div = NULL;
464         u32 prescaler = mpc_i2c_get_prescaler_8xxx();
465         u32 divider;
466         int i;
467
468         if (clock == MPC_I2C_CLOCK_LEGACY) {
469                 /* see below - default fdr = 0x1031 -> div = 16 * 3072 */
470                 *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072);
471                 return -EINVAL;
472         }
473
474         divider = fsl_get_sys_freq() / clock / prescaler;
475
476         pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
477                  fsl_get_sys_freq(), clock, divider);
478
479         /*
480          * We want to choose an FDR/DFSR that generates an I2C bus speed that
481          * is equal to or lower than the requested speed.
482          */
483         for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
484                 div = &mpc_i2c_dividers_8xxx[i];
485                 if (div->divider >= divider)
486                         break;
487         }
488
489         *real_clk = fsl_get_sys_freq() / prescaler / div->divider;
490         return div ? (int)div->fdr : -EINVAL;
491 }
492
493 static void mpc_i2c_setup_8xxx(struct device_node *node,
494                                          struct mpc_i2c *i2c,
495                                          u32 clock)
496 {
497         int ret, fdr;
498
499         if (clock == MPC_I2C_CLOCK_PRESERVE) {
500                 dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
501                         readb(i2c->base + MPC_I2C_DFSRR),
502                         readb(i2c->base + MPC_I2C_FDR));
503                 return;
504         }
505
506         ret = mpc_i2c_get_fdr_8xxx(node, clock, &i2c->real_clk);
507         fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
508
509         writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
510         writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
511
512         if (ret >= 0)
513                 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
514                          i2c->real_clk, fdr >> 8, fdr & 0xff);
515 }
516
517 #else /* !CONFIG_FSL_SOC */
518 static void mpc_i2c_setup_8xxx(struct device_node *node,
519                                          struct mpc_i2c *i2c,
520                                          u32 clock)
521 {
522 }
523 #endif /* CONFIG_FSL_SOC */
524
525 static void mpc_i2c_start(struct mpc_i2c *i2c)
526 {
527         /* Clear arbitration */
528         writeb(0, i2c->base + MPC_I2C_SR);
529         /* Start with MEN */
530         writeccr(i2c, CCR_MEN);
531 }
532
533 static void mpc_i2c_stop(struct mpc_i2c *i2c)
534 {
535         writeccr(i2c, CCR_MEN);
536 }
537
538 static int mpc_write(struct mpc_i2c *i2c, int target,
539                      const u8 *data, int length, int restart)
540 {
541         int i, result;
542         unsigned timeout = i2c->adap.timeout;
543         u32 flags = restart ? CCR_RSTA : 0;
544
545         /* Start as master */
546         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
547         /* Write target byte */
548         writeb((target << 1), i2c->base + MPC_I2C_DR);
549
550         result = i2c_wait(i2c, timeout, 1);
551         if (result < 0)
552                 return result;
553
554         for (i = 0; i < length; i++) {
555                 /* Write data byte */
556                 writeb(data[i], i2c->base + MPC_I2C_DR);
557
558                 result = i2c_wait(i2c, timeout, 1);
559                 if (result < 0)
560                         return result;
561         }
562
563         return 0;
564 }
565
566 static int mpc_read(struct mpc_i2c *i2c, int target,
567                     u8 *data, int length, int restart, bool recv_len)
568 {
569         unsigned timeout = i2c->adap.timeout;
570         int i, result;
571         u32 flags = restart ? CCR_RSTA : 0;
572
573         /* Switch to read - restart */
574         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
575         /* Write target address byte - this time with the read flag set */
576         writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
577
578         result = i2c_wait(i2c, timeout, 1);
579         if (result < 0)
580                 return result;
581
582         if (length) {
583                 if (length == 1 && !recv_len)
584                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
585                 else
586                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
587                 /* Dummy read */
588                 readb(i2c->base + MPC_I2C_DR);
589         }
590
591         for (i = 0; i < length; i++) {
592                 u8 byte;
593
594                 result = i2c_wait(i2c, timeout, 0);
595                 if (result < 0)
596                         return result;
597
598                 /*
599                  * For block reads, we have to know the total length (1st byte)
600                  * before we can determine if we are done.
601                  */
602                 if (i || !recv_len) {
603                         /* Generate txack on next to last byte */
604                         if (i == length - 2)
605                                 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
606                                          | CCR_TXAK);
607                         /* Do not generate stop on last byte */
608                         if (i == length - 1)
609                                 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
610                                          | CCR_MTX);
611                 }
612
613                 byte = readb(i2c->base + MPC_I2C_DR);
614
615                 /*
616                  * Adjust length if first received byte is length.
617                  * The length is 1 length byte plus actually data length
618                  */
619                 if (i == 0 && recv_len) {
620                         if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX)
621                                 return -EPROTO;
622                         length += byte;
623                         /*
624                          * For block reads, generate txack here if data length
625                          * is 1 byte (total length is 2 bytes).
626                          */
627                         if (length == 2)
628                                 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
629                                          | CCR_TXAK);
630                 }
631                 data[i] = byte;
632         }
633
634         return length;
635 }
636
637 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
638 {
639         struct i2c_msg *pmsg;
640         int i;
641         int ret = 0;
642         unsigned long orig_jiffies = jiffies;
643         struct mpc_i2c *i2c = i2c_get_adapdata(adap);
644
645         mpc_i2c_start(i2c);
646
647         /* Allow bus up to 1s to become not busy */
648         while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
649                 if (signal_pending(current)) {
650                         dev_dbg(i2c->dev, "Interrupted\n");
651                         writeccr(i2c, 0);
652                         return -EINTR;
653                 }
654                 if (time_after(jiffies, orig_jiffies + HZ)) {
655                         u8 status = readb(i2c->base + MPC_I2C_SR);
656
657                         dev_dbg(i2c->dev, "timeout\n");
658                         if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
659                                 writeb(status & ~CSR_MAL,
660                                        i2c->base + MPC_I2C_SR);
661                                 i2c_recover_bus(&i2c->adap);
662                         }
663                         return -EIO;
664                 }
665                 schedule();
666         }
667
668         for (i = 0; ret >= 0 && i < num; i++) {
669                 pmsg = &msgs[i];
670                 dev_dbg(i2c->dev,
671                         "Doing %s %d bytes to 0x%02x - %d of %d messages\n",
672                         pmsg->flags & I2C_M_RD ? "read" : "write",
673                         pmsg->len, pmsg->addr, i + 1, num);
674                 if (pmsg->flags & I2C_M_RD) {
675                         bool recv_len = pmsg->flags & I2C_M_RECV_LEN;
676
677                         ret = mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i,
678                                        recv_len);
679                         if (recv_len && ret > 0)
680                                 pmsg->len = ret;
681                 } else {
682                         ret =
683                             mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
684                 }
685         }
686         mpc_i2c_stop(i2c); /* Initiate STOP */
687         orig_jiffies = jiffies;
688         /* Wait until STOP is seen, allow up to 1 s */
689         while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
690                 if (time_after(jiffies, orig_jiffies + HZ)) {
691                         u8 status = readb(i2c->base + MPC_I2C_SR);
692
693                         dev_dbg(i2c->dev, "timeout\n");
694                         if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
695                                 writeb(status & ~CSR_MAL,
696                                        i2c->base + MPC_I2C_SR);
697                                 i2c_recover_bus(&i2c->adap);
698                         }
699                         return -EIO;
700                 }
701                 cond_resched();
702         }
703         return (ret < 0) ? ret : num;
704 }
705
706 static u32 mpc_functionality(struct i2c_adapter *adap)
707 {
708         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
709           | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL;
710 }
711
712 static int fsl_i2c_bus_recovery(struct i2c_adapter *adap)
713 {
714         struct mpc_i2c *i2c = i2c_get_adapdata(adap);
715
716         if (i2c->has_errata_A004447)
717                 mpc_i2c_fixup_A004447(i2c);
718         else
719                 mpc_i2c_fixup(i2c);
720
721         return 0;
722 }
723
724 static const struct i2c_algorithm mpc_algo = {
725         .master_xfer = mpc_xfer,
726         .functionality = mpc_functionality,
727 };
728
729 static struct i2c_adapter mpc_ops = {
730         .owner = THIS_MODULE,
731         .algo = &mpc_algo,
732         .timeout = HZ,
733 };
734
735 static struct i2c_bus_recovery_info fsl_i2c_recovery_info = {
736         .recover_bus = fsl_i2c_bus_recovery,
737 };
738
739 static const struct of_device_id mpc_i2c_of_match[];
740 static int fsl_i2c_probe(struct platform_device *op)
741 {
742         const struct of_device_id *match;
743         struct mpc_i2c *i2c;
744         const u32 *prop;
745         u32 clock = MPC_I2C_CLOCK_LEGACY;
746         int result = 0;
747         int plen;
748         struct resource res;
749         struct clk *clk;
750         int err;
751
752         match = of_match_device(mpc_i2c_of_match, &op->dev);
753         if (!match)
754                 return -EINVAL;
755
756         i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
757         if (!i2c)
758                 return -ENOMEM;
759
760         i2c->dev = &op->dev; /* for debug and error output */
761
762         init_waitqueue_head(&i2c->queue);
763
764         i2c->base = of_iomap(op->dev.of_node, 0);
765         if (!i2c->base) {
766                 dev_err(i2c->dev, "failed to map controller\n");
767                 result = -ENOMEM;
768                 goto fail_map;
769         }
770
771         i2c->irq = irq_of_parse_and_map(op->dev.of_node, 0);
772         if (i2c->irq) { /* no i2c->irq implies polling */
773                 result = request_irq(i2c->irq, mpc_i2c_isr,
774                                      IRQF_SHARED, "i2c-mpc", i2c);
775                 if (result < 0) {
776                         dev_err(i2c->dev, "failed to attach interrupt\n");
777                         goto fail_request;
778                 }
779         }
780
781         /*
782          * enable clock for the I2C peripheral (non fatal),
783          * keep a reference upon successful allocation
784          */
785         clk = devm_clk_get(&op->dev, NULL);
786         if (!IS_ERR(clk)) {
787                 err = clk_prepare_enable(clk);
788                 if (err) {
789                         dev_err(&op->dev, "failed to enable clock\n");
790                         goto fail_request;
791                 } else {
792                         i2c->clk_per = clk;
793                 }
794         }
795
796         if (of_property_read_bool(op->dev.of_node, "fsl,preserve-clocking")) {
797                 clock = MPC_I2C_CLOCK_PRESERVE;
798         } else {
799                 prop = of_get_property(op->dev.of_node, "clock-frequency",
800                                         &plen);
801                 if (prop && plen == sizeof(u32))
802                         clock = *prop;
803         }
804
805         if (match->data) {
806                 const struct mpc_i2c_data *data = match->data;
807                 data->setup(op->dev.of_node, i2c, clock);
808         } else {
809                 /* Backwards compatibility */
810                 if (of_get_property(op->dev.of_node, "dfsrr", NULL))
811                         mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock);
812         }
813
814         prop = of_get_property(op->dev.of_node, "fsl,timeout", &plen);
815         if (prop && plen == sizeof(u32)) {
816                 mpc_ops.timeout = *prop * HZ / 1000000;
817                 if (mpc_ops.timeout < 5)
818                         mpc_ops.timeout = 5;
819         }
820         dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
821
822         platform_set_drvdata(op, i2c);
823         if (of_property_read_bool(op->dev.of_node, "fsl,i2c-erratum-a004447"))
824                 i2c->has_errata_A004447 = true;
825
826         i2c->adap = mpc_ops;
827         of_address_to_resource(op->dev.of_node, 0, &res);
828         scnprintf(i2c->adap.name, sizeof(i2c->adap.name),
829                   "MPC adapter at 0x%llx", (unsigned long long)res.start);
830         i2c_set_adapdata(&i2c->adap, i2c);
831         i2c->adap.dev.parent = &op->dev;
832         i2c->adap.dev.of_node = of_node_get(op->dev.of_node);
833         i2c->adap.bus_recovery_info = &fsl_i2c_recovery_info;
834
835         result = i2c_add_adapter(&i2c->adap);
836         if (result < 0)
837                 goto fail_add;
838
839         return result;
840
841  fail_add:
842         if (i2c->clk_per)
843                 clk_disable_unprepare(i2c->clk_per);
844         free_irq(i2c->irq, i2c);
845  fail_request:
846         irq_dispose_mapping(i2c->irq);
847         iounmap(i2c->base);
848  fail_map:
849         kfree(i2c);
850         return result;
851 };
852
853 static int fsl_i2c_remove(struct platform_device *op)
854 {
855         struct mpc_i2c *i2c = platform_get_drvdata(op);
856
857         i2c_del_adapter(&i2c->adap);
858
859         if (i2c->clk_per)
860                 clk_disable_unprepare(i2c->clk_per);
861
862         if (i2c->irq)
863                 free_irq(i2c->irq, i2c);
864
865         irq_dispose_mapping(i2c->irq);
866         iounmap(i2c->base);
867         kfree(i2c);
868         return 0;
869 };
870
871 #ifdef CONFIG_PM_SLEEP
872 static int mpc_i2c_suspend(struct device *dev)
873 {
874         struct mpc_i2c *i2c = dev_get_drvdata(dev);
875
876         i2c->fdr = readb(i2c->base + MPC_I2C_FDR);
877         i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR);
878
879         return 0;
880 }
881
882 static int mpc_i2c_resume(struct device *dev)
883 {
884         struct mpc_i2c *i2c = dev_get_drvdata(dev);
885
886         writeb(i2c->fdr, i2c->base + MPC_I2C_FDR);
887         writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR);
888
889         return 0;
890 }
891
892 static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume);
893 #define MPC_I2C_PM_OPS  (&mpc_i2c_pm_ops)
894 #else
895 #define MPC_I2C_PM_OPS  NULL
896 #endif
897
898 static const struct mpc_i2c_data mpc_i2c_data_512x = {
899         .setup = mpc_i2c_setup_512x,
900 };
901
902 static const struct mpc_i2c_data mpc_i2c_data_52xx = {
903         .setup = mpc_i2c_setup_52xx,
904 };
905
906 static const struct mpc_i2c_data mpc_i2c_data_8313 = {
907         .setup = mpc_i2c_setup_8xxx,
908 };
909
910 static const struct mpc_i2c_data mpc_i2c_data_8543 = {
911         .setup = mpc_i2c_setup_8xxx,
912 };
913
914 static const struct mpc_i2c_data mpc_i2c_data_8544 = {
915         .setup = mpc_i2c_setup_8xxx,
916 };
917
918 static const struct of_device_id mpc_i2c_of_match[] = {
919         {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
920         {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
921         {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
922         {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
923         {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
924         {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
925         {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
926         /* Backward compatibility */
927         {.compatible = "fsl-i2c", },
928         {},
929 };
930 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
931
932 /* Structure for a device driver */
933 static struct platform_driver mpc_i2c_driver = {
934         .probe          = fsl_i2c_probe,
935         .remove         = fsl_i2c_remove,
936         .driver = {
937                 .name = DRV_NAME,
938                 .of_match_table = mpc_i2c_of_match,
939                 .pm = MPC_I2C_PM_OPS,
940         },
941 };
942
943 module_platform_driver(mpc_i2c_driver);
944
945 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
946 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
947                    "MPC824x/83xx/85xx/86xx/512x/52xx processors");
948 MODULE_LICENSE("GPL");