1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for Intel(R) 10nm server memory controller.
4 * Copyright (c) 2019, Intel Corporation.
8 #include <linux/kernel.h>
10 #include <asm/cpu_device_id.h>
11 #include <asm/intel-family.h>
13 #include "edac_module.h"
14 #include "skx_common.h"
16 #define I10NM_REVISION "v0.0.3"
17 #define EDAC_MOD_STR "i10nm_edac"
20 #define i10nm_printk(level, fmt, arg...) \
21 edac_printk(level, "i10nm", fmt, ##arg)
23 #define I10NM_GET_SCK_BAR(d, reg) \
24 pci_read_config_dword((d)->uracu, 0xd0, &(reg))
25 #define I10NM_GET_IMC_BAR(d, i, reg) \
26 pci_read_config_dword((d)->uracu, 0xd8 + (i) * 4, &(reg))
27 #define I10NM_GET_DIMMMTR(m, i, j) \
28 readl((m)->mbase + 0x2080c + (i) * 0x4000 + (j) * 4)
29 #define I10NM_GET_MCDDRTCFG(m, i) \
30 readl((m)->mbase + 0x20970 + (i) * 0x4000)
31 #define I10NM_GET_MCMTR(m, i) \
32 readl((m)->mbase + 0x20ef8 + (i) * 0x4000)
34 #define I10NM_GET_SCK_MMIO_BASE(reg) (GET_BITFIELD(reg, 0, 28) << 23)
35 #define I10NM_GET_IMC_MMIO_OFFSET(reg) (GET_BITFIELD(reg, 0, 10) << 12)
36 #define I10NM_GET_IMC_MMIO_SIZE(reg) ((GET_BITFIELD(reg, 13, 23) - \
37 GET_BITFIELD(reg, 0, 10) + 1) << 12)
39 static struct list_head *i10nm_edac_list;
41 static struct pci_dev *pci_get_dev_wrapper(int dom, unsigned int bus,
42 unsigned int dev, unsigned int fun)
46 pdev = pci_get_domain_bus_and_slot(dom, bus, PCI_DEVFN(dev, fun));
48 edac_dbg(2, "No device %02x:%02x.%x\n",
53 if (unlikely(pci_enable_device(pdev) < 0)) {
54 edac_dbg(2, "Failed to enable device %02x:%02x.%x\n",
64 static int i10nm_get_all_munits(void)
74 list_for_each_entry(d, i10nm_edac_list, list) {
75 d->util_all = pci_get_dev_wrapper(d->seg, d->bus[1], 29, 1);
79 d->uracu = pci_get_dev_wrapper(d->seg, d->bus[0], 0, 1);
83 if (I10NM_GET_SCK_BAR(d, reg)) {
84 i10nm_printk(KERN_ERR, "Failed to socket bar\n");
88 base = I10NM_GET_SCK_MMIO_BASE(reg);
89 edac_dbg(2, "socket%d mmio base 0x%llx (reg 0x%x)\n",
92 for (i = 0; i < I10NM_NUM_IMC; i++) {
93 mdev = pci_get_dev_wrapper(d->seg, d->bus[0],
95 if (i == 0 && !mdev) {
96 i10nm_printk(KERN_ERR, "No IMC found\n");
102 d->imc[i].mdev = mdev;
104 if (I10NM_GET_IMC_BAR(d, i, reg)) {
105 i10nm_printk(KERN_ERR, "Failed to get mc bar\n");
109 off = I10NM_GET_IMC_MMIO_OFFSET(reg);
110 size = I10NM_GET_IMC_MMIO_SIZE(reg);
111 edac_dbg(2, "mc%d mmio base 0x%llx size 0x%lx (reg 0x%x)\n",
112 i, base + off, size, reg);
114 mbase = ioremap(base + off, size);
116 i10nm_printk(KERN_ERR, "Failed to ioremap 0x%llx\n",
121 d->imc[i].mbase = mbase;
128 static struct res_config i10nm_cfg0 = {
131 .busno_cfg_offset = 0xcc,
134 static struct res_config i10nm_cfg1 = {
137 .busno_cfg_offset = 0xd0,
140 static const struct x86_cpu_id i10nm_cpuids[] = {
141 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
142 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
143 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X, X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
144 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_X, X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
145 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_D, X86_STEPPINGS(0x0, 0xf), &i10nm_cfg1),
148 MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids);
150 static bool i10nm_check_ecc(struct skx_imc *imc, int chan)
154 mcmtr = I10NM_GET_MCMTR(imc, chan);
155 edac_dbg(1, "ch%d mcmtr reg %x\n", chan, mcmtr);
157 return !!GET_BITFIELD(mcmtr, 2, 2);
160 static int i10nm_get_dimm_config(struct mem_ctl_info *mci)
162 struct skx_pvt *pvt = mci->pvt_info;
163 struct skx_imc *imc = pvt->imc;
164 struct dimm_info *dimm;
168 for (i = 0; i < I10NM_NUM_CHANNELS; i++) {
173 mcddrtcfg = I10NM_GET_MCDDRTCFG(imc, i);
174 for (j = 0; j < I10NM_NUM_DIMMS; j++) {
175 dimm = edac_get_dimm(mci, i, j, 0);
176 mtr = I10NM_GET_DIMMMTR(imc, i, j);
177 edac_dbg(1, "dimmmtr 0x%x mcddrtcfg 0x%x (mc%d ch%d dimm%d)\n",
178 mtr, mcddrtcfg, imc->mc, i, j);
180 if (IS_DIMM_PRESENT(mtr))
181 ndimms += skx_get_dimm_info(mtr, 0, 0, dimm,
183 else if (IS_NVDIMM_PRESENT(mcddrtcfg, j))
184 ndimms += skx_get_nvdimm_info(dimm, imc, i, j,
187 if (ndimms && !i10nm_check_ecc(imc, i)) {
188 i10nm_printk(KERN_ERR, "ECC is disabled on imc %d channel %d\n",
197 static struct notifier_block i10nm_mce_dec = {
198 .notifier_call = skx_mce_check_error,
199 .priority = MCE_PRIO_EDAC,
202 #ifdef CONFIG_EDAC_DEBUG
205 * Exercise the address decode logic by writing an address to
206 * /sys/kernel/debug/edac/i10nm_test/addr.
208 static struct dentry *i10nm_test;
210 static int debugfs_u64_set(void *data, u64 val)
214 pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val);
216 memset(&m, 0, sizeof(m));
217 /* ADDRV + MemRd + Unknown channel */
218 m.status = MCI_STATUS_ADDRV + 0x90;
219 /* One corrected error */
220 m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT);
222 skx_mce_check_error(NULL, 0, &m);
226 DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");
228 static void setup_i10nm_debug(void)
230 i10nm_test = edac_debugfs_create_dir("i10nm_test");
234 if (!edac_debugfs_create_file("addr", 0200, i10nm_test,
235 NULL, &fops_u64_wo)) {
236 debugfs_remove(i10nm_test);
241 static void teardown_i10nm_debug(void)
243 debugfs_remove_recursive(i10nm_test);
246 static inline void setup_i10nm_debug(void) {}
247 static inline void teardown_i10nm_debug(void) {}
248 #endif /*CONFIG_EDAC_DEBUG*/
250 static int __init i10nm_init(void)
252 u8 mc = 0, src_id = 0, node_id = 0;
253 const struct x86_cpu_id *id;
254 struct res_config *cfg;
257 int rc, i, off[3] = {0xd0, 0xc8, 0xcc};
262 owner = edac_get_owner();
263 if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR)))
266 if (cpu_feature_enabled(X86_FEATURE_HYPERVISOR))
269 id = x86_match_cpu(i10nm_cpuids);
273 cfg = (struct res_config *)id->driver_data;
275 rc = skx_get_hi_lo(0x09a2, off, &tolm, &tohm);
279 rc = skx_get_all_bus_mappings(cfg, &i10nm_edac_list);
283 i10nm_printk(KERN_ERR, "No memory controllers found\n");
287 rc = i10nm_get_all_munits();
291 list_for_each_entry(d, i10nm_edac_list, list) {
292 rc = skx_get_src_id(d, 0xf8, &src_id);
296 rc = skx_get_node_id(d, &node_id);
300 edac_dbg(2, "src_id = %d node_id = %d\n", src_id, node_id);
301 for (i = 0; i < I10NM_NUM_IMC; i++) {
307 d->imc[i].src_id = src_id;
308 d->imc[i].node_id = node_id;
310 rc = skx_register_mci(&d->imc[i], d->imc[i].mdev,
311 "Intel_10nm Socket", EDAC_MOD_STR,
312 i10nm_get_dimm_config);
323 mce_register_decode_chain(&i10nm_mce_dec);
326 i10nm_printk(KERN_INFO, "%s\n", I10NM_REVISION);
334 static void __exit i10nm_exit(void)
337 teardown_i10nm_debug();
338 mce_unregister_decode_chain(&i10nm_mce_dec);
343 module_init(i10nm_init);
344 module_exit(i10nm_exit);
346 MODULE_LICENSE("GPL v2");
347 MODULE_DESCRIPTION("MC Driver for Intel 10nm server processors");