1 /******************************************************************************
3 * Copyright(c) 2009-2010 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
40 #include "../pwrseqcmd.h"
42 #include "../btcoexist/rtl_btc.h"
46 static void _rtl8821ae_return_beacon_queue_skb(struct ieee80211_hw *hw)
48 struct rtl_priv *rtlpriv = rtl_priv(hw);
49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
50 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
53 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
54 while (skb_queue_len(&ring->queue)) {
55 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
56 struct sk_buff *skb = __skb_dequeue(&ring->queue);
58 pci_unmap_single(rtlpci->pdev,
59 rtlpriv->cfg->ops->get_desc(
60 (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
61 skb->len, PCI_DMA_TODEVICE);
63 ring->idx = (ring->idx + 1) % ring->entries;
65 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
68 static void _rtl8821ae_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
69 u8 set_bits, u8 clear_bits)
71 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
72 struct rtl_priv *rtlpriv = rtl_priv(hw);
74 rtlpci->reg_bcn_ctrl_val |= set_bits;
75 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
77 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
80 void _rtl8821ae_stop_tx_beacon(struct ieee80211_hw *hw)
82 struct rtl_priv *rtlpriv = rtl_priv(hw);
85 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
86 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
87 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
88 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
89 tmp1byte &= ~(BIT(0));
90 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
93 void _rtl8821ae_resume_tx_beacon(struct ieee80211_hw *hw)
95 struct rtl_priv *rtlpriv = rtl_priv(hw);
98 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
99 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
100 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
101 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
103 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
106 static void _rtl8821ae_enable_bcn_sub_func(struct ieee80211_hw *hw)
108 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(1));
111 static void _rtl8821ae_disable_bcn_sub_func(struct ieee80211_hw *hw)
113 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(1), 0);
116 static void _rtl8821ae_set_fw_clock_on(struct ieee80211_hw *hw,
117 u8 rpwm_val, bool b_need_turn_off_ckk)
119 struct rtl_priv *rtlpriv = rtl_priv(hw);
120 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
121 bool b_support_remote_wake_up;
122 u32 count = 0, isr_regaddr, content;
123 bool b_schedule_timer = b_need_turn_off_ckk;
125 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
126 (u8 *)(&b_support_remote_wake_up));
128 if (!rtlhal->fw_ready)
130 if (!rtlpriv->psc.fw_current_inpsmode)
134 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
135 if (rtlhal->fw_clk_change_in_progress) {
136 while (rtlhal->fw_clk_change_in_progress) {
137 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
142 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
144 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
146 rtlhal->fw_clk_change_in_progress = false;
147 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
152 if (IS_IN_LOW_POWER_STATE_8821AE(rtlhal->fw_ps_state)) {
153 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
155 if (FW_PS_IS_ACK(rpwm_val)) {
156 isr_regaddr = REG_HISR;
157 content = rtl_read_dword(rtlpriv, isr_regaddr);
158 while (!(content & IMR_CPWM) && (count < 500)) {
161 content = rtl_read_dword(rtlpriv, isr_regaddr);
164 if (content & IMR_CPWM) {
165 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
166 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_8821AE;
167 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
168 "Receive CPWM INT!!! Set rtlhal->FwPSState = %X\n",
169 rtlhal->fw_ps_state);
173 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
174 rtlhal->fw_clk_change_in_progress = false;
175 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
176 if (b_schedule_timer)
177 mod_timer(&rtlpriv->works.fw_clockoff_timer,
178 jiffies + MSECS(10));
180 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
181 rtlhal->fw_clk_change_in_progress = false;
182 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
186 static void _rtl8821ae_set_fw_clock_off(struct ieee80211_hw *hw,
189 struct rtl_priv *rtlpriv = rtl_priv(hw);
190 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
191 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
192 struct rtl8192_tx_ring *ring;
193 enum rf_pwrstate rtstate;
194 bool b_schedule_timer = false;
197 if (!rtlhal->fw_ready)
199 if (!rtlpriv->psc.fw_current_inpsmode)
201 if (!rtlhal->allow_sw_to_change_hwclc)
203 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
204 if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
207 for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
208 ring = &rtlpci->tx_ring[queue];
209 if (skb_queue_len(&ring->queue)) {
210 b_schedule_timer = true;
215 if (b_schedule_timer) {
216 mod_timer(&rtlpriv->works.fw_clockoff_timer,
217 jiffies + MSECS(10));
221 if (FW_PS_STATE(rtlhal->fw_ps_state) !=
222 FW_PS_STATE_RF_OFF_LOW_PWR_8821AE) {
223 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
224 if (!rtlhal->fw_clk_change_in_progress) {
225 rtlhal->fw_clk_change_in_progress = true;
226 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
227 rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
228 rtl_write_word(rtlpriv, REG_HISR, 0x0100);
229 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
231 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
232 rtlhal->fw_clk_change_in_progress = false;
233 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
235 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
236 mod_timer(&rtlpriv->works.fw_clockoff_timer,
237 jiffies + MSECS(10));
242 static void _rtl8821ae_set_fw_ps_rf_on(struct ieee80211_hw *hw)
246 rpwm_val |= (FW_PS_STATE_RF_OFF_8821AE | FW_PS_ACK);
247 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, true);
250 static void _rtl8821ae_fwlps_leave(struct ieee80211_hw *hw)
252 struct rtl_priv *rtlpriv = rtl_priv(hw);
253 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
254 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
255 bool fw_current_inps = false;
256 u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
258 if (ppsc->low_power_enable) {
259 rpwm_val = (FW_PS_STATE_ALL_ON_8821AE|FW_PS_ACK);/* RF on */
260 _rtl8821ae_set_fw_clock_on(hw, rpwm_val, false);
261 rtlhal->allow_sw_to_change_hwclc = false;
262 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
263 (u8 *)(&fw_pwrmode));
264 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
265 (u8 *)(&fw_current_inps));
267 rpwm_val = FW_PS_STATE_ALL_ON_8821AE; /* RF on */
268 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
270 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
271 (u8 *)(&fw_pwrmode));
272 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
273 (u8 *)(&fw_current_inps));
277 static void _rtl8821ae_fwlps_enter(struct ieee80211_hw *hw)
279 struct rtl_priv *rtlpriv = rtl_priv(hw);
280 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
281 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
282 bool fw_current_inps = true;
285 if (ppsc->low_power_enable) {
286 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_8821AE; /* RF off */
287 rtlpriv->cfg->ops->set_hw_reg(hw,
288 HW_VAR_FW_PSMODE_STATUS,
289 (u8 *)(&fw_current_inps));
290 rtlpriv->cfg->ops->set_hw_reg(hw,
291 HW_VAR_H2C_FW_PWRMODE,
292 (u8 *)(&ppsc->fwctrl_psmode));
293 rtlhal->allow_sw_to_change_hwclc = true;
294 _rtl8821ae_set_fw_clock_off(hw, rpwm_val);
296 rpwm_val = FW_PS_STATE_RF_OFF_8821AE; /* RF off */
297 rtlpriv->cfg->ops->set_hw_reg(hw,
298 HW_VAR_FW_PSMODE_STATUS,
299 (u8 *)(&fw_current_inps));
300 rtlpriv->cfg->ops->set_hw_reg(hw,
301 HW_VAR_H2C_FW_PWRMODE,
302 (u8 *)(&ppsc->fwctrl_psmode));
303 rtlpriv->cfg->ops->set_hw_reg(hw,
309 static void _rtl8821ae_download_rsvd_page(struct ieee80211_hw *hw,
310 bool dl_whole_packets)
312 struct rtl_priv *rtlpriv = rtl_priv(hw);
313 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
314 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
315 u8 count = 0, dlbcn_count = 0;
316 bool send_beacon = false;
318 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
319 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr | BIT(0)));
321 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
322 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
324 tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
325 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
326 tmp_reg422 & (~BIT(6)));
327 if (tmp_reg422 & BIT(6))
331 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
332 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
333 (bcnvalid_reg | BIT(0)));
334 _rtl8821ae_return_beacon_queue_skb(hw);
336 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
337 rtl8812ae_set_fw_rsvdpagepkt(hw, false,
340 rtl8821ae_set_fw_rsvdpagepkt(hw, false,
343 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
345 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
348 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
351 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
353 if (!(bcnvalid_reg & BIT(0)))
354 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
355 "Download RSVD page failed!\n");
356 if (bcnvalid_reg & BIT(0) && rtlhal->enter_pnp_sleep) {
357 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, bcnvalid_reg | BIT(0));
358 _rtl8821ae_return_beacon_queue_skb(hw);
362 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
363 bcnvalid_reg | BIT(0));
365 _rtl8821ae_return_beacon_queue_skb(hw);
367 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
368 rtl8812ae_set_fw_rsvdpagepkt(hw, true,
371 rtl8821ae_set_fw_rsvdpagepkt(hw, true,
374 /* check rsvd page download OK. */
375 bcnvalid_reg = rtl_read_byte(rtlpriv,
378 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
382 rtl_read_byte(rtlpriv,
386 } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
388 if (!(bcnvalid_reg & BIT(0)))
389 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
390 "2 Download RSVD page failed!\n");
394 if (bcnvalid_reg & BIT(0))
395 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
397 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
398 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
401 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
403 if (!rtlhal->enter_pnp_sleep) {
404 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
405 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
409 void rtl8821ae_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
411 struct rtl_priv *rtlpriv = rtl_priv(hw);
412 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
413 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
414 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
417 case HW_VAR_ETHER_ADDR:
418 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_MACID);
419 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_MACID + 4);
422 *((u32 *)(val)) = rtl_read_dword(rtlpriv, REG_BSSID);
423 *((u16 *)(val+4)) = rtl_read_word(rtlpriv, REG_BSSID+4);
425 case HW_VAR_MEDIA_STATUS:
426 val[0] = rtl_read_byte(rtlpriv, MSR) & 0x3;
428 case HW_VAR_SLOT_TIME:
429 *((u8 *)(val)) = mac->slot_time;
431 case HW_VAR_BEACON_INTERVAL:
432 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_BCN_INTERVAL);
434 case HW_VAR_ATIM_WINDOW:
435 *((u16 *)(val)) = rtl_read_word(rtlpriv, REG_ATIMWND);
438 *((u32 *)(val)) = rtlpci->receive_config;
440 case HW_VAR_RF_STATE:
441 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
443 case HW_VAR_FWLPS_RF_ON:{
444 enum rf_pwrstate rfstate;
447 rtlpriv->cfg->ops->get_hw_reg(hw,
450 if (rfstate == ERFOFF) {
451 *((bool *)(val)) = true;
453 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
454 val_rcr &= 0x00070000;
456 *((bool *)(val)) = false;
458 *((bool *)(val)) = true;
461 case HW_VAR_FW_PSMODE_STATUS:
462 *((bool *)(val)) = ppsc->fw_current_inpsmode;
464 case HW_VAR_CORRECT_TSF:{
466 u32 *ptsf_low = (u32 *)&tsf;
467 u32 *ptsf_high = ((u32 *)&tsf) + 1;
469 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
470 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
472 *((u64 *)(val)) = tsf;
476 if (ppsc->wo_wlan_mode)
477 *((bool *)(val)) = true;
479 *((bool *)(val)) = false;
482 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
483 "switch case not process %x\n", variable);
488 void rtl8821ae_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
490 struct rtl_priv *rtlpriv = rtl_priv(hw);
491 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
492 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
493 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
494 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
495 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
499 case HW_VAR_ETHER_ADDR:{
500 for (idx = 0; idx < ETH_ALEN; idx++) {
501 rtl_write_byte(rtlpriv, (REG_MACID + idx),
506 case HW_VAR_BASIC_RATE:{
507 u16 b_rate_cfg = ((u16 *)val)[0];
508 b_rate_cfg = b_rate_cfg & 0x15f;
509 rtl_write_word(rtlpriv, REG_RRSR, b_rate_cfg);
513 for (idx = 0; idx < ETH_ALEN; idx++) {
514 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
520 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
521 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[0]);
523 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
524 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
526 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
527 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM, val[0]);
529 case HW_VAR_R2T_SIFS:
530 rtl_write_byte(rtlpriv, REG_RESP_SIFS_OFDM + 1, val[0]);
532 case HW_VAR_SLOT_TIME:{
535 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
536 "HW_VAR_SLOT_TIME %x\n", val[0]);
538 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
540 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
541 rtlpriv->cfg->ops->set_hw_reg(hw,
546 case HW_VAR_ACK_PREAMBLE:{
548 u8 short_preamble = (bool)(*(u8 *)val);
550 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
551 if (short_preamble) {
553 rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2,
556 reg_tmp &= (~BIT(1));
557 rtl_write_byte(rtlpriv,
562 case HW_VAR_WPA_CONFIG:
563 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
565 case HW_VAR_AMPDU_MIN_SPACE:{
566 u8 min_spacing_to_set;
569 min_spacing_to_set = *((u8 *)val);
570 if (min_spacing_to_set <= 7) {
573 if (min_spacing_to_set < sec_min_space)
574 min_spacing_to_set = sec_min_space;
576 mac->min_space_cfg = ((mac->min_space_cfg &
580 *val = min_spacing_to_set;
582 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
583 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
586 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
590 case HW_VAR_SHORTGI_DENSITY:{
593 density_to_set = *((u8 *)val);
594 mac->min_space_cfg |= (density_to_set << 3);
596 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
597 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
600 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
604 case HW_VAR_AMPDU_FACTOR:{
605 u32 ampdu_len = (*((u8 *)val));
607 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
608 if (ampdu_len < VHT_AGG_SIZE_128K)
610 (0x2000 << (*((u8 *)val))) - 1;
613 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
614 if (ampdu_len < HT_AGG_SIZE_64K)
616 (0x2000 << (*((u8 *)val))) - 1;
620 ampdu_len |= BIT(31);
622 rtl_write_dword(rtlpriv,
623 REG_AMPDU_MAX_LENGTH_8812, ampdu_len);
625 case HW_VAR_AC_PARAM:{
626 u8 e_aci = *((u8 *)val);
628 rtl8821ae_dm_init_edca_turbo(hw);
629 if (rtlpci->acm_method != EACMWAY2_SW)
630 rtlpriv->cfg->ops->set_hw_reg(hw,
634 case HW_VAR_ACM_CTRL:{
635 u8 e_aci = *((u8 *)val);
636 union aci_aifsn *p_aci_aifsn =
637 (union aci_aifsn *)(&mac->ac[0].aifs);
638 u8 acm = p_aci_aifsn->f.acm;
639 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
642 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
647 acm_ctrl |= ACMHW_BEQEN;
650 acm_ctrl |= ACMHW_VIQEN;
653 acm_ctrl |= ACMHW_VOQEN;
656 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
657 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
664 acm_ctrl &= (~ACMHW_BEQEN);
667 acm_ctrl &= (~ACMHW_VIQEN);
670 acm_ctrl &= (~ACMHW_VOQEN);
673 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
674 "switch case not process\n");
679 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
680 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
682 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
685 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
686 rtlpci->receive_config = ((u32 *)(val))[0];
688 case HW_VAR_RETRY_LIMIT:{
689 u8 retry_limit = ((u8 *)(val))[0];
691 rtl_write_word(rtlpriv, REG_RL,
692 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
693 retry_limit << RETRY_LIMIT_LONG_SHIFT);
695 case HW_VAR_DUAL_TSF_RST:
696 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
698 case HW_VAR_EFUSE_BYTES:
699 rtlefuse->efuse_usedbytes = *((u16 *)val);
701 case HW_VAR_EFUSE_USAGE:
702 rtlefuse->efuse_usedpercentage = *((u8 *)val);
705 rtl8821ae_phy_set_io_cmd(hw, (*(enum io_type *)val));
707 case HW_VAR_SET_RPWM:{
710 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
713 if (rpwm_val & BIT(7)) {
714 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
717 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
718 ((*(u8 *)val) | BIT(7)));
722 case HW_VAR_H2C_FW_PWRMODE:
723 rtl8821ae_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
725 case HW_VAR_FW_PSMODE_STATUS:
726 ppsc->fw_current_inpsmode = *((bool *)val);
728 case HW_VAR_INIT_RTS_RATE:
730 case HW_VAR_RESUME_CLK_ON:
731 _rtl8821ae_set_fw_ps_rf_on(hw);
733 case HW_VAR_FW_LPS_ACTION:{
734 bool b_enter_fwlps = *((bool *)val);
737 _rtl8821ae_fwlps_enter(hw);
739 _rtl8821ae_fwlps_leave(hw);
741 case HW_VAR_H2C_FW_JOINBSSRPT:{
742 u8 mstatus = (*(u8 *)val);
744 if (mstatus == RT_MEDIA_CONNECT) {
745 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
747 _rtl8821ae_download_rsvd_page(hw, false);
749 rtl8821ae_set_fw_media_status_rpt_cmd(hw, mstatus);
752 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
753 rtl8821ae_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
757 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
759 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
762 case HW_VAR_CORRECT_TSF:{
763 u8 btype_ibss = ((u8 *)(val))[0];
766 _rtl8821ae_stop_tx_beacon(hw);
768 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(3));
770 rtl_write_dword(rtlpriv, REG_TSFTR,
771 (u32)(mac->tsf & 0xffffffff));
772 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
773 (u32)((mac->tsf >> 32) & 0xffffffff));
775 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
778 _rtl8821ae_resume_tx_beacon(hw);
780 case HW_VAR_NAV_UPPER: {
781 u32 us_nav_upper = ((u32)*val);
783 if (us_nav_upper > HAL_92C_NAV_UPPER_UNIT * 0xFF) {
784 RT_TRACE(rtlpriv, COMP_INIT , DBG_WARNING,
785 "The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n",
786 us_nav_upper, HAL_92C_NAV_UPPER_UNIT);
789 rtl_write_byte(rtlpriv, REG_NAV_UPPER,
790 ((u8)((us_nav_upper +
791 HAL_92C_NAV_UPPER_UNIT - 1) /
792 HAL_92C_NAV_UPPER_UNIT)));
794 case HW_VAR_KEEP_ALIVE: {
797 array[1] = *((u8 *)val);
798 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_KEEP_ALIVE_CTRL, 2,
802 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
803 "switch case not process %x\n", variable);
808 static bool _rtl8821ae_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
810 struct rtl_priv *rtlpriv = rtl_priv(hw);
813 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
814 _LLT_OP(_LLT_WRITE_ACCESS);
816 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
819 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
820 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
823 if (count > POLLING_LLT_THRESHOLD) {
824 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
825 "Failed to polling write LLT done at address %d!\n",
835 static bool _rtl8821ae_llt_table_init(struct ieee80211_hw *hw)
837 struct rtl_priv *rtlpriv = rtl_priv(hw);
845 txpktbuf_bndy = 0xF8;
847 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8812AE) {
848 txpktbuf_bndy = 0xFA;
852 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
853 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, MAX_RX_DMA_BUFFER_SIZE - 1);
855 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
857 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
858 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
860 rtl_write_byte(rtlpriv, REG_PBP, 0x31);
861 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
863 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
864 status = _rtl8821ae_llt_write(hw, i, i + 1);
869 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
873 for (i = txpktbuf_bndy; i < maxpage; i++) {
874 status = _rtl8821ae_llt_write(hw, i, (i + 1));
879 status = _rtl8821ae_llt_write(hw, maxpage, txpktbuf_bndy);
883 rtl_write_dword(rtlpriv, REG_RQPN, rqpn);
885 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
890 static void _rtl8821ae_gen_refresh_led_state(struct ieee80211_hw *hw)
892 struct rtl_priv *rtlpriv = rtl_priv(hw);
893 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
894 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
895 struct rtl_led *pled0 = &pcipriv->ledctl.sw_led0;
896 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
898 if (rtlpriv->rtlhal.up_first_time)
901 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
902 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
903 rtl8812ae_sw_led_on(hw, pled0);
905 rtl8821ae_sw_led_on(hw, pled0);
906 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
907 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
908 rtl8812ae_sw_led_on(hw, pled0);
910 rtl8821ae_sw_led_on(hw, pled0);
912 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
913 rtl8812ae_sw_led_off(hw, pled0);
915 rtl8821ae_sw_led_off(hw, pled0);
918 static bool _rtl8821ae_init_mac(struct ieee80211_hw *hw)
920 struct rtl_priv *rtlpriv = rtl_priv(hw);
921 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
922 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
926 bool mac_func_enable = rtlhal->mac_func_enable;
928 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
930 /*Auto Power Down to CHIP-off State*/
931 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
932 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
934 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
935 /* HW Power on sequence*/
936 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
937 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
938 RTL8812_NIC_ENABLE_FLOW)) {
939 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
940 "init 8812 MAC Fail as power on failure\n");
944 /* HW Power on sequence */
945 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_A_MSK,
946 PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
947 RTL8821A_NIC_ENABLE_FLOW)){
948 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
949 "init 8821 MAC Fail as power on failure\n");
954 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
955 rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
957 bytetmp = rtl_read_byte(rtlpriv, REG_CR);
959 rtl_write_byte(rtlpriv, REG_CR, bytetmp);
963 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
966 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
967 bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
968 if (bytetmp & BIT(0)) {
969 bytetmp = rtl_read_byte(rtlpriv, 0x7c);
971 rtl_write_byte(rtlpriv, 0x7c, bytetmp);
975 bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
977 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp);
979 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
981 if (!mac_func_enable) {
982 if (!_rtl8821ae_llt_table_init(hw))
986 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
987 rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
989 /* Enable FW Beamformer Interrupt */
990 bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
991 rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
993 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
996 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
998 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
999 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1000 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
1002 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1003 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1004 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1005 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1006 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1007 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1008 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1009 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1010 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1011 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1012 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1013 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1014 rtl_write_dword(rtlpriv, REG_HQ_DESA,
1015 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1016 rtl_write_dword(rtlpriv, REG_RX_DESA,
1017 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1019 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
1021 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
1023 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0);
1025 rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
1026 _rtl8821ae_gen_refresh_led_state(hw);
1031 static void _rtl8821ae_hw_configure(struct ieee80211_hw *hw)
1033 struct rtl_priv *rtlpriv = rtl_priv(hw);
1034 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1037 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
1039 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
1040 /* ARFB table 9 for 11ac 5G 2SS */
1041 rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
1042 /* ARFB table 10 for 11ac 5G 1SS */
1043 rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
1044 /* ARFB table 11 for 11ac 24G 1SS */
1045 rtl_write_dword(rtlpriv, REG_ARFR2, 0x00000015);
1046 rtl_write_dword(rtlpriv, REG_ARFR2 + 4, 0x003ff000);
1047 /* ARFB table 12 for 11ac 24G 1SS */
1048 rtl_write_dword(rtlpriv, REG_ARFR3, 0x00000015);
1049 rtl_write_dword(rtlpriv, REG_ARFR3 + 4, 0xffcff000);
1050 /* 0x420[7] = 0 , enable retry AMPDU in new AMPD not singal MPDU. */
1051 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
1052 rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
1055 rtl_write_word(rtlpriv, REG_RL, 0x0707);
1057 /* Set Data / Response auto rate fallack retry count*/
1058 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
1059 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
1060 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
1061 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
1063 rtlpci->reg_bcn_ctrl_val = 0x1d;
1064 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
1066 /* TBTT prohibit hold time. Suggested by designer TimChen. */
1067 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1069 /* AGGR_BK_TIME Reg51A 0x16 */
1070 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
1072 /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
1073 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
1075 rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
1076 rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
1077 rtl_write_word(rtlpriv, REG_MAX_AGGR_NUM, 0x1F1F);
1080 static u16 _rtl8821ae_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1083 u8 tmp = 0, count = 0;
1085 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1086 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1088 while (tmp && count < 20) {
1090 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1094 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1099 static void _rtl8821ae_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1101 u8 tmp = 0, count = 0;
1103 rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1104 rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1105 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1107 while (tmp && count < 20) {
1109 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1114 static u8 _rtl8821ae_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
1116 u16 read_addr = addr & 0xfffc;
1117 u8 tmp = 0, count = 0, ret = 0;
1119 rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
1120 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
1121 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1123 while (tmp && count < 20) {
1125 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1129 read_addr = REG_DBI_RDATA + addr % 4;
1130 ret = rtl_read_byte(rtlpriv, read_addr);
1135 static void _rtl8821ae_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1137 u8 tmp = 0, count = 0;
1138 u16 wrtie_addr, remainder = addr % 4;
1140 wrtie_addr = REG_DBI_WDATA + remainder;
1141 rtl_write_byte(rtlpriv, wrtie_addr, data);
1143 wrtie_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1144 rtl_write_word(rtlpriv, REG_DBI_ADDR, wrtie_addr);
1146 rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1148 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1150 while (tmp && count < 20) {
1152 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1157 static void _rtl8821ae_enable_aspm_back_door(struct ieee80211_hw *hw)
1159 struct rtl_priv *rtlpriv = rtl_priv(hw);
1160 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1163 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1164 if (_rtl8821ae_mdio_read(rtlpriv, 0x04) != 0x8544)
1165 _rtl8821ae_mdio_write(rtlpriv, 0x04, 0x8544);
1167 if (_rtl8821ae_mdio_read(rtlpriv, 0x0b) != 0x0070)
1168 _rtl8821ae_mdio_write(rtlpriv, 0x0b, 0x0070);
1171 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x70f);
1172 _rtl8821ae_dbi_write(rtlpriv, 0x70f, tmp | BIT(7) |
1173 ASPM_L1_LATENCY << 3);
1175 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x719);
1176 _rtl8821ae_dbi_write(rtlpriv, 0x719, tmp | BIT(3) | BIT(4));
1178 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1179 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1180 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp|BIT(4));
1184 void rtl8821ae_enable_hw_security_config(struct ieee80211_hw *hw)
1186 struct rtl_priv *rtlpriv = rtl_priv(hw);
1190 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1191 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1192 rtlpriv->sec.pairwise_enc_algorithm,
1193 rtlpriv->sec.group_enc_algorithm);
1195 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1196 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1197 "not open hw encryption\n");
1201 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1203 if (rtlpriv->sec.use_defaultkey) {
1204 sec_reg_value |= SCR_TXUSEDK;
1205 sec_reg_value |= SCR_RXUSEDK;
1208 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1210 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1211 rtl_write_byte(rtlpriv, REG_CR + 1, tmp | BIT(1));
1213 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1214 "The SECR-value %x\n", sec_reg_value);
1216 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1219 /* Static MacID Mapping (cf. Used in MacIdDoStaticMapping) ---------- */
1220 #define MAC_ID_STATIC_FOR_DEFAULT_PORT 0
1221 #define MAC_ID_STATIC_FOR_BROADCAST_MULTICAST 1
1222 #define MAC_ID_STATIC_FOR_BT_CLIENT_START 2
1223 #define MAC_ID_STATIC_FOR_BT_CLIENT_END 3
1224 /* ----------------------------------------------------------- */
1226 static void rtl8821ae_macid_initialize_mediastatus(struct ieee80211_hw *hw)
1228 struct rtl_priv *rtlpriv = rtl_priv(hw);
1229 u8 media_rpt[4] = {RT_MEDIA_CONNECT, 1,
1230 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1231 MAC_ID_STATIC_FOR_BT_CLIENT_END};
1233 rtlpriv->cfg->ops->set_hw_reg(hw,
1234 HW_VAR_H2C_FW_MEDIASTATUSRPT, media_rpt);
1236 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1237 "Initialize MacId media status: from %d to %d\n",
1238 MAC_ID_STATIC_FOR_BROADCAST_MULTICAST,
1239 MAC_ID_STATIC_FOR_BT_CLIENT_END);
1242 static bool _rtl8821ae_check_pcie_dma_hang(struct ieee80211_hw *hw)
1244 struct rtl_priv *rtlpriv = rtl_priv(hw);
1247 /* write reg 0x350 Bit[26]=1. Enable debug port. */
1248 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1249 if (!(tmp & BIT(2))) {
1250 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
1254 /* read reg 0x350 Bit[25] if 1 : RX hang */
1255 /* read reg 0x350 Bit[24] if 1 : TX hang */
1256 tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1257 if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1258 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1259 "CheckPcieDMAHang8821AE(): true! Reset PCIE DMA!\n");
1266 static bool _rtl8821ae_reset_pcie_interface_dma(struct ieee80211_hw *hw,
1270 struct rtl_priv *rtlpriv = rtl_priv(hw);
1271 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1273 bool release_mac_rx_pause;
1274 u8 backup_pcie_dma_pause;
1276 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "\n");
1278 /* 1. Disable register write lock. 0x1c[1] = 0 */
1279 tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1281 rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1282 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1283 /* write 0xCC bit[2] = 1'b1 */
1284 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1286 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1289 /* 2. Check and pause TRX DMA */
1290 /* write 0x284 bit[18] = 1'b1 */
1291 /* write 0x301 = 0xFF */
1292 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1294 /* Already pause before the function for another purpose. */
1295 release_mac_rx_pause = false;
1297 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1298 release_mac_rx_pause = true;
1300 backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1301 if (backup_pcie_dma_pause != 0xFF)
1302 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1305 /* 3. reset TRX function */
1306 /* write 0x100 = 0x00 */
1307 rtl_write_byte(rtlpriv, REG_CR, 0);
1310 /* 4. Reset PCIe DMA. 0x3[0] = 0 */
1311 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1313 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1315 /* 5. Enable PCIe DMA. 0x3[0] = 1 */
1316 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1318 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1321 /* 6. enable TRX function */
1322 /* write 0x100 = 0xFF */
1323 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1325 /* We should init LLT & RQPN and
1326 * prepare Tx/Rx descrptor address later
1327 * because MAC function is reset.*/
1330 /* 7. Restore PCIe autoload down bit */
1331 /* 8812AE does not has the defination. */
1332 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1333 /* write 0xF8 bit[17] = 1'b1 */
1334 tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1336 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1339 /* In MAC power on state, BB and RF maybe in ON state,
1340 * if we release TRx DMA here.
1341 * it will cause packets to be started to Tx/Rx,
1342 * so we release Tx/Rx DMA later.*/
1343 if (!mac_power_on/* || in_watchdog*/) {
1344 /* 8. release TRX DMA */
1345 /* write 0x284 bit[18] = 1'b0 */
1346 /* write 0x301 = 0x00 */
1347 if (release_mac_rx_pause) {
1348 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1349 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1352 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1353 backup_pcie_dma_pause);
1356 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1357 /* 9. lock system register */
1358 /* write 0xCC bit[2] = 1'b0 */
1359 tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1361 rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1366 static void _rtl8821ae_get_wakeup_reason(struct ieee80211_hw *hw)
1368 struct rtl_priv *rtlpriv = rtl_priv(hw);
1369 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1370 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1374 fw_reason = rtl_read_byte(rtlpriv, REG_MCUTST_WOWLAN);
1376 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "WOL Read 0x1c7 = %02X\n",
1379 ppsc->wakeup_reason = 0;
1381 do_gettimeofday(&ts);
1382 rtlhal->last_suspend_sec = ts.tv_sec;
1384 switch (fw_reason) {
1385 case FW_WOW_V2_PTK_UPDATE_EVENT:
1386 ppsc->wakeup_reason = WOL_REASON_PTK_UPDATE;
1387 do_gettimeofday(&ts);
1388 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000;
1389 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1390 "It's a WOL PTK Key update event!\n");
1392 case FW_WOW_V2_GTK_UPDATE_EVENT:
1393 ppsc->wakeup_reason = WOL_REASON_GTK_UPDATE;
1394 do_gettimeofday(&ts);
1395 ppsc->last_wakeup_time = ts.tv_sec*1000 + ts.tv_usec/1000;
1396 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1397 "It's a WOL GTK Key update event!\n");
1399 case FW_WOW_V2_DISASSOC_EVENT:
1400 ppsc->wakeup_reason = WOL_REASON_DISASSOC;
1401 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1402 "It's a disassociation event!\n");
1404 case FW_WOW_V2_DEAUTH_EVENT:
1405 ppsc->wakeup_reason = WOL_REASON_DEAUTH;
1406 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1407 "It's a deauth event!\n");
1409 case FW_WOW_V2_FW_DISCONNECT_EVENT:
1410 ppsc->wakeup_reason = WOL_REASON_AP_LOST;
1411 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1412 "It's a Fw disconnect decision (AP lost) event!\n");
1414 case FW_WOW_V2_MAGIC_PKT_EVENT:
1415 ppsc->wakeup_reason = WOL_REASON_MAGIC_PKT;
1416 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1417 "It's a magic packet event!\n");
1419 case FW_WOW_V2_UNICAST_PKT_EVENT:
1420 ppsc->wakeup_reason = WOL_REASON_UNICAST_PKT;
1421 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1422 "It's an unicast packet event!\n");
1424 case FW_WOW_V2_PATTERN_PKT_EVENT:
1425 ppsc->wakeup_reason = WOL_REASON_PATTERN_PKT;
1426 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1427 "It's a pattern match event!\n");
1429 case FW_WOW_V2_RTD3_SSID_MATCH_EVENT:
1430 ppsc->wakeup_reason = WOL_REASON_RTD3_SSID_MATCH;
1431 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1432 "It's an RTD3 Ssid match event!\n");
1434 case FW_WOW_V2_REALWOW_V2_WAKEUPPKT:
1435 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_WAKEUPPKT;
1436 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1437 "It's an RealWoW wake packet event!\n");
1439 case FW_WOW_V2_REALWOW_V2_ACKLOST:
1440 ppsc->wakeup_reason = WOL_REASON_REALWOW_V2_ACKLOST;
1441 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1442 "It's an RealWoW ack lost event!\n");
1445 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
1446 "WOL Read 0x1c7 = %02X, Unknown reason!\n",
1452 static void _rtl8821ae_init_trx_desc_hw_address(struct ieee80211_hw *hw)
1454 struct rtl_priv *rtlpriv = rtl_priv(hw);
1455 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1458 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
1459 rtlpci->tx_ring[BEACON_QUEUE].dma & DMA_BIT_MASK(32));
1460 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
1461 rtlpci->tx_ring[MGNT_QUEUE].dma & DMA_BIT_MASK(32));
1462 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
1463 rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
1464 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
1465 rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
1466 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
1467 rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
1468 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
1469 rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
1470 rtl_write_dword(rtlpriv, REG_HQ_DESA,
1471 rtlpci->tx_ring[HIGH_QUEUE].dma & DMA_BIT_MASK(32));
1472 rtl_write_dword(rtlpriv, REG_RX_DESA,
1473 rtlpci->rx_ring[RX_MPDU_QUEUE].dma & DMA_BIT_MASK(32));
1476 static bool _rtl8821ae_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
1480 u32 txpktbuf_bndy = boundary;
1481 u32 last_entry_of_txpktbuf = LAST_ENTRY_OF_TX_PKT_BUFFER;
1483 for (i = 0 ; i < (txpktbuf_bndy - 1) ; i++) {
1484 status = _rtl8821ae_llt_write(hw, i , i + 1);
1489 status = _rtl8821ae_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
1493 for (i = txpktbuf_bndy ; i < last_entry_of_txpktbuf ; i++) {
1494 status = _rtl8821ae_llt_write(hw, i, (i + 1));
1499 status = _rtl8821ae_llt_write(hw, last_entry_of_txpktbuf,
1507 static bool _rtl8821ae_dynamic_rqpn(struct ieee80211_hw *hw, u32 boundary,
1508 u16 npq_rqpn_value, u32 rqpn_val)
1510 struct rtl_priv *rtlpriv = rtl_priv(hw);
1513 u16 count = 0, tmp16;
1514 bool support_remote_wakeup;
1516 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1517 (u8 *)(&support_remote_wakeup));
1519 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1520 "boundary=%#X, NPQ_RQPNValue=%#X, RQPNValue=%#X\n",
1521 boundary, npq_rqpn_value, rqpn_val);
1524 * 1. 0x301[7:0] = 0xFE */
1525 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1528 * 2. polling till 0x41A[15:0]=0x07FF */
1529 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1530 while ((tmp16 & 0x07FF) != 0x07FF) {
1532 tmp16 = rtl_read_word(rtlpriv, REG_TXPKT_EMPTY);
1534 if ((count % 200) == 0) {
1535 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1536 "Tx queue is not empty for 20ms!\n");
1538 if (count >= 1000) {
1539 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1540 "Wait for Tx FIFO empty timeout!\n");
1546 * 3. reg 0x522=0xFF */
1547 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1549 /* Wait TX State Machine OK
1550 * 4. polling till reg 0x5FB~0x5F8 = 0x00000000 for 50ms */
1552 while (rtl_read_byte(rtlpriv, REG_SCH_TXCMD) != 0) {
1556 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1557 "Wait for TX State Machine ready timeout !!\n");
1564 * 6. wait till 0x284[17] == 1
1565 * wait RX DMA idle */
1567 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1568 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1570 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1573 } while (!(tmp & BIT(1)) && count < 100);
1575 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1576 "Wait until Rx DMA Idle. count=%d REG[0x286]=0x%x\n",
1580 * 7. 0x02 [0] = 0 */
1581 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1583 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmp);
1588 rtl_write_byte(rtlpriv, REG_CR, 0x00);
1591 /* Disable MAC Security Engine
1592 * 9. 0x100 bit[9]=0 */
1593 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1595 rtl_write_byte(rtlpriv, REG_CR + 1, tmp);
1597 /* To avoid DD-Tim Circuit hang
1598 * 10. 0x553 bit[5]=1 */
1599 tmp = rtl_read_byte(rtlpriv, REG_DUAL_TSF_RST);
1600 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (tmp | BIT(5)));
1602 /* Enable MAC Security Engine
1603 * 11. 0x100 bit[9]=1 */
1604 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1605 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp | BIT(1)));
1610 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1614 * 13. 0x02 [0] = 1 */
1615 tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
1616 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, (tmp | BIT(0)));
1619 * 14,15. set beacon head page (reg 0x209 and 0x424) */
1620 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, (u8)boundary);
1621 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, (u8)boundary);
1622 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, (u8)boundary);
1624 /* 16. WMAC_LBK_BF_HD 0x45D[7:0]
1626 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD,
1629 rtl_write_word(rtlpriv, REG_TRXFF_BNDY, boundary);
1633 if (!_rtl8821ae_init_llt_table(hw, boundary)) {
1634 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
1635 "Failed to init LLT table!\n");
1640 * 18. reallocate RQPN and init LLT */
1641 rtl_write_word(rtlpriv, REG_RQPN_NPQ, npq_rqpn_value);
1642 rtl_write_dword(rtlpriv, REG_RQPN, rqpn_val);
1646 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1649 * 20. 0x301[7:0] = 0x00
1650 * 21. 0x284[18] = 0 */
1651 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1652 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1653 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp&~BIT(2)));
1655 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "End.\n");
1659 static void _rtl8821ae_simple_initialize_adapter(struct ieee80211_hw *hw)
1661 struct rtl_priv *rtlpriv = rtl_priv(hw);
1662 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1663 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
1665 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
1666 /* Re-download normal Fw. */
1667 rtl8821ae_set_fw_related_for_wowlan(hw, false);
1670 /* Re-Initialize LLT table. */
1671 if (rtlhal->re_init_llt_table) {
1672 u32 rqpn = 0x80e70808;
1673 u8 rqpn_npq = 0, boundary = 0xF8;
1674 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
1678 if (_rtl8821ae_dynamic_rqpn(hw, boundary, rqpn_npq, rqpn))
1679 rtlhal->re_init_llt_table = false;
1682 ppsc->rfpwr_state = ERFON;
1685 static void _rtl8821ae_enable_l1off(struct ieee80211_hw *hw)
1688 struct rtl_priv *rtlpriv = rtl_priv(hw);
1690 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1692 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x160);
1693 if (!(tmp & (BIT(2) | BIT(3)))) {
1694 RT_TRACE(rtlpriv, COMP_POWER | COMP_INIT, DBG_LOUD,
1695 "0x160(%#x)return!!\n", tmp);
1699 tmp = _rtl8821ae_mdio_read(rtlpriv, 0x1b);
1700 _rtl8821ae_mdio_write(rtlpriv, 0x1b, (tmp | BIT(4)));
1702 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x718);
1703 _rtl8821ae_dbi_write(rtlpriv, 0x718, tmp | BIT(5));
1705 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1708 static void _rtl8821ae_enable_ltr(struct ieee80211_hw *hw)
1711 struct rtl_priv *rtlpriv = rtl_priv(hw);
1713 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "--->\n");
1715 /* Check 0x98[10] */
1716 tmp = _rtl8821ae_dbi_read(rtlpriv, 0x99);
1717 if (!(tmp & BIT(2))) {
1718 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1719 "<---0x99(%#x) return!!\n", tmp);
1723 /* LTR idle latency, 0x90 for 144us */
1724 rtl_write_dword(rtlpriv, 0x798, 0x88908890);
1726 /* LTR active latency, 0x3c for 60us */
1727 rtl_write_dword(rtlpriv, 0x79c, 0x883c883c);
1729 tmp = rtl_read_byte(rtlpriv, 0x7a4);
1730 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(4)));
1732 tmp = rtl_read_byte(rtlpriv, 0x7a4);
1733 rtl_write_byte(rtlpriv, 0x7a4, (tmp & (~BIT(0))));
1734 rtl_write_byte(rtlpriv, 0x7a4, (tmp | BIT(0)));
1736 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<---\n");
1739 static bool _rtl8821ae_wowlan_initialize_adapter(struct ieee80211_hw *hw)
1741 struct rtl_priv *rtlpriv = rtl_priv(hw);
1742 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1743 bool init_finished = true;
1746 /* Get Fw wake up reason. */
1747 _rtl8821ae_get_wakeup_reason(hw);
1749 /* Patch Pcie Rx DMA hang after S3/S4 several times.
1750 * The root cause has not be found. */
1751 if (_rtl8821ae_check_pcie_dma_hang(hw))
1752 _rtl8821ae_reset_pcie_interface_dma(hw, true, false);
1754 /* Prepare Tx/Rx Desc Hw address. */
1755 _rtl8821ae_init_trx_desc_hw_address(hw);
1757 /* Release Pcie Interface Rx DMA to allow wake packet DMA. */
1758 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1759 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Enable PCIE Rx DMA.\n");
1761 /* Check wake up event.
1762 * We should check wake packet bit before disable wowlan by H2C or
1763 * Fw will clear the bit. */
1764 tmp = rtl_read_byte(rtlpriv, REG_FTISR + 3);
1765 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
1766 "Read REG_FTISR 0x13f = %#X\n", tmp);
1768 /* Set the WoWLAN related function control disable. */
1769 rtl8821ae_set_fw_wowlan_mode(hw, false);
1770 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 0);
1772 if (rtlhal->hw_rof_enable) {
1773 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
1775 /* Clear GPIO9 ISR */
1776 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
1777 init_finished = false;
1779 init_finished = true;
1783 if (init_finished) {
1784 _rtl8821ae_simple_initialize_adapter(hw);
1786 /* Release Pcie Interface Tx DMA. */
1787 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x00);
1788 /* Release Pcie RX DMA */
1789 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, 0x02);
1791 tmp = rtl_read_byte(rtlpriv, REG_CR + 1);
1792 rtl_write_byte(rtlpriv, REG_CR + 1, (tmp & (~BIT(0))));
1794 _rtl8821ae_enable_l1off(hw);
1795 _rtl8821ae_enable_ltr(hw);
1798 return init_finished;
1801 static void _rtl8812ae_bb8812_config_1t(struct ieee80211_hw *hw)
1803 /* BB OFDM RX Path_A */
1804 rtl_set_bbreg(hw, 0x808, 0xff, 0x11);
1805 /* BB OFDM TX Path_A */
1806 rtl_set_bbreg(hw, 0x80c, MASKLWORD, 0x1111);
1807 /* BB CCK R/Rx Path_A */
1808 rtl_set_bbreg(hw, 0xa04, 0x0c000000, 0x0);
1810 rtl_set_bbreg(hw, 0x8bc, 0xc0000060, 0x4);
1811 /* RF Path_B HSSI OFF */
1812 rtl_set_bbreg(hw, 0xe00, 0xf, 0x4);
1813 /* RF Path_B Power Down */
1814 rtl_set_bbreg(hw, 0xe90, MASKDWORD, 0);
1815 /* ADDA Path_B OFF */
1816 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0);
1817 rtl_set_bbreg(hw, 0xe64, MASKDWORD, 0);
1820 static void _rtl8821ae_poweroff_adapter(struct ieee80211_hw *hw)
1822 struct rtl_priv *rtlpriv = rtl_priv(hw);
1823 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1826 rtlhal->mac_func_enable = false;
1828 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1829 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1830 /* 1. Run LPS WL RFOFF flow */
1831 /* RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1832 "=====>CardDisableRTL8812E,RTL8821A_NIC_LPS_ENTER_FLOW\n");
1834 rtl_hal_pwrseqcmdparsing(rtlpriv,
1835 PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1836 PWR_INTF_PCI_MSK, RTL8821A_NIC_LPS_ENTER_FLOW);
1838 /* 2. 0x1F[7:0] = 0 */
1840 /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
1841 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1843 rtl8821ae_firmware_selfreset(hw);
1846 /* Reset MCU. Suggested by Filen. */
1847 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1848 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
1850 /* g. MCUFWDL 0x80[1:0]=0 */
1851 /* reset MCU ready status */
1852 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1854 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
1855 /* HW card disable configuration. */
1856 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1857 PWR_INTF_PCI_MSK, RTL8821A_NIC_DISABLE_FLOW);
1859 /* HW card disable configuration. */
1860 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1861 PWR_INTF_PCI_MSK, RTL8812_NIC_DISABLE_FLOW);
1864 /* Reset MCU IO Wrapper */
1865 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1866 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1867 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1868 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1870 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1871 /* lock ISO/CLK/Power control register */
1872 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1875 int rtl8821ae_hw_init(struct ieee80211_hw *hw)
1877 struct rtl_priv *rtlpriv = rtl_priv(hw);
1878 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1879 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1880 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1881 bool rtstatus = true;
1884 bool support_remote_wakeup;
1885 u32 nav_upper = WIFI_NAV_UPPER_US;
1887 rtlhal->being_init_adapter = true;
1888 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
1889 (u8 *)(&support_remote_wakeup));
1890 rtlpriv->intf_ops->disable_aspm(hw);
1892 /*YP wowlan not considered*/
1894 tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1895 if (tmp_u1b != 0 && tmp_u1b != 0xEA) {
1896 rtlhal->mac_func_enable = true;
1897 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1898 "MAC has already power on.\n");
1900 rtlhal->mac_func_enable = false;
1901 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1904 if (support_remote_wakeup &&
1905 rtlhal->wake_from_pnp_sleep &&
1906 rtlhal->mac_func_enable) {
1907 if (_rtl8821ae_wowlan_initialize_adapter(hw)) {
1908 rtlhal->being_init_adapter = false;
1913 if (_rtl8821ae_check_pcie_dma_hang(hw)) {
1914 _rtl8821ae_reset_pcie_interface_dma(hw,
1915 rtlhal->mac_func_enable,
1917 rtlhal->mac_func_enable = false;
1920 /* Reset MAC/BB/RF status if it is not powered off
1921 * before calling initialize Hw flow to prevent
1922 * from interface and MAC status mismatch.
1923 * 2013.06.21, by tynli. Suggested by SD1 JackieLau. */
1924 if (rtlhal->mac_func_enable) {
1925 _rtl8821ae_poweroff_adapter(hw);
1926 rtlhal->mac_func_enable = false;
1929 rtstatus = _rtl8821ae_init_mac(hw);
1930 if (rtstatus != true) {
1931 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1936 tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1938 rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b);
1940 err = rtl8821ae_download_fw(hw, false);
1942 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1943 "Failed to download FW. Init HW without FW now\n");
1945 rtlhal->fw_ready = false;
1948 rtlhal->fw_ready = true;
1950 ppsc->fw_current_inpsmode = false;
1951 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_8821AE;
1952 rtlhal->fw_clk_change_in_progress = false;
1953 rtlhal->allow_sw_to_change_hwclc = false;
1954 rtlhal->last_hmeboxnum = 0;
1956 /*SIC_Init(Adapter);
1957 if(rtlhal->AMPDUBurstMode)
1958 rtl_write_byte(rtlpriv,REG_AMPDU_BURST_MODE_8812, 0x7F);*/
1960 rtl8821ae_phy_mac_config(hw);
1961 /* because last function modify RCR, so we update
1962 * rcr var here, or TP will unstable for receive_config
1963 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1964 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1965 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1966 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1967 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);*/
1968 rtl8821ae_phy_bb_config(hw);
1970 rtl8821ae_phy_rf_config(hw);
1972 if (rtlpriv->phy.rf_type == RF_1T1R &&
1973 rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
1974 _rtl8812ae_bb8812_config_1t(hw);
1976 _rtl8821ae_hw_configure(hw);
1978 rtl8821ae_phy_switch_wirelessband(hw, BAND_ON_2_4G);
1980 /*set wireless mode*/
1982 rtlhal->mac_func_enable = true;
1984 rtl_cam_reset_all_entry(hw);
1986 rtl8821ae_enable_hw_security_config(hw);
1988 ppsc->rfpwr_state = ERFON;
1990 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1991 _rtl8821ae_enable_aspm_back_door(hw);
1992 rtlpriv->intf_ops->enable_aspm(hw);
1994 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE &&
1995 (rtlhal->rfe_type == 1 || rtlhal->rfe_type == 5))
1996 rtl_set_bbreg(hw, 0x900, 0x00000303, 0x0302);
1998 rtl8821ae_bt_hw_init(hw);
1999 rtlpriv->rtlhal.being_init_adapter = false;
2001 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_NAV_UPPER, (u8 *)&nav_upper);
2003 /* rtl8821ae_dm_check_txpower_tracking(hw); */
2004 /* rtl8821ae_phy_lc_calibrate(hw); */
2005 if (support_remote_wakeup)
2006 rtl_write_byte(rtlpriv, REG_WOW_CTRL, 0);
2009 tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2010 if (tmp_u1b & BIT(2)) {
2011 /* Release Rx DMA if needed*/
2013 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
2016 /* Release Tx/Rx PCIE DMA if*/
2017 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
2019 rtl8821ae_dm_init(hw);
2020 rtl8821ae_macid_initialize_mediastatus(hw);
2022 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_hw_init() <====\n");
2026 static enum version_8821ae _rtl8821ae_read_chip_version(struct ieee80211_hw *hw)
2028 struct rtl_priv *rtlpriv = rtl_priv(hw);
2029 struct rtl_phy *rtlphy = &rtlpriv->phy;
2030 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2031 enum version_8821ae version = VERSION_UNKNOWN;
2034 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
2035 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2036 "ReadChipVersion8812A 0xF0 = 0x%x\n", value32);
2038 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
2039 rtlphy->rf_type = RF_2T2R;
2040 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE)
2041 rtlphy->rf_type = RF_1T1R;
2043 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2044 "RF_Type is %x!!\n", rtlphy->rf_type);
2046 if (value32 & TRP_VAUX_EN) {
2047 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2048 if (rtlphy->rf_type == RF_2T2R)
2049 version = VERSION_TEST_CHIP_2T2R_8812;
2051 version = VERSION_TEST_CHIP_1T1R_8812;
2053 version = VERSION_TEST_CHIP_8821;
2055 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
2056 u32 rtl_id = ((value32 & CHIP_VER_RTL_MASK) >> 12) + 1;
2058 if (rtlphy->rf_type == RF_2T2R)
2060 (enum version_8821ae)(CHIP_8812
2064 version = (enum version_8821ae)(CHIP_8812
2067 version = (enum version_8821ae)(version | (rtl_id << 12));
2068 } else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2069 u32 rtl_id = value32 & CHIP_VER_RTL_MASK;
2071 version = (enum version_8821ae)(CHIP_8821
2072 | NORMAL_CHIP | rtl_id);
2076 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8821AE) {
2078 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2079 rtlhal->hw_rof_enable = ((value32 & WL_HWROF_EN) ? 1 : 0);
2083 case VERSION_TEST_CHIP_1T1R_8812:
2084 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2085 "Chip Version ID: VERSION_TEST_CHIP_1T1R_8812\n");
2087 case VERSION_TEST_CHIP_2T2R_8812:
2088 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2089 "Chip Version ID: VERSION_TEST_CHIP_2T2R_8812\n");
2091 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812:
2092 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2093 "Chip Version ID:VERSION_NORMAL_TSMC_CHIP_1T1R_8812\n");
2095 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812:
2096 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2097 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812\n");
2099 case VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT:
2100 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2101 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_1T1R_8812 C CUT\n");
2103 case VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT:
2104 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2105 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_2T2R_8812 C CUT\n");
2107 case VERSION_TEST_CHIP_8821:
2108 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2109 "Chip Version ID: VERSION_TEST_CHIP_8821\n");
2111 case VERSION_NORMAL_TSMC_CHIP_8821:
2112 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2113 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 A CUT\n");
2115 case VERSION_NORMAL_TSMC_CHIP_8821_B_CUT:
2116 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2117 "Chip Version ID: VERSION_NORMAL_TSMC_CHIP_8821 B CUT\n");
2120 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2121 "Chip Version ID: Unknow (0x%X)\n", version);
2128 static int _rtl8821ae_set_media_status(struct ieee80211_hw *hw,
2129 enum nl80211_iftype type)
2131 struct rtl_priv *rtlpriv = rtl_priv(hw);
2132 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
2133 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
2136 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
2137 RT_TRACE(rtlpriv, COMP_BEACON, DBG_LOUD,
2138 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
2140 if (type == NL80211_IFTYPE_UNSPECIFIED ||
2141 type == NL80211_IFTYPE_STATION) {
2142 _rtl8821ae_stop_tx_beacon(hw);
2143 _rtl8821ae_enable_bcn_sub_func(hw);
2144 } else if (type == NL80211_IFTYPE_ADHOC ||
2145 type == NL80211_IFTYPE_AP) {
2146 _rtl8821ae_resume_tx_beacon(hw);
2147 _rtl8821ae_disable_bcn_sub_func(hw);
2149 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2150 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
2155 case NL80211_IFTYPE_UNSPECIFIED:
2156 bt_msr |= MSR_NOLINK;
2157 ledaction = LED_CTL_LINK;
2158 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2159 "Set Network type to NO LINK!\n");
2161 case NL80211_IFTYPE_ADHOC:
2162 bt_msr |= MSR_ADHOC;
2163 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2164 "Set Network type to Ad Hoc!\n");
2166 case NL80211_IFTYPE_STATION:
2167 bt_msr |= MSR_INFRA;
2168 ledaction = LED_CTL_LINK;
2169 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2170 "Set Network type to STA!\n");
2172 case NL80211_IFTYPE_AP:
2174 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
2175 "Set Network type to AP!\n");
2178 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2179 "Network type %d not support!\n", type);
2183 rtl_write_byte(rtlpriv, MSR, bt_msr);
2184 rtlpriv->cfg->ops->led_control(hw, ledaction);
2185 if ((bt_msr & MSR_MASK) == MSR_AP)
2186 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
2188 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
2193 void rtl8821ae_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
2195 struct rtl_priv *rtlpriv = rtl_priv(hw);
2196 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2197 u32 reg_rcr = rtlpci->receive_config;
2199 if (rtlpriv->psc.rfpwr_state != ERFON)
2203 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
2204 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
2206 _rtl8821ae_set_bcn_ctrl_reg(hw, 0, BIT(4));
2207 } else if (!check_bssid) {
2208 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
2209 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(4), 0);
2210 rtlpriv->cfg->ops->set_hw_reg(hw,
2211 HW_VAR_RCR, (u8 *)(®_rcr));
2215 int rtl8821ae_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
2217 struct rtl_priv *rtlpriv = rtl_priv(hw);
2219 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rtl8821ae_set_network_type!\n");
2221 if (_rtl8821ae_set_media_status(hw, type))
2224 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
2225 if (type != NL80211_IFTYPE_AP)
2226 rtl8821ae_set_check_bssid(hw, true);
2228 rtl8821ae_set_check_bssid(hw, false);
2234 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
2235 void rtl8821ae_set_qos(struct ieee80211_hw *hw, int aci)
2237 struct rtl_priv *rtlpriv = rtl_priv(hw);
2238 rtl8821ae_dm_init_edca_turbo(hw);
2241 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
2244 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
2247 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
2250 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
2253 RT_ASSERT(false, "invalid aci: %d !\n", aci);
2258 static void rtl8821ae_clear_interrupt(struct ieee80211_hw *hw)
2260 struct rtl_priv *rtlpriv = rtl_priv(hw);
2261 u32 tmp = rtl_read_dword(rtlpriv, REG_HISR);
2263 rtl_write_dword(rtlpriv, REG_HISR, tmp);
2265 tmp = rtl_read_dword(rtlpriv, REG_HISRE);
2266 rtl_write_dword(rtlpriv, REG_HISRE, tmp);
2268 tmp = rtl_read_dword(rtlpriv, REG_HSISR);
2269 rtl_write_dword(rtlpriv, REG_HSISR, tmp);
2272 void rtl8821ae_enable_interrupt(struct ieee80211_hw *hw)
2274 struct rtl_priv *rtlpriv = rtl_priv(hw);
2275 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2277 if (rtlpci->int_clear)
2278 rtl8821ae_clear_interrupt(hw);/*clear it here first*/
2280 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
2281 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
2282 rtlpci->irq_enabled = true;
2283 /* there are some C2H CMDs have been sent before
2284 system interrupt is enabled, e.g., C2H, CPWM.
2285 *So we need to clear all C2H events that FW has
2286 notified, otherwise FW won't schedule any commands anymore.
2288 /* rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0); */
2289 /*enable system interrupt*/
2290 rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
2293 void rtl8821ae_disable_interrupt(struct ieee80211_hw *hw)
2295 struct rtl_priv *rtlpriv = rtl_priv(hw);
2296 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2298 rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
2299 rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
2300 rtlpci->irq_enabled = false;
2301 /*synchronize_irq(rtlpci->pdev->irq);*/
2304 static void _rtl8821ae_clear_pci_pme_status(struct ieee80211_hw *hw)
2306 struct rtl_priv *rtlpriv = rtl_priv(hw);
2307 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2314 /* Get the Capability pointer first,
2315 * the Capability Pointer is located at
2316 * offset 0x34 from the Function Header */
2318 pci_read_config_byte(rtlpci->pdev, 0x34, &cap_pointer);
2319 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2320 "PCI configration 0x34 = 0x%2x\n", cap_pointer);
2323 pci_read_config_word(rtlpci->pdev, cap_pointer, &cap_hdr);
2324 cap_id = cap_hdr & 0xFF;
2326 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2327 "in pci configration, cap_pointer%x = %x\n",
2328 cap_pointer, cap_id);
2330 if (cap_id == 0x01) {
2333 /* point to next Capability */
2334 cap_pointer = (cap_hdr >> 8) & 0xFF;
2335 /* 0: end of pci capability, 0xff: invalid value */
2336 if (cap_pointer == 0x00 || cap_pointer == 0xff) {
2341 } while (cnt++ < 200);
2343 if (cap_id == 0x01) {
2344 /* Get the PM CSR (Control/Status Register),
2345 * The PME_Status is located at PM Capatibility offset 5, bit 7
2347 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5, &pmcs_reg);
2349 if (pmcs_reg & BIT(7)) {
2350 /* PME event occured, clear the PM_Status by write 1 */
2351 pmcs_reg = pmcs_reg | BIT(7);
2353 pci_write_config_byte(rtlpci->pdev, cap_pointer + 5,
2355 /* Read it back to check */
2356 pci_read_config_byte(rtlpci->pdev, cap_pointer + 5,
2358 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2359 "Clear PME status 0x%2x to 0x%2x\n",
2360 cap_pointer + 5, pmcs_reg);
2362 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2363 "PME status(0x%2x) = 0x%2x\n",
2364 cap_pointer + 5, pmcs_reg);
2367 RT_TRACE(rtlpriv, COMP_INIT, DBG_WARNING,
2368 "Cannot find PME Capability\n");
2372 void rtl8821ae_card_disable(struct ieee80211_hw *hw)
2374 struct rtl_priv *rtlpriv = rtl_priv(hw);
2375 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2376 struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
2377 struct rtl_mac *mac = rtl_mac(rtlpriv);
2378 enum nl80211_iftype opmode;
2379 bool support_remote_wakeup;
2383 rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
2384 (u8 *)(&support_remote_wakeup));
2386 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2388 if (!(support_remote_wakeup && mac->opmode == NL80211_IFTYPE_STATION)
2389 || !rtlhal->enter_pnp_sleep) {
2390 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Normal Power off\n");
2391 mac->link_state = MAC80211_NOLINK;
2392 opmode = NL80211_IFTYPE_UNSPECIFIED;
2393 _rtl8821ae_set_media_status(hw, opmode);
2394 _rtl8821ae_poweroff_adapter(hw);
2396 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Wowlan Supported.\n");
2397 /* 3 <1> Prepare for configuring wowlan related infomations */
2398 /* Clear Fw WoWLAN event. */
2399 rtl_write_byte(rtlpriv, REG_MCUTST_WOWLAN, 0x0);
2401 #if (USE_SPECIFIC_FW_TO_SUPPORT_WOWLAN == 1)
2402 rtl8821ae_set_fw_related_for_wowlan(hw, true);
2404 /* Dynamically adjust Tx packet boundary
2405 * for download reserved page packet.
2406 * reserve 30 pages for rsvd page */
2407 if (_rtl8821ae_dynamic_rqpn(hw, 0xE0, 0x3, 0x80c20d0d))
2408 rtlhal->re_init_llt_table = true;
2410 /* 3 <2> Set Fw releted H2C cmd. */
2412 /* Set WoWLAN related security information. */
2413 rtl8821ae_set_fw_global_info_cmd(hw);
2415 _rtl8821ae_download_rsvd_page(hw, true);
2417 /* Just enable AOAC related functions when we connect to AP. */
2418 printk("mac->link_state = %d\n", mac->link_state);
2419 if (mac->link_state >= MAC80211_LINKED &&
2420 mac->opmode == NL80211_IFTYPE_STATION) {
2421 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
2422 rtl8821ae_set_fw_media_status_rpt_cmd(hw,
2425 rtl8821ae_set_fw_wowlan_mode(hw, true);
2426 /* Enable Fw Keep alive mechanism. */
2427 rtl8821ae_set_fw_keep_alive_cmd(hw, true);
2429 /* Enable disconnect decision control. */
2430 rtl8821ae_set_fw_disconnect_decision_ctrl_cmd(hw, true);
2433 /* 3 <3> Hw Configutations */
2435 /* Wait untill Rx DMA Finished before host sleep.
2436 * FW Pause Rx DMA may happens when received packet doing dma.
2438 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, BIT(2));
2440 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2442 while (!(tmp & BIT(1)) && (count++ < 100)) {
2444 tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
2446 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2447 "Wait Rx DMA Finished before host sleep. count=%d\n",
2450 /* reset trx ring */
2451 rtlpriv->intf_ops->reset_trx_ring(hw);
2453 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x0);
2455 _rtl8821ae_clear_pci_pme_status(hw);
2456 tmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
2457 rtl_write_byte(rtlpriv, REG_SYS_CLKR, tmp | BIT(3));
2458 /* prevent 8051 to be reset by PERST */
2459 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x20);
2460 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x60);
2463 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
2464 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
2465 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
2466 /* For wowlan+LPS+32k. */
2467 if (support_remote_wakeup && rtlhal->enter_pnp_sleep) {
2468 /* Set the WoWLAN related function control enable.
2469 * It should be the last H2C cmd in the WoWLAN flow. */
2470 rtl8821ae_set_fw_remote_wake_ctrl_cmd(hw, 1);
2472 /* Stop Pcie Interface Tx DMA. */
2473 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
2474 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "Stop PCIE Tx DMA.\n");
2476 /* Wait for TxDMA idle. */
2479 tmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG);
2482 } while ((tmp != 0) && (count < 100));
2483 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2484 "Wait Tx DMA Finished before host sleep. count=%d\n",
2487 if (rtlhal->hw_rof_enable) {
2488 printk("hw_rof_enable\n");
2489 tmp = rtl_read_byte(rtlpriv, REG_HSISR + 3);
2490 rtl_write_byte(rtlpriv, REG_HSISR + 3, tmp | BIT(1));
2493 /* after power off we should do iqk again */
2494 rtlpriv->phy.iqk_initialized = false;
2497 void rtl8821ae_interrupt_recognized(struct ieee80211_hw *hw,
2498 u32 *p_inta, u32 *p_intb)
2500 struct rtl_priv *rtlpriv = rtl_priv(hw);
2501 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2503 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
2504 rtl_write_dword(rtlpriv, ISR, *p_inta);
2506 *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
2507 rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
2510 void rtl8821ae_set_beacon_related_registers(struct ieee80211_hw *hw)
2512 struct rtl_priv *rtlpriv = rtl_priv(hw);
2513 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2514 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2515 u16 bcn_interval, atim_window;
2517 bcn_interval = mac->beacon_interval;
2518 atim_window = 2; /*FIX MERGE */
2519 rtl8821ae_disable_interrupt(hw);
2520 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
2521 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2522 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
2523 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
2524 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
2525 rtl_write_byte(rtlpriv, 0x606, 0x30);
2526 rtlpci->reg_bcn_ctrl_val |= BIT(3);
2527 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
2528 rtl8821ae_enable_interrupt(hw);
2531 void rtl8821ae_set_beacon_interval(struct ieee80211_hw *hw)
2533 struct rtl_priv *rtlpriv = rtl_priv(hw);
2534 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2535 u16 bcn_interval = mac->beacon_interval;
2537 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
2538 "beacon_interval:%d\n", bcn_interval);
2539 rtl8821ae_disable_interrupt(hw);
2540 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
2541 rtl8821ae_enable_interrupt(hw);
2544 void rtl8821ae_update_interrupt_mask(struct ieee80211_hw *hw,
2545 u32 add_msr, u32 rm_msr)
2547 struct rtl_priv *rtlpriv = rtl_priv(hw);
2548 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2550 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
2551 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
2554 rtlpci->irq_mask[0] |= add_msr;
2556 rtlpci->irq_mask[0] &= (~rm_msr);
2557 rtl8821ae_disable_interrupt(hw);
2558 rtl8821ae_enable_interrupt(hw);
2561 static u8 _rtl8821ae_get_chnl_group(u8 chnl)
2566 if (1 <= chnl && chnl <= 2)
2568 else if (3 <= chnl && chnl <= 5)
2570 else if (6 <= chnl && chnl <= 8)
2572 else if (9 <= chnl && chnl <= 11)
2574 else /*if (12 <= chnl && chnl <= 14)*/
2577 if (36 <= chnl && chnl <= 42)
2579 else if (44 <= chnl && chnl <= 48)
2581 else if (50 <= chnl && chnl <= 58)
2583 else if (60 <= chnl && chnl <= 64)
2585 else if (100 <= chnl && chnl <= 106)
2587 else if (108 <= chnl && chnl <= 114)
2589 else if (116 <= chnl && chnl <= 122)
2591 else if (124 <= chnl && chnl <= 130)
2593 else if (132 <= chnl && chnl <= 138)
2595 else if (140 <= chnl && chnl <= 144)
2597 else if (149 <= chnl && chnl <= 155)
2599 else if (157 <= chnl && chnl <= 161)
2601 else if (165 <= chnl && chnl <= 171)
2603 else if (173 <= chnl && chnl <= 177)
2606 /*RT_TRACE(rtlpriv, COMP_EFUSE,DBG_LOUD,
2607 "5G, Channel %d in Group not found\n",chnl);*/
2608 RT_ASSERT(!COMP_EFUSE,
2609 "5G, Channel %d in Group not found\n", chnl);
2614 static void _rtl8821ae_read_power_value_fromprom(struct ieee80211_hw *hw,
2615 struct txpower_info_2g *pwrinfo24g,
2616 struct txpower_info_5g *pwrinfo5g,
2620 struct rtl_priv *rtlpriv = rtl_priv(hw);
2621 u32 rfPath, eeAddr = EEPROM_TX_PWR_INX, group, TxCount = 0;
2623 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2624 "hal_ReadPowerValueFromPROM8821ae(): hwinfo[0x%x]=0x%x\n",
2625 (eeAddr+1), hwinfo[eeAddr+1]);
2626 if (0xFF == hwinfo[eeAddr+1]) /*YJ,add,120316*/
2627 autoload_fail = true;
2629 if (autoload_fail) {
2630 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2631 "auto load fail : Use Default value!\n");
2632 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2633 /*2.4G default value*/
2634 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2635 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D;
2636 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2638 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2640 pwrinfo24g->bw20_diff[rfPath][0] = 0x02;
2641 pwrinfo24g->ofdm_diff[rfPath][0] = 0x04;
2643 pwrinfo24g->bw20_diff[rfPath][TxCount] = 0xFE;
2644 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0xFE;
2645 pwrinfo24g->cck_diff[rfPath][TxCount] = 0xFE;
2646 pwrinfo24g->ofdm_diff[rfPath][TxCount] = 0xFE;
2649 /*5G default value*/
2650 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++)
2651 pwrinfo5g->index_bw40_base[rfPath][group] = 0x2A;
2653 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2655 pwrinfo5g->ofdm_diff[rfPath][0] = 0x04;
2656 pwrinfo5g->bw20_diff[rfPath][0] = 0x00;
2657 pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2658 pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2660 pwrinfo5g->ofdm_diff[rfPath][0] = 0xFE;
2661 pwrinfo5g->bw20_diff[rfPath][0] = 0xFE;
2662 pwrinfo5g->bw40_diff[rfPath][0] = 0xFE;
2663 pwrinfo5g->bw80_diff[rfPath][0] = 0xFE;
2664 pwrinfo5g->bw160_diff[rfPath][0] = 0xFE;
2671 rtl_priv(hw)->efuse.txpwr_fromeprom = true;
2673 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) {
2674 /*2.4G default value*/
2675 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
2676 pwrinfo24g->index_cck_base[rfPath][group] = hwinfo[eeAddr++];
2677 if (pwrinfo24g->index_cck_base[rfPath][group] == 0xFF)
2678 pwrinfo24g->index_cck_base[rfPath][group] = 0x2D;
2680 for (group = 0 ; group < MAX_CHNL_GROUP_24G - 1; group++) {
2681 pwrinfo24g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2682 if (pwrinfo24g->index_bw40_base[rfPath][group] == 0xFF)
2683 pwrinfo24g->index_bw40_base[rfPath][group] = 0x2D;
2685 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2687 pwrinfo24g->bw40_diff[rfPath][TxCount] = 0;
2688 /*bit sign number to 8 bit sign number*/
2689 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2690 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2691 pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2692 /*bit sign number to 8 bit sign number*/
2693 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2694 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2695 pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2697 pwrinfo24g->cck_diff[rfPath][TxCount] = 0;
2700 pwrinfo24g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr]&0xf0) >> 4;
2701 if (pwrinfo24g->bw40_diff[rfPath][TxCount] & BIT(3))
2702 pwrinfo24g->bw40_diff[rfPath][TxCount] |= 0xF0;
2704 pwrinfo24g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2705 if (pwrinfo24g->bw20_diff[rfPath][TxCount] & BIT(3))
2706 pwrinfo24g->bw20_diff[rfPath][TxCount] |= 0xF0;
2710 pwrinfo24g->ofdm_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2711 if (pwrinfo24g->ofdm_diff[rfPath][TxCount] & BIT(3))
2712 pwrinfo24g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2714 pwrinfo24g->cck_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2715 if (pwrinfo24g->cck_diff[rfPath][TxCount] & BIT(3))
2716 pwrinfo24g->cck_diff[rfPath][TxCount] |= 0xF0;
2722 /*5G default value*/
2723 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
2724 pwrinfo5g->index_bw40_base[rfPath][group] = hwinfo[eeAddr++];
2725 if (pwrinfo5g->index_bw40_base[rfPath][group] == 0xFF)
2726 pwrinfo5g->index_bw40_base[rfPath][group] = 0xFE;
2729 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2731 pwrinfo5g->bw40_diff[rfPath][TxCount] = 0;
2733 pwrinfo5g->bw20_diff[rfPath][0] = (hwinfo[eeAddr] & 0xf0) >> 4;
2734 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2735 pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2737 pwrinfo5g->ofdm_diff[rfPath][0] = (hwinfo[eeAddr] & 0x0f);
2738 if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2739 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2743 pwrinfo5g->bw40_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2744 if (pwrinfo5g->bw40_diff[rfPath][TxCount] & BIT(3))
2745 pwrinfo5g->bw40_diff[rfPath][TxCount] |= 0xF0;
2747 pwrinfo5g->bw20_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2748 if (pwrinfo5g->bw20_diff[rfPath][TxCount] & BIT(3))
2749 pwrinfo5g->bw20_diff[rfPath][TxCount] |= 0xF0;
2755 pwrinfo5g->ofdm_diff[rfPath][1] = (hwinfo[eeAddr] & 0xf0) >> 4;
2756 pwrinfo5g->ofdm_diff[rfPath][2] = (hwinfo[eeAddr] & 0x0f);
2760 pwrinfo5g->ofdm_diff[rfPath][3] = (hwinfo[eeAddr] & 0x0f);
2764 for (TxCount = 1; TxCount < MAX_TX_COUNT; TxCount++) {
2765 if (pwrinfo5g->ofdm_diff[rfPath][TxCount] & BIT(3))
2766 pwrinfo5g->ofdm_diff[rfPath][TxCount] |= 0xF0;
2768 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) {
2769 pwrinfo5g->bw80_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0xf0) >> 4;
2770 /* 4bit sign number to 8 bit sign number */
2771 if (pwrinfo5g->bw80_diff[rfPath][TxCount] & BIT(3))
2772 pwrinfo5g->bw80_diff[rfPath][TxCount] |= 0xF0;
2773 /* 4bit sign number to 8 bit sign number */
2774 pwrinfo5g->bw160_diff[rfPath][TxCount] = (hwinfo[eeAddr] & 0x0f);
2775 if (pwrinfo5g->bw160_diff[rfPath][TxCount] & BIT(3))
2776 pwrinfo5g->bw160_diff[rfPath][TxCount] |= 0xF0;
2783 static void _rtl8812ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2787 struct rtl_priv *rtlpriv = rtl_priv(hw);
2788 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2789 struct txpower_info_2g pwrinfo24g;
2790 struct txpower_info_5g pwrinfo5g;
2791 u8 channel5g[CHANNEL_MAX_NUMBER_5G] = {
2792 36, 38, 40, 42, 44, 46, 48, 50, 52, 54,
2793 56, 58, 60, 62, 64, 100, 102, 104, 106,
2794 108, 110, 112, 114, 116, 118, 120, 122,
2795 124, 126, 128, 130, 132, 134, 136, 138,
2796 140, 142, 144, 149, 151, 153, 155, 157,
2797 159, 161, 163, 165, 167, 168, 169, 171, 173, 175, 177};
2798 u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {42, 58, 106, 122, 138, 155, 171};
2802 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2803 &pwrinfo5g, autoload_fail, hwinfo);
2805 for (rf_path = 0; rf_path < 2; rf_path++) {
2806 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2807 index = _rtl8821ae_get_chnl_group(i + 1);
2809 if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2810 rtlefuse->txpwrlevel_cck[rf_path][i] =
2811 pwrinfo24g.index_cck_base[rf_path][5];
2812 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2813 pwrinfo24g.index_bw40_base[rf_path][index];
2815 rtlefuse->txpwrlevel_cck[rf_path][i] =
2816 pwrinfo24g.index_cck_base[rf_path][index];
2817 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2818 pwrinfo24g.index_bw40_base[rf_path][index];
2822 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2823 index = _rtl8821ae_get_chnl_group(channel5g[i]);
2824 rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2825 pwrinfo5g.index_bw40_base[rf_path][index];
2827 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2829 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2830 upper = pwrinfo5g.index_bw40_base[rf_path][index];
2831 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2833 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2835 for (i = 0; i < MAX_TX_COUNT; i++) {
2836 rtlefuse->txpwr_cckdiff[rf_path][i] =
2837 pwrinfo24g.cck_diff[rf_path][i];
2838 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2839 pwrinfo24g.ofdm_diff[rf_path][i];
2840 rtlefuse->txpwr_ht20diff[rf_path][i] =
2841 pwrinfo24g.bw20_diff[rf_path][i];
2842 rtlefuse->txpwr_ht40diff[rf_path][i] =
2843 pwrinfo24g.bw40_diff[rf_path][i];
2845 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2846 pwrinfo5g.ofdm_diff[rf_path][i];
2847 rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2848 pwrinfo5g.bw20_diff[rf_path][i];
2849 rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2850 pwrinfo5g.bw40_diff[rf_path][i];
2851 rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2852 pwrinfo5g.bw80_diff[rf_path][i];
2856 if (!autoload_fail) {
2857 rtlefuse->eeprom_regulatory =
2858 hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;/*bit0~2*/
2859 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2860 rtlefuse->eeprom_regulatory = 0;
2862 rtlefuse->eeprom_regulatory = 0;
2865 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2866 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2869 static void _rtl8821ae_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
2873 struct rtl_priv *rtlpriv = rtl_priv(hw);
2874 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2875 struct txpower_info_2g pwrinfo24g;
2876 struct txpower_info_5g pwrinfo5g;
2877 u8 channel5g[CHANNEL_MAX_NUMBER_5G] = {
2878 36, 38, 40, 42, 44, 46, 48, 50, 52, 54,
2879 56, 58, 60, 62, 64, 100, 102, 104, 106,
2880 108, 110, 112, 114, 116, 118, 120, 122,
2881 124, 126, 128, 130, 132, 134, 136, 138,
2882 140, 142, 144, 149, 151, 153, 155, 157,
2883 159, 161, 163, 165, 167, 168, 169, 171,
2885 u8 channel5g_80m[CHANNEL_MAX_NUMBER_5G_80M] = {
2886 42, 58, 106, 122, 138, 155, 171};
2890 _rtl8821ae_read_power_value_fromprom(hw, &pwrinfo24g,
2891 &pwrinfo5g, autoload_fail, hwinfo);
2893 for (rf_path = 0; rf_path < 2; rf_path++) {
2894 for (i = 0; i < CHANNEL_MAX_NUMBER_2G; i++) {
2895 index = _rtl8821ae_get_chnl_group(i + 1);
2897 if (i == CHANNEL_MAX_NUMBER_2G - 1) {
2898 rtlefuse->txpwrlevel_cck[rf_path][i] =
2899 pwrinfo24g.index_cck_base[rf_path][5];
2900 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2901 pwrinfo24g.index_bw40_base[rf_path][index];
2903 rtlefuse->txpwrlevel_cck[rf_path][i] =
2904 pwrinfo24g.index_cck_base[rf_path][index];
2905 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
2906 pwrinfo24g.index_bw40_base[rf_path][index];
2910 for (i = 0; i < CHANNEL_MAX_NUMBER_5G; i++) {
2911 index = _rtl8821ae_get_chnl_group(channel5g[i]);
2912 rtlefuse->txpwr_5g_bw40base[rf_path][i] =
2913 pwrinfo5g.index_bw40_base[rf_path][index];
2915 for (i = 0; i < CHANNEL_MAX_NUMBER_5G_80M; i++) {
2917 index = _rtl8821ae_get_chnl_group(channel5g_80m[i]);
2918 upper = pwrinfo5g.index_bw40_base[rf_path][index];
2919 lower = pwrinfo5g.index_bw40_base[rf_path][index + 1];
2921 rtlefuse->txpwr_5g_bw80base[rf_path][i] = (upper + lower) / 2;
2923 for (i = 0; i < MAX_TX_COUNT; i++) {
2924 rtlefuse->txpwr_cckdiff[rf_path][i] =
2925 pwrinfo24g.cck_diff[rf_path][i];
2926 rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
2927 pwrinfo24g.ofdm_diff[rf_path][i];
2928 rtlefuse->txpwr_ht20diff[rf_path][i] =
2929 pwrinfo24g.bw20_diff[rf_path][i];
2930 rtlefuse->txpwr_ht40diff[rf_path][i] =
2931 pwrinfo24g.bw40_diff[rf_path][i];
2933 rtlefuse->txpwr_5g_ofdmdiff[rf_path][i] =
2934 pwrinfo5g.ofdm_diff[rf_path][i];
2935 rtlefuse->txpwr_5g_bw20diff[rf_path][i] =
2936 pwrinfo5g.bw20_diff[rf_path][i];
2937 rtlefuse->txpwr_5g_bw40diff[rf_path][i] =
2938 pwrinfo5g.bw40_diff[rf_path][i];
2939 rtlefuse->txpwr_5g_bw80diff[rf_path][i] =
2940 pwrinfo5g.bw80_diff[rf_path][i];
2944 if (!autoload_fail) {
2945 rtlefuse->eeprom_regulatory = hwinfo[EEPROM_RF_BOARD_OPTION] & 0x07;
2946 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xFF)
2947 rtlefuse->eeprom_regulatory = 0;
2949 rtlefuse->eeprom_regulatory = 0;
2952 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2953 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2956 static void _rtl8812ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2959 struct rtl_priv *rtlpriv = rtl_priv(hw);
2960 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
2962 if (!autoload_fail) {
2963 rtlhal->pa_type_2g = hwinfo[0xBC];
2964 rtlhal->lna_type_2g = hwinfo[0xBD];
2965 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
2966 rtlhal->pa_type_2g = 0;
2967 rtlhal->lna_type_2g = 0;
2969 rtlhal->external_pa_2g = ((rtlhal->pa_type_2g & BIT(5)) &&
2970 (rtlhal->pa_type_2g & BIT(4))) ?
2972 rtlhal->external_lna_2g = ((rtlhal->lna_type_2g & BIT(7)) &&
2973 (rtlhal->lna_type_2g & BIT(3))) ?
2976 rtlhal->pa_type_5g = hwinfo[0xBC];
2977 rtlhal->lna_type_5g = hwinfo[0xBF];
2978 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
2979 rtlhal->pa_type_5g = 0;
2980 rtlhal->lna_type_5g = 0;
2982 rtlhal->external_pa_5g = ((rtlhal->pa_type_5g & BIT(1)) &&
2983 (rtlhal->pa_type_5g & BIT(0))) ?
2985 rtlhal->external_lna_5g = ((rtlhal->lna_type_5g & BIT(7)) &&
2986 (rtlhal->lna_type_5g & BIT(3))) ?
2989 rtlhal->external_pa_2g = 0;
2990 rtlhal->external_lna_2g = 0;
2991 rtlhal->external_pa_5g = 0;
2992 rtlhal->external_lna_5g = 0;
2996 static void _rtl8821ae_read_pa_type(struct ieee80211_hw *hw, u8 *hwinfo,
2999 struct rtl_priv *rtlpriv = rtl_priv(hw);
3000 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
3002 if (!autoload_fail) {
3003 rtlhal->pa_type_2g = hwinfo[0xBC];
3004 rtlhal->lna_type_2g = hwinfo[0xBD];
3005 if (rtlhal->pa_type_2g == 0xFF && rtlhal->lna_type_2g == 0xFF) {
3006 rtlhal->pa_type_2g = 0;
3007 rtlhal->lna_type_2g = 0;
3009 rtlhal->external_pa_2g = (rtlhal->pa_type_2g & BIT(5)) ? 1 : 0;
3010 rtlhal->external_lna_2g = (rtlhal->lna_type_2g & BIT(7)) ? 1 : 0;
3012 rtlhal->pa_type_5g = hwinfo[0xBC];
3013 rtlhal->lna_type_5g = hwinfo[0xBF];
3014 if (rtlhal->pa_type_5g == 0xFF && rtlhal->lna_type_5g == 0xFF) {
3015 rtlhal->pa_type_5g = 0;
3016 rtlhal->lna_type_5g = 0;
3018 rtlhal->external_pa_5g = (rtlhal->pa_type_5g & BIT(1)) ? 1 : 0;
3019 rtlhal->external_lna_5g = (rtlhal->lna_type_5g & BIT(7)) ? 1 : 0;
3021 rtlhal->external_pa_2g = 0;
3022 rtlhal->external_lna_2g = 0;
3023 rtlhal->external_pa_5g = 0;
3024 rtlhal->external_lna_5g = 0;
3028 static void _rtl8821ae_read_rfe_type(struct ieee80211_hw *hw, u8 *hwinfo,
3031 struct rtl_priv *rtlpriv = rtl_priv(hw);
3032 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
3034 if (!autoload_fail) {
3035 if (hwinfo[EEPROM_RFE_OPTION] & BIT(7)) {
3036 if (rtlhal->external_lna_5g) {
3037 if (rtlhal->external_pa_5g) {
3038 if (rtlhal->external_lna_2g &&
3039 rtlhal->external_pa_2g)
3040 rtlhal->rfe_type = 3;
3042 rtlhal->rfe_type = 0;
3044 rtlhal->rfe_type = 2;
3047 rtlhal->rfe_type = 4;
3050 rtlhal->rfe_type = hwinfo[EEPROM_RFE_OPTION] & 0x3F;
3052 if (rtlhal->rfe_type == 4 &&
3053 (rtlhal->external_pa_5g ||
3054 rtlhal->external_pa_2g ||
3055 rtlhal->external_lna_5g ||
3056 rtlhal->external_lna_2g)) {
3057 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE)
3058 rtlhal->rfe_type = 2;
3062 rtlhal->rfe_type = 0x04;
3065 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3066 "RFE Type: 0x%2x\n", rtlhal->rfe_type);
3069 static void _rtl8812ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3070 bool auto_load_fail, u8 *hwinfo)
3072 struct rtl_priv *rtlpriv = rtl_priv(hw);
3075 if (!auto_load_fail) {
3076 value = *(u8 *)&hwinfo[EEPROM_RF_BOARD_OPTION];
3077 if (((value & 0xe0) >> 5) == 0x1)
3078 rtlpriv->btcoexist.btc_info.btcoexist = 1;
3080 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3081 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3083 value = hwinfo[EEPROM_RF_BT_SETTING];
3084 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3086 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3087 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8812A;
3088 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3090 /*move BT_InitHalVars() to init_sw_vars*/
3093 static void _rtl8821ae_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
3094 bool auto_load_fail, u8 *hwinfo)
3096 struct rtl_priv *rtlpriv = rtl_priv(hw);
3100 if (!auto_load_fail) {
3101 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
3102 if (tmpu_32 & BIT(18))
3103 rtlpriv->btcoexist.btc_info.btcoexist = 1;
3105 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3106 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3108 value = hwinfo[EEPROM_RF_BT_SETTING];
3109 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
3111 rtlpriv->btcoexist.btc_info.btcoexist = 0;
3112 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8821A;
3113 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
3115 /*move BT_InitHalVars() to init_sw_vars*/
3118 static void _rtl8821ae_read_adapter_info(struct ieee80211_hw *hw, bool b_pseudo_test)
3120 struct rtl_priv *rtlpriv = rtl_priv(hw);
3121 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3122 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3123 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3125 u8 hwinfo[HWSET_MAX_SIZE];
3128 if (b_pseudo_test) {
3132 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
3133 rtl_efuse_shadow_map_update(hw);
3134 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
3136 } else if (rtlefuse->epromtype == EEPROM_93C46) {
3137 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3138 "RTL819X Not boot from eeprom, check it !!");
3141 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP\n",
3142 hwinfo, HWSET_MAX_SIZE);
3144 eeprom_id = *((u16 *)&hwinfo[0]);
3145 if (eeprom_id != RTL_EEPROM_ID) {
3146 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
3147 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
3148 rtlefuse->autoload_failflag = true;
3150 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
3151 rtlefuse->autoload_failflag = false;
3154 if (rtlefuse->autoload_failflag) {
3155 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
3156 "RTL8812AE autoload_failflag, check it !!");
3160 rtlefuse->eeprom_version = *(u8 *)&hwinfo[EEPROM_VERSION];
3161 if (rtlefuse->eeprom_version == 0xff)
3162 rtlefuse->eeprom_version = 0;
3164 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3165 "EEPROM version: 0x%2x\n", rtlefuse->eeprom_version);
3167 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
3168 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
3169 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
3170 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
3171 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3172 "EEPROMId = 0x%4x\n", eeprom_id);
3173 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3174 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
3175 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3176 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
3177 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3178 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
3179 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3180 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
3183 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
3184 if (rtlefuse->eeprom_oemid == 0xFF)
3185 rtlefuse->eeprom_oemid = 0;
3187 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3188 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
3190 for (i = 0; i < 6; i += 2) {
3191 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
3192 *((u16 *)(&rtlefuse->dev_addr[i])) = usvalue;
3195 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3196 "dev_addr: %pM\n", rtlefuse->dev_addr);
3198 _rtl8821ae_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
3201 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8812AE) {
3202 _rtl8812ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag);
3203 _rtl8812ae_read_bt_coexist_info_from_hwpg(hw,
3204 rtlefuse->autoload_failflag, hwinfo);
3206 _rtl8821ae_read_pa_type(hw, hwinfo, rtlefuse->autoload_failflag);
3207 _rtl8821ae_read_bt_coexist_info_from_hwpg(hw,
3208 rtlefuse->autoload_failflag, hwinfo);
3211 _rtl8821ae_read_rfe_type(hw, hwinfo, rtlefuse->autoload_failflag);
3213 rtlefuse->board_type = ODM_BOARD_DEFAULT;
3214 if (rtlhal->external_lna_2g != 0)
3215 rtlefuse->board_type |= ODM_BOARD_EXT_LNA;
3216 if (rtlhal->external_lna_5g != 0)
3217 rtlefuse->board_type |= ODM_BOARD_EXT_LNA_5G;
3218 if (rtlhal->external_pa_2g != 0)
3219 rtlefuse->board_type |= ODM_BOARD_EXT_PA;
3220 if (rtlhal->external_pa_5g != 0)
3221 rtlefuse->board_type |= ODM_BOARD_EXT_PA_5G;
3223 if (rtlpriv->btcoexist.btc_info.btcoexist == 1)
3224 rtlefuse->board_type |= ODM_BOARD_BT;
3226 rtlhal->board_type = rtlefuse->board_type;
3227 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3228 "board_type = 0x%x\n", rtlefuse->board_type);
3230 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
3231 if (rtlefuse->eeprom_channelplan == 0xff)
3232 rtlefuse->eeprom_channelplan = 0x7F;
3234 /* set channel plan from efuse */
3235 rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
3238 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8821AE];
3239 if (rtlefuse->crystalcap == 0xFF)
3240 rtlefuse->crystalcap = 0x20;
3242 rtlefuse->eeprom_thermalmeter = *(u8 *)&hwinfo[EEPROM_THERMAL_METER];
3243 if ((rtlefuse->eeprom_thermalmeter == 0xff) ||
3244 rtlefuse->autoload_failflag) {
3245 rtlefuse->apk_thermalmeterignore = true;
3246 rtlefuse->eeprom_thermalmeter = 0xff;
3249 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
3250 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3251 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
3253 if (!rtlefuse->autoload_failflag) {
3254 rtlefuse->antenna_div_cfg =
3255 (hwinfo[EEPROM_RF_BOARD_OPTION] & 0x18) >> 3;
3256 if (hwinfo[EEPROM_RF_BOARD_OPTION] == 0xff)
3257 rtlefuse->antenna_div_cfg = 0;
3259 if (rtlpriv->btcoexist.btc_info.btcoexist == 1 &&
3260 rtlpriv->btcoexist.btc_info.ant_num == ANT_X1)
3261 rtlefuse->antenna_div_cfg = 0;
3263 rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
3264 if (rtlefuse->antenna_div_type == 0xff)
3265 rtlefuse->antenna_div_type = FIXED_HW_ANTDIV;
3267 rtlefuse->antenna_div_cfg = 0;
3268 rtlefuse->antenna_div_type = 0;
3271 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
3272 "SWAS: bHwAntDiv = %x, TRxAntDivType = %x\n",
3273 rtlefuse->antenna_div_cfg, rtlefuse->antenna_div_type);
3275 pcipriv->ledctl.led_opendrain = true;
3277 if (rtlhal->oem_id == RT_CID_DEFAULT) {
3278 switch (rtlefuse->eeprom_oemid) {
3279 case RT_CID_DEFAULT:
3281 case EEPROM_CID_TOSHIBA:
3282 rtlhal->oem_id = RT_CID_TOSHIBA;
3284 case EEPROM_CID_CCX:
3285 rtlhal->oem_id = RT_CID_CCX;
3287 case EEPROM_CID_QMI:
3288 rtlhal->oem_id = RT_CID_819X_QMI;
3290 case EEPROM_CID_WHQL:
3298 /*static void _rtl8821ae_hal_customized_behavior(struct ieee80211_hw *hw)
3300 struct rtl_priv *rtlpriv = rtl_priv(hw);
3301 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
3302 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3304 pcipriv->ledctl.led_opendrain = true;
3305 switch (rtlhal->oem_id) {
3306 case RT_CID_819X_HP:
3307 pcipriv->ledctl.led_opendrain = true;
3309 case RT_CID_819X_LENOVO:
3310 case RT_CID_DEFAULT:
3311 case RT_CID_TOSHIBA:
3313 case RT_CID_819X_ACER:
3318 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
3319 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
3322 void rtl8821ae_read_eeprom_info(struct ieee80211_hw *hw)
3324 struct rtl_priv *rtlpriv = rtl_priv(hw);
3325 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3326 struct rtl_phy *rtlphy = &rtlpriv->phy;
3327 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3330 rtlhal->version = _rtl8821ae_read_chip_version(hw);
3331 if (get_rf_type(rtlphy) == RF_1T1R)
3332 rtlpriv->dm.rfpath_rxenable[0] = true;
3334 rtlpriv->dm.rfpath_rxenable[0] =
3335 rtlpriv->dm.rfpath_rxenable[1] = true;
3336 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
3339 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
3340 if (tmp_u1b & BIT(4)) {
3341 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
3342 rtlefuse->epromtype = EEPROM_93C46;
3344 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
3345 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
3348 if (tmp_u1b & BIT(5)) {
3349 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
3350 rtlefuse->autoload_failflag = false;
3351 _rtl8821ae_read_adapter_info(hw, false);
3353 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
3355 /*hal_ReadRFType_8812A()*/
3356 /* _rtl8821ae_hal_customized_behavior(hw); */
3359 static void rtl8821ae_update_hal_rate_table(struct ieee80211_hw *hw,
3360 struct ieee80211_sta *sta)
3362 struct rtl_priv *rtlpriv = rtl_priv(hw);
3363 struct rtl_phy *rtlphy = &rtlpriv->phy;
3364 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3365 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
3368 u8 b_nmode = mac->ht_enable;
3369 u8 mimo_ps = IEEE80211_SMPS_OFF;
3372 u8 curtxbw_40mhz = mac->bw_40;
3373 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3375 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3377 enum wireless_mode wirelessmode = mac->mode;
3379 if (rtlhal->current_bandtype == BAND_ON_5G)
3380 ratr_value = sta->supp_rates[1] << 4;
3382 ratr_value = sta->supp_rates[0];
3383 if (mac->opmode == NL80211_IFTYPE_ADHOC)
3385 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3386 sta->ht_cap.mcs.rx_mask[0] << 12);
3387 switch (wirelessmode) {
3388 case WIRELESS_MODE_B:
3389 if (ratr_value & 0x0000000c)
3390 ratr_value &= 0x0000000d;
3392 ratr_value &= 0x0000000f;
3394 case WIRELESS_MODE_G:
3395 ratr_value &= 0x00000FF5;
3397 case WIRELESS_MODE_N_24G:
3398 case WIRELESS_MODE_N_5G:
3400 if (mimo_ps == IEEE80211_SMPS_STATIC) {
3401 ratr_value &= 0x0007F005;
3405 if (get_rf_type(rtlphy) == RF_1T2R ||
3406 get_rf_type(rtlphy) == RF_1T1R)
3407 ratr_mask = 0x000ff005;
3409 ratr_mask = 0x0f0ff005;
3411 ratr_value &= ratr_mask;
3415 if (rtlphy->rf_type == RF_1T2R)
3416 ratr_value &= 0x000ff0ff;
3418 ratr_value &= 0x0f0ff0ff;
3423 if ((rtlpriv->btcoexist.bt_coexistence) &&
3424 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
3425 (rtlpriv->btcoexist.bt_cur_state) &&
3426 (rtlpriv->btcoexist.bt_ant_isolation) &&
3427 ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
3428 (rtlpriv->btcoexist.bt_service == BT_BUSY)))
3429 ratr_value &= 0x0fffcfc0;
3431 ratr_value &= 0x0FFFFFFF;
3433 if (b_nmode && ((curtxbw_40mhz &&
3434 b_curshortgi_40mhz) || (!curtxbw_40mhz &&
3435 b_curshortgi_20mhz))) {
3436 ratr_value |= 0x10000000;
3437 tmp_ratr_value = (ratr_value >> 12);
3439 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
3440 if ((1 << shortgi_rate) & tmp_ratr_value)
3444 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
3445 (shortgi_rate << 4) | (shortgi_rate);
3448 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
3450 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3451 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
3454 static u8 _rtl8821ae_mrate_idx_to_arfr_id(
3455 struct ieee80211_hw *hw, u8 rate_index,
3456 enum wireless_mode wirelessmode)
3458 struct rtl_priv *rtlpriv = rtl_priv(hw);
3459 struct rtl_phy *rtlphy = &rtlpriv->phy;
3461 switch (rate_index) {
3462 case RATR_INX_WIRELESS_NGB:
3463 if (rtlphy->rf_type == RF_1T1R)
3468 case RATR_INX_WIRELESS_N:
3469 case RATR_INX_WIRELESS_NG:
3470 if (rtlphy->rf_type == RF_1T1R)
3475 case RATR_INX_WIRELESS_NB:
3476 if (rtlphy->rf_type == RF_1T1R)
3481 case RATR_INX_WIRELESS_GB:
3484 case RATR_INX_WIRELESS_G:
3487 case RATR_INX_WIRELESS_B:
3490 case RATR_INX_WIRELESS_MC:
3491 if ((wirelessmode == WIRELESS_MODE_B)
3492 || (wirelessmode == WIRELESS_MODE_G)
3493 || (wirelessmode == WIRELESS_MODE_N_24G)
3494 || (wirelessmode == WIRELESS_MODE_AC_24G))
3498 case RATR_INX_WIRELESS_AC_5N:
3499 if (rtlphy->rf_type == RF_1T1R)
3504 case RATR_INX_WIRELESS_AC_24N:
3505 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80) {
3506 if (rtlphy->rf_type == RF_1T1R)
3511 if (rtlphy->rf_type == RF_1T1R)
3523 static u32 _rtl8821ae_rate_to_bitmap_2ssvht(__le16 vht_rate)
3526 u32 rate_bitmap = 0;
3528 for (i = j = 0; i < 4; i += 2, j += 10) {
3529 tmp_rate = (le16_to_cpu(vht_rate) >> i) & 3;
3533 rate_bitmap = rate_bitmap | (0x03ff << j);
3536 rate_bitmap = rate_bitmap | (0x01ff << j);
3539 rate_bitmap = rate_bitmap | (0x00ff << j);
3549 static u32 _rtl8821ae_set_ra_vht_ratr_bitmap(struct ieee80211_hw *hw,
3550 enum wireless_mode wirelessmode,
3553 struct rtl_priv *rtlpriv = rtl_priv(hw);
3554 struct rtl_phy *rtlphy = &rtlpriv->phy;
3555 u32 ret_bitmap = ratr_bitmap;
3557 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40
3558 || rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_80)
3559 ret_bitmap = ratr_bitmap;
3560 else if (wirelessmode == WIRELESS_MODE_AC_5G
3561 || wirelessmode == WIRELESS_MODE_AC_24G) {
3562 if (rtlphy->rf_type == RF_1T1R)
3563 ret_bitmap = ratr_bitmap & (~BIT21);
3565 ret_bitmap = ratr_bitmap & (~(BIT31|BIT21));
3571 static u8 _rtl8821ae_get_vht_eni(enum wireless_mode wirelessmode,
3575 if (wirelessmode < WIRELESS_MODE_N_24G)
3577 else if (wirelessmode == WIRELESS_MODE_AC_24G) {
3578 if (ratr_bitmap & 0xfff00000) /* Mix , 2SS */
3582 } else if (wirelessmode == WIRELESS_MODE_AC_5G) {
3589 static u8 _rtl8821ae_get_ra_ldpc(struct ieee80211_hw *hw,
3590 u8 mac_id, struct rtl_sta_info *sta_entry,
3591 enum wireless_mode wirelessmode)
3594 /*not support ldpc, do not open*/
3598 static u8 _rtl8821ae_get_ra_rftype(struct ieee80211_hw *hw,
3599 enum wireless_mode wirelessmode,
3602 struct rtl_priv *rtlpriv = rtl_priv(hw);
3603 struct rtl_phy *rtlphy = &rtlpriv->phy;
3604 u8 rf_type = RF_1T1R;
3606 if (rtlphy->rf_type == RF_1T1R)
3608 else if (wirelessmode == WIRELESS_MODE_AC_5G
3609 || wirelessmode == WIRELESS_MODE_AC_24G
3610 || wirelessmode == WIRELESS_MODE_AC_ONLY) {
3611 if (ratr_bitmap & 0xffc00000)
3613 } else if (wirelessmode == WIRELESS_MODE_N_5G
3614 || wirelessmode == WIRELESS_MODE_N_24G) {
3615 if (ratr_bitmap & 0xfff00000)
3622 static bool _rtl8821ae_get_ra_shortgi(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
3625 bool b_short_gi = false;
3626 u8 b_curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
3628 u8 b_curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
3630 u8 b_curshortgi_80mhz = 0;
3631 b_curshortgi_80mhz = (sta->vht_cap.cap &
3632 IEEE80211_VHT_CAP_SHORT_GI_80) ? 1 : 0;
3634 if (mac_id == MAC_ID_STATIC_FOR_BROADCAST_MULTICAST)
3637 if (b_curshortgi_40mhz || b_curshortgi_80mhz
3638 || b_curshortgi_20mhz)
3644 static void rtl8821ae_update_hal_rate_mask(struct ieee80211_hw *hw,
3645 struct ieee80211_sta *sta, u8 rssi_level)
3647 struct rtl_priv *rtlpriv = rtl_priv(hw);
3648 struct rtl_phy *rtlphy = &rtlpriv->phy;
3649 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3650 struct rtl_sta_info *sta_entry = NULL;
3653 enum wireless_mode wirelessmode = 0;
3654 u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
3656 bool b_shortgi = false;
3659 u8 mimo_ps = IEEE80211_SMPS_OFF;
3662 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
3663 wirelessmode = sta_entry->wireless_mode;
3665 RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3666 "wireless mode = 0x%x\n", wirelessmode);
3667 if (mac->opmode == NL80211_IFTYPE_STATION ||
3668 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
3669 curtxbw_40mhz = mac->bw_40;
3670 } else if (mac->opmode == NL80211_IFTYPE_AP ||
3671 mac->opmode == NL80211_IFTYPE_ADHOC)
3672 macid = sta->aid + 1;
3673 if (wirelessmode == WIRELESS_MODE_N_5G ||
3674 wirelessmode == WIRELESS_MODE_AC_5G ||
3675 wirelessmode == WIRELESS_MODE_A)
3676 ratr_bitmap = sta->supp_rates[NL80211_BAND_5GHZ] << 4;
3678 ratr_bitmap = sta->supp_rates[NL80211_BAND_2GHZ];
3680 if (mac->opmode == NL80211_IFTYPE_ADHOC)
3681 ratr_bitmap = 0xfff;
3683 if (wirelessmode == WIRELESS_MODE_N_24G
3684 || wirelessmode == WIRELESS_MODE_N_5G)
3685 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
3686 sta->ht_cap.mcs.rx_mask[0] << 12);
3687 else if (wirelessmode == WIRELESS_MODE_AC_24G
3688 || wirelessmode == WIRELESS_MODE_AC_5G
3689 || wirelessmode == WIRELESS_MODE_AC_ONLY)
3690 ratr_bitmap |= _rtl8821ae_rate_to_bitmap_2ssvht(
3691 sta->vht_cap.vht_mcs.rx_mcs_map) << 12;
3693 b_shortgi = _rtl8821ae_get_ra_shortgi(hw, sta, macid);
3694 rf_type = _rtl8821ae_get_ra_rftype(hw, wirelessmode, ratr_bitmap);
3697 switch (wirelessmode) {
3698 case WIRELESS_MODE_B:
3699 ratr_index = RATR_INX_WIRELESS_B;
3700 if (ratr_bitmap & 0x0000000c)
3701 ratr_bitmap &= 0x0000000d;
3703 ratr_bitmap &= 0x0000000f;
3705 case WIRELESS_MODE_G:
3706 ratr_index = RATR_INX_WIRELESS_GB;
3708 if (rssi_level == 1)
3709 ratr_bitmap &= 0x00000f00;
3710 else if (rssi_level == 2)
3711 ratr_bitmap &= 0x00000ff0;
3713 ratr_bitmap &= 0x00000ff5;
3715 case WIRELESS_MODE_A:
3716 ratr_index = RATR_INX_WIRELESS_G;
3717 ratr_bitmap &= 0x00000ff0;
3719 case WIRELESS_MODE_N_24G:
3720 case WIRELESS_MODE_N_5G:
3721 if (wirelessmode == WIRELESS_MODE_N_24G)
3722 ratr_index = RATR_INX_WIRELESS_NGB;
3724 ratr_index = RATR_INX_WIRELESS_NG;
3726 if (mimo_ps == IEEE80211_SMPS_STATIC
3727 || mimo_ps == IEEE80211_SMPS_DYNAMIC) {
3728 if (rssi_level == 1)
3729 ratr_bitmap &= 0x000f0000;
3730 else if (rssi_level == 2)
3731 ratr_bitmap &= 0x000ff000;
3733 ratr_bitmap &= 0x000ff005;
3735 if (rf_type == RF_1T1R) {
3736 if (curtxbw_40mhz) {
3737 if (rssi_level == 1)
3738 ratr_bitmap &= 0x000f0000;
3739 else if (rssi_level == 2)
3740 ratr_bitmap &= 0x000ff000;
3742 ratr_bitmap &= 0x000ff015;
3744 if (rssi_level == 1)
3745 ratr_bitmap &= 0x000f0000;
3746 else if (rssi_level == 2)
3747 ratr_bitmap &= 0x000ff000;
3749 ratr_bitmap &= 0x000ff005;
3752 if (curtxbw_40mhz) {
3753 if (rssi_level == 1)
3754 ratr_bitmap &= 0x0fff0000;
3755 else if (rssi_level == 2)
3756 ratr_bitmap &= 0x0ffff000;
3758 ratr_bitmap &= 0x0ffff015;
3760 if (rssi_level == 1)
3761 ratr_bitmap &= 0x0fff0000;
3762 else if (rssi_level == 2)
3763 ratr_bitmap &= 0x0ffff000;
3765 ratr_bitmap &= 0x0ffff005;
3771 case WIRELESS_MODE_AC_24G:
3772 ratr_index = RATR_INX_WIRELESS_AC_24N;
3773 if (rssi_level == 1)
3774 ratr_bitmap &= 0xfc3f0000;
3775 else if (rssi_level == 2)
3776 ratr_bitmap &= 0xfffff000;
3778 ratr_bitmap &= 0xffffffff;
3781 case WIRELESS_MODE_AC_5G:
3782 ratr_index = RATR_INX_WIRELESS_AC_5N;
3784 if (rf_type == RF_1T1R) {
3785 if (rssi_level == 1) /*add by Gary for ac-series*/
3786 ratr_bitmap &= 0x003f8000;
3787 else if (rssi_level == 2)
3788 ratr_bitmap &= 0x003ff000;
3790 ratr_bitmap &= 0x003ff010;
3792 if (rssi_level == 1)
3793 ratr_bitmap &= 0xfe3f8000;
3794 else if (rssi_level == 2)
3795 ratr_bitmap &= 0xfffff000;
3797 ratr_bitmap &= 0xfffff010;
3802 ratr_index = RATR_INX_WIRELESS_NGB;
3804 if (rf_type == RF_1T2R)
3805 ratr_bitmap &= 0x000ff0ff;
3807 ratr_bitmap &= 0x0f8ff0ff;
3811 ratr_index = _rtl8821ae_mrate_idx_to_arfr_id(hw, ratr_index, wirelessmode);
3812 sta_entry->ratr_index = ratr_index;
3813 ratr_bitmap = _rtl8821ae_set_ra_vht_ratr_bitmap(hw, wirelessmode,
3816 RT_TRACE(rtlpriv, COMP_RATR, DBG_LOUD,
3817 "ratr_bitmap :%x\n", ratr_bitmap);
3819 /* *(u32 *)& rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
3820 (ratr_index << 28)); */
3822 rate_mask[0] = macid;
3823 rate_mask[1] = ratr_index | (b_shortgi ? 0x80 : 0x00);
3824 rate_mask[2] = rtlphy->current_chan_bw
3825 | _rtl8821ae_get_vht_eni(wirelessmode, ratr_bitmap)
3826 | _rtl8821ae_get_ra_ldpc(hw, macid, sta_entry, wirelessmode);
3828 rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
3829 rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
3830 rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
3831 rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
3833 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
3834 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
3835 ratr_index, ratr_bitmap,
3836 rate_mask[0], rate_mask[1],
3837 rate_mask[2], rate_mask[3],
3838 rate_mask[4], rate_mask[5],
3840 rtl8821ae_fill_h2c_cmd(hw, H2C_8821AE_RA_MASK, 7, rate_mask);
3841 _rtl8821ae_set_bcn_ctrl_reg(hw, BIT(3), 0);
3844 void rtl8821ae_update_hal_rate_tbl(struct ieee80211_hw *hw,
3845 struct ieee80211_sta *sta, u8 rssi_level)
3847 struct rtl_priv *rtlpriv = rtl_priv(hw);
3848 if (rtlpriv->dm.useramask)
3849 rtl8821ae_update_hal_rate_mask(hw, sta, rssi_level);
3851 /*RT_TRACE(rtlpriv, COMP_RATR,DBG_LOUD,
3852 "rtl8821ae_update_hal_rate_tbl() Error! 8821ae FW RA Only");*/
3853 rtl8821ae_update_hal_rate_table(hw, sta);
3856 void rtl8821ae_update_channel_access_setting(struct ieee80211_hw *hw)
3858 struct rtl_priv *rtlpriv = rtl_priv(hw);
3859 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3860 u8 wireless_mode = mac->mode;
3861 u8 sifs_timer, r2t_sifs;
3863 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
3864 (u8 *)&mac->slot_time);
3865 if (wireless_mode == WIRELESS_MODE_G)
3869 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
3873 if (wireless_mode == WIRELESS_MODE_AC_5G &&
3874 (mac->vht_ldpc_cap & LDPC_VHT_ENABLE_RX) &&
3875 (mac->vht_stbc_cap & STBC_VHT_ENABLE_RX)) {
3876 if (mac->vendor == PEER_ATH)
3880 } else if (wireless_mode == WIRELESS_MODE_AC_5G) {
3884 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_R2T_SIFS, (u8 *)&r2t_sifs);
3887 bool rtl8821ae_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
3889 struct rtl_priv *rtlpriv = rtl_priv(hw);
3890 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
3891 struct rtl_phy *rtlphy = &rtlpriv->phy;
3892 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
3894 bool b_actuallyset = false;
3896 if (rtlpriv->rtlhal.being_init_adapter)
3899 if (ppsc->swrf_processing)
3902 spin_lock(&rtlpriv->locks.rf_ps_lock);
3903 if (ppsc->rfchange_inprogress) {
3904 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3907 ppsc->rfchange_inprogress = true;
3908 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3911 cur_rfstate = ppsc->rfpwr_state;
3913 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
3914 rtl_read_byte(rtlpriv,
3915 REG_GPIO_IO_SEL_2) & ~(BIT(1)));
3917 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
3919 if (rtlphy->polarity_ctl)
3920 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
3922 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
3924 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
3925 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3926 "GPIOChangeRF - HW Radio ON, RF ON\n");
3928 e_rfpowerstate_toset = ERFON;
3929 ppsc->hwradiooff = false;
3930 b_actuallyset = true;
3931 } else if ((!ppsc->hwradiooff)
3932 && (e_rfpowerstate_toset == ERFOFF)) {
3933 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
3934 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
3936 e_rfpowerstate_toset = ERFOFF;
3937 ppsc->hwradiooff = true;
3938 b_actuallyset = true;
3941 if (b_actuallyset) {
3942 spin_lock(&rtlpriv->locks.rf_ps_lock);
3943 ppsc->rfchange_inprogress = false;
3944 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3946 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
3947 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
3949 spin_lock(&rtlpriv->locks.rf_ps_lock);
3950 ppsc->rfchange_inprogress = false;
3951 spin_unlock(&rtlpriv->locks.rf_ps_lock);
3955 return !ppsc->hwradiooff;
3958 void rtl8821ae_set_key(struct ieee80211_hw *hw, u32 key_index,
3959 u8 *p_macaddr, bool is_group, u8 enc_algo,
3960 bool is_wepkey, bool clear_all)
3962 struct rtl_priv *rtlpriv = rtl_priv(hw);
3963 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
3964 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
3965 u8 *macaddr = p_macaddr;
3967 bool is_pairwise = false;
3969 static u8 cam_const_addr[4][6] = {
3970 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
3971 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
3972 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
3973 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
3975 static u8 cam_const_broad[] = {
3976 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
3982 u8 clear_number = 5;
3984 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
3986 for (idx = 0; idx < clear_number; idx++) {
3987 rtl_cam_mark_invalid(hw, cam_offset + idx);
3988 rtl_cam_empty_entry(hw, cam_offset + idx);
3991 memset(rtlpriv->sec.key_buf[idx], 0,
3993 rtlpriv->sec.key_len[idx] = 0;
3998 case WEP40_ENCRYPTION:
3999 enc_algo = CAM_WEP40;
4001 case WEP104_ENCRYPTION:
4002 enc_algo = CAM_WEP104;
4004 case TKIP_ENCRYPTION:
4005 enc_algo = CAM_TKIP;
4007 case AESCCMP_ENCRYPTION:
4011 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
4012 "switch case not process\n");
4013 enc_algo = CAM_TKIP;
4017 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
4018 macaddr = cam_const_addr[key_index];
4019 entry_id = key_index;
4022 macaddr = cam_const_broad;
4023 entry_id = key_index;
4025 if (mac->opmode == NL80211_IFTYPE_AP) {
4026 entry_id = rtl_cam_get_free_entry(hw, p_macaddr);
4027 if (entry_id >= TOTAL_CAM_ENTRY) {
4028 RT_TRACE(rtlpriv, COMP_SEC, DBG_EMERG,
4029 "Can not find free hwsecurity cam entry\n");
4033 entry_id = CAM_PAIRWISE_KEY_POSITION;
4036 key_index = PAIRWISE_KEYIDX;
4041 if (rtlpriv->sec.key_len[key_index] == 0) {
4042 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4043 "delete one entry, entry_id is %d\n",
4045 if (mac->opmode == NL80211_IFTYPE_AP)
4046 rtl_cam_del_entry(hw, p_macaddr);
4047 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
4049 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4052 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4053 "set Pairwise key\n");
4055 rtl_cam_add_one_entry(hw, macaddr, key_index,
4057 CAM_CONFIG_NO_USEDK,
4058 rtlpriv->sec.key_buf[key_index]);
4060 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
4063 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
4064 rtl_cam_add_one_entry(hw,
4067 CAM_PAIRWISE_KEY_POSITION,
4069 CAM_CONFIG_NO_USEDK,
4070 rtlpriv->sec.key_buf
4074 rtl_cam_add_one_entry(hw, macaddr, key_index,
4076 CAM_CONFIG_NO_USEDK,
4077 rtlpriv->sec.key_buf[entry_id]);
4083 void rtl8821ae_bt_reg_init(struct ieee80211_hw *hw)
4085 struct rtl_priv *rtlpriv = rtl_priv(hw);
4087 /* 0:Low, 1:High, 2:From Efuse. */
4088 rtlpriv->btcoexist.reg_bt_iso = 2;
4089 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
4090 rtlpriv->btcoexist.reg_bt_sco = 3;
4091 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
4092 rtlpriv->btcoexist.reg_bt_sco = 0;
4095 void rtl8821ae_bt_hw_init(struct ieee80211_hw *hw)
4097 struct rtl_priv *rtlpriv = rtl_priv(hw);
4099 if (rtlpriv->cfg->ops->get_btc_status())
4100 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
4103 void rtl8821ae_suspend(struct ieee80211_hw *hw)
4107 void rtl8821ae_resume(struct ieee80211_hw *hw)
4111 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
4112 void rtl8821ae_allow_all_destaddr(struct ieee80211_hw *hw,
4113 bool allow_all_da, bool write_into_reg)
4115 struct rtl_priv *rtlpriv = rtl_priv(hw);
4116 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
4118 if (allow_all_da) /* Set BIT0 */
4119 rtlpci->receive_config |= RCR_AAP;
4120 else /* Clear BIT0 */
4121 rtlpci->receive_config &= ~RCR_AAP;
4124 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
4126 RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
4127 "receive_config=0x%08X, write_into_reg=%d\n",
4128 rtlpci->receive_config, write_into_reg);
4131 /* WKFMCAMAddAllEntry8812 */
4132 void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw,
4133 struct rtl_wow_pattern *rtl_pattern,
4136 struct rtl_priv *rtlpriv = rtl_priv(hw);
4144 /* Count the WFCAM entry start offset. */
4146 /* RX page size = 128 byte */
4147 offset = MAX_RX_DMA_BUFFER_SIZE_8812 / 128;
4148 /* We should start from the boundry */
4149 cam_start = offset * 128;
4151 /* Enable Rx packet buffer access. */
4152 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
4153 for (addr = 0; addr < WKFMCAM_ADDR_NUM; addr++) {
4154 /* Set Rx packet buffer offset.
4155 * RxBufer pointer increases 1,
4156 * we can access 8 bytes in Rx packet buffer.
4157 * CAM start offset (unit: 1 byte) = index*WKFMCAM_SIZE
4158 * RxBufer addr = (CAM start offset +
4159 * per entry offset of a WKFM CAM)/8
4160 * * index: The index of the wake up frame mask
4161 * * WKFMCAM_SIZE: the total size of one WKFM CAM
4162 * * per entry offset of a WKFM CAM: Addr*4 bytes
4164 rxbuf_addr = (cam_start + index * WKFMCAM_SIZE + addr * 4) >> 3;
4165 /* Set R/W start offset */
4166 rtl_write_word(rtlpriv, REG_PKTBUF_DBG_CTRL, rxbuf_addr);
4169 cam = BIT(31) | rtl_pattern->crc;
4171 if (rtl_pattern->type == UNICAST_PATTERN)
4173 else if (rtl_pattern->type == MULTICAST_PATTERN)
4175 else if (rtl_pattern->type == BROADCAST_PATTERN)
4178 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4179 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4180 "WRITE entry[%d] 0x%x: %x\n", addr,
4181 REG_PKTBUF_DBG_DATA_L, cam);
4183 /* Write to Rx packet buffer. */
4184 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4185 } else if (addr == 2 || addr == 4) {/* WKFM[127:0] */
4186 cam = rtl_pattern->mask[addr - 2];
4188 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
4189 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4190 "WRITE entry[%d] 0x%x: %x\n", addr,
4191 REG_PKTBUF_DBG_DATA_L, cam);
4193 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
4194 } else if (addr == 3 || addr == 5) {/* WKFM[127:0] */
4195 cam = rtl_pattern->mask[addr - 2];
4197 rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_H, cam);
4198 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
4199 "WRITE entry[%d] 0x%x: %x\n", addr,
4200 REG_PKTBUF_DBG_DATA_H, cam);
4202 rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0xf001);
4207 tmp = rtl_read_byte(rtlpriv, REG_RXPKTBUF_CTRL);
4210 } while (tmp && count < 100);
4212 RT_ASSERT((count < 100),
4213 "Write wake up frame mask FAIL %d value!\n", tmp);
4215 /* Disable Rx packet buffer access. */
4216 rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL,
4217 DISABLE_TRXPKT_BUF_ACCESS);