1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/usb/host/ehci-orion.c
5 * Tzachi Perelstein <tzachi@marvell.com>
8 #include <linux/kernel.h>
9 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 #include <linux/mbus.h>
12 #include <linux/clk.h>
13 #include <linux/platform_data/usb-ehci-orion.h>
15 #include <linux/phy/phy.h>
16 #include <linux/usb.h>
17 #include <linux/usb/hcd.h>
19 #include <linux/dma-mapping.h>
23 #define rdl(off) readl_relaxed(hcd->regs + (off))
24 #define wrl(off, val) writel_relaxed((val), hcd->regs + (off))
27 #define USB_CMD_RUN BIT(0)
28 #define USB_CMD_RESET BIT(1)
29 #define USB_MODE 0x1a8
30 #define USB_MODE_MASK GENMASK(1, 0)
31 #define USB_MODE_DEVICE 0x2
32 #define USB_MODE_HOST 0x3
33 #define USB_MODE_SDIS BIT(4)
34 #define USB_CAUSE 0x310
35 #define USB_MASK 0x314
36 #define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4))
37 #define USB_WINDOW_BASE(i) (0x324 + ((i) << 4))
39 #define USB_PHY_PWR_CTRL 0x400
40 #define USB_PHY_TX_CTRL 0x420
41 #define USB_PHY_RX_CTRL 0x430
42 #define USB_PHY_IVREF_CTRL 0x440
43 #define USB_PHY_TST_GRP_CTRL 0x450
45 #define USB_SBUSCFG 0x90
47 /* BAWR = BARD = 3 : Align read/write bursts packets larger than 128 bytes */
48 #define USB_SBUSCFG_BAWR_ALIGN_128B (0x3 << 6)
49 #define USB_SBUSCFG_BARD_ALIGN_128B (0x3 << 3)
50 /* AHBBRST = 3 : Align AHB Burst to INCR16 (64 bytes) */
51 #define USB_SBUSCFG_AHBBRST_INCR16 (0x3 << 0)
53 #define USB_SBUSCFG_DEF_VAL (USB_SBUSCFG_BAWR_ALIGN_128B \
54 | USB_SBUSCFG_BARD_ALIGN_128B \
55 | USB_SBUSCFG_AHBBRST_INCR16)
57 #define DRIVER_DESC "EHCI orion driver"
59 #define hcd_to_orion_priv(h) ((struct orion_ehci_hcd *)hcd_to_ehci(h)->priv)
61 struct orion_ehci_hcd {
66 static struct hc_driver __read_mostly ehci_orion_hc_driver;
69 * Implement Orion USB controller specification guidelines
71 static void orion_usb_phy_v1_setup(struct usb_hcd *hcd)
73 /* The below GLs are according to the Orion Errata document */
75 * Clear interrupt cause and mask
83 wrl(USB_CMD, rdl(USB_CMD) | USB_CMD_RESET);
84 while (rdl(USB_CMD) & USB_CMD_RESET);
87 * GL# USB-10: Set IPG for non start of frame packets
90 wrl(USB_IPG, (rdl(USB_IPG) & ~0x7f00) | 0xc00);
93 * GL# USB-9: USB 2.0 Power Control
96 wrl(USB_PHY_PWR_CTRL, (rdl(USB_PHY_PWR_CTRL) & ~0xc0)| 0x40);
99 * GL# USB-1: USB PHY Tx Control - force calibration to '8'
100 * TXDATA_BLOCK_EN[21]=0x1, EXT_RCAL_EN[13]=0x1, IMP_CAL[6:3]=0x8
102 wrl(USB_PHY_TX_CTRL, (rdl(USB_PHY_TX_CTRL) & ~0x78) | 0x202040);
105 * GL# USB-3 GL# USB-9: USB PHY Rx Control
106 * RXDATA_BLOCK_LENGHT[31:30]=0x3, EDGE_DET_SEL[27:26]=0,
107 * CDR_FASTLOCK_EN[21]=0, DISCON_THRESHOLD[9:8]=0, SQ_THRESH[7:4]=0x1
109 wrl(USB_PHY_RX_CTRL, (rdl(USB_PHY_RX_CTRL) & ~0xc2003f0) | 0xc0000010);
112 * GL# USB-3 GL# USB-9: USB PHY IVREF Control
113 * PLLVDD12[1:0]=0x2, RXVDD[5:4]=0x3, Reserved[19]=0
115 wrl(USB_PHY_IVREF_CTRL, (rdl(USB_PHY_IVREF_CTRL) & ~0x80003 ) | 0x32);
118 * GL# USB-3 GL# USB-9: USB PHY Test Group Control
119 * REG_FIFO_SQ_RST[15]=0
121 wrl(USB_PHY_TST_GRP_CTRL, rdl(USB_PHY_TST_GRP_CTRL) & ~0x8000);
124 * Stop and reset controller
126 wrl(USB_CMD, rdl(USB_CMD) & ~USB_CMD_RUN);
127 wrl(USB_CMD, rdl(USB_CMD) | USB_CMD_RESET);
128 while (rdl(USB_CMD) & USB_CMD_RESET);
131 * GL# USB-5 Streaming disable REG_USB_MODE[4]=1
132 * TBD: This need to be done after each reset!
133 * GL# USB-4 Setup USB Host mode
135 wrl(USB_MODE, USB_MODE_SDIS | USB_MODE_HOST);
139 ehci_orion_conf_mbus_windows(struct usb_hcd *hcd,
140 const struct mbus_dram_target_info *dram)
144 for (i = 0; i < 4; i++) {
145 wrl(USB_WINDOW_CTRL(i), 0);
146 wrl(USB_WINDOW_BASE(i), 0);
149 for (i = 0; i < dram->num_cs; i++) {
150 const struct mbus_dram_window *cs = dram->cs + i;
152 wrl(USB_WINDOW_CTRL(i), ((cs->size - 1) & 0xffff0000) |
153 (cs->mbus_attr << 8) |
154 (dram->mbus_dram_target_id << 4) | 1);
155 wrl(USB_WINDOW_BASE(i), cs->base);
159 static int ehci_orion_drv_reset(struct usb_hcd *hcd)
161 struct device *dev = hcd->self.controller;
164 ret = ehci_setup(hcd);
169 * For SoC without hlock, need to program sbuscfg value to guarantee
170 * AHB master's burst would not overrun or underrun FIFO.
172 * sbuscfg reg has to be set after usb controller reset, otherwise
173 * the value would be override to 0.
175 if (of_device_is_compatible(dev->of_node, "marvell,armada-3700-ehci"))
176 wrl(USB_SBUSCFG, USB_SBUSCFG_DEF_VAL);
181 static int __maybe_unused ehci_orion_drv_suspend(struct device *dev)
183 struct usb_hcd *hcd = dev_get_drvdata(dev);
185 return ehci_suspend(hcd, device_may_wakeup(dev));
188 static int __maybe_unused ehci_orion_drv_resume(struct device *dev)
190 struct usb_hcd *hcd = dev_get_drvdata(dev);
192 return ehci_resume(hcd, false);
195 static SIMPLE_DEV_PM_OPS(ehci_orion_pm_ops, ehci_orion_drv_suspend,
196 ehci_orion_drv_resume);
198 static const struct ehci_driver_overrides orion_overrides __initconst = {
199 .extra_priv_size = sizeof(struct orion_ehci_hcd),
200 .reset = ehci_orion_drv_reset,
203 static int ehci_orion_drv_probe(struct platform_device *pdev)
205 struct orion_ehci_data *pd = dev_get_platdata(&pdev->dev);
206 const struct mbus_dram_target_info *dram;
207 struct resource *res;
209 struct ehci_hcd *ehci;
212 enum orion_ehci_phy_ver phy_version;
213 struct orion_ehci_hcd *priv;
218 pr_debug("Initializing Orion-SoC USB Host Controller\n");
220 irq = platform_get_irq(pdev, 0);
227 * Right now device-tree probed devices don't get dma_mask
228 * set. Since shared usb code relies on it, set it here for
229 * now. Once we have dma capability bindings this can go away.
231 err = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
235 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
241 hcd = usb_create_hcd(&ehci_orion_hc_driver,
242 &pdev->dev, dev_name(&pdev->dev));
248 hcd->rsrc_start = res->start;
249 hcd->rsrc_len = resource_size(res);
252 ehci = hcd_to_ehci(hcd);
253 ehci->caps = hcd->regs + 0x100;
256 priv = hcd_to_orion_priv(hcd);
258 * Not all platforms can gate the clock, so it is not an error if
259 * the clock does not exists.
261 priv->clk = devm_clk_get(&pdev->dev, NULL);
262 if (!IS_ERR(priv->clk)) {
263 err = clk_prepare_enable(priv->clk);
268 priv->phy = devm_phy_optional_get(&pdev->dev, "usb");
269 if (IS_ERR(priv->phy)) {
270 err = PTR_ERR(priv->phy);
276 * (Re-)program MBUS remapping windows if we are asked to.
278 dram = mv_mbus_dram_info();
280 ehci_orion_conf_mbus_windows(hcd, dram);
283 * setup Orion USB controller.
285 if (pdev->dev.of_node)
286 phy_version = EHCI_PHY_NA;
288 phy_version = pd->phy_version;
290 switch (phy_version) {
291 case EHCI_PHY_NA: /* dont change USB phy settings */
294 orion_usb_phy_v1_setup(hcd);
299 dev_warn(&pdev->dev, "USB phy version isn't supported.\n");
302 err = usb_add_hcd(hcd, irq, IRQF_SHARED);
306 device_wakeup_enable(hcd->self.controller);
310 if (!IS_ERR(priv->clk))
311 clk_disable_unprepare(priv->clk);
315 dev_err(&pdev->dev, "init %s fail, %d\n",
316 dev_name(&pdev->dev), err);
321 static void ehci_orion_drv_remove(struct platform_device *pdev)
323 struct usb_hcd *hcd = platform_get_drvdata(pdev);
324 struct orion_ehci_hcd *priv = hcd_to_orion_priv(hcd);
328 if (!IS_ERR(priv->clk))
329 clk_disable_unprepare(priv->clk);
334 static const struct of_device_id ehci_orion_dt_ids[] = {
335 { .compatible = "marvell,orion-ehci", },
336 { .compatible = "marvell,armada-3700-ehci", },
339 MODULE_DEVICE_TABLE(of, ehci_orion_dt_ids);
341 static struct platform_driver ehci_orion_driver = {
342 .probe = ehci_orion_drv_probe,
343 .remove_new = ehci_orion_drv_remove,
344 .shutdown = usb_hcd_platform_shutdown,
346 .name = "orion-ehci",
347 .of_match_table = ehci_orion_dt_ids,
348 .pm = &ehci_orion_pm_ops,
352 static int __init ehci_orion_init(void)
357 ehci_init_driver(&ehci_orion_hc_driver, &orion_overrides);
358 return platform_driver_register(&ehci_orion_driver);
360 module_init(ehci_orion_init);
362 static void __exit ehci_orion_cleanup(void)
364 platform_driver_unregister(&ehci_orion_driver);
366 module_exit(ehci_orion_cleanup);
368 MODULE_DESCRIPTION(DRIVER_DESC);
369 MODULE_ALIAS("platform:orion-ehci");
370 MODULE_AUTHOR("Tzachi Perelstein");
371 MODULE_LICENSE("GPL v2");