2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/clk.h>
13 #include <linux/mmc/host.h>
14 #include <linux/mmc/dw_mmc.h>
15 #include <linux/of_address.h>
16 #include <linux/slab.h>
19 #include "dw_mmc-pltfm.h"
21 #define RK3288_CLKGEN_DIV 2
23 struct dw_mci_rockchip_priv_data {
25 struct clk *sample_clk;
26 int default_sample_phase;
29 static void dw_mci_rockchip_prepare_command(struct dw_mci *host, u32 *cmdr)
31 *cmdr |= SDMMC_CMD_USE_HOLD_REG;
34 static int dw_mci_rk3288_setup_clock(struct dw_mci *host)
36 host->bus_hz /= RK3288_CLKGEN_DIV;
41 static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios)
43 struct dw_mci_rockchip_priv_data *priv = host->priv;
52 * cclkin: source clock of mmc controller
53 * bus_hz: card interface clock generated by CLKGEN
54 * bus_hz = cclkin / RK3288_CLKGEN_DIV
55 * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div))
57 * Note: div can only be 0 or 1
58 * if DDR50 8bit mode(only emmc work in 8bit mode),
61 if (ios->bus_width == MMC_BUS_WIDTH_8 &&
62 ios->timing == MMC_TIMING_MMC_DDR52)
63 cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV;
65 cclkin = ios->clock * RK3288_CLKGEN_DIV;
67 ret = clk_set_rate(host->ciu_clk, cclkin);
69 dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock);
71 bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV;
72 if (bus_hz != host->bus_hz) {
73 host->bus_hz = bus_hz;
74 /* force dw_mci_setup_bus() */
75 host->current_speed = 0;
78 /* Make sure we use phases which we can enumerate with */
79 if (!IS_ERR(priv->sample_clk))
80 clk_set_phase(priv->sample_clk, priv->default_sample_phase);
83 * Set the drive phase offset based on speed mode to achieve hold times.
85 * NOTE: this is _not_ a value that is dynamically tuned and is also
86 * _not_ a value that will vary from board to board. It is a value
87 * that could vary between different SoC models if they had massively
88 * different output clock delays inside their dw_mmc IP block (delay_o),
89 * but since it's OK to overshoot a little we don't need to do complex
90 * calculations and can pick values that will just work for everyone.
92 * When picking values we'll stick with picking 0/90/180/270 since
93 * those can be made very accurately on all known Rockchip SoCs.
95 * Note that these values match values from the DesignWare Databook
96 * tables for the most part except for SDR12 and "ID mode". For those
97 * two modes the databook calculations assume a clock in of 50MHz. As
98 * seen above, we always use a clock in rate that is exactly the
99 * card's input clock (times RK3288_CLKGEN_DIV, but that gets divided
100 * back out before the controller sees it).
102 * From measurement of a single device, it appears that delay_o is
103 * about .5 ns. Since we try to leave a bit of margin, it's expected
104 * that numbers here will be fine even with much larger delay_o
105 * (the 1.4 ns assumed by the DesignWare Databook would result in the
106 * same results, for instance).
108 if (!IS_ERR(priv->drv_clk)) {
112 * In almost all cases a 90 degree phase offset will provide
113 * sufficient hold times across all valid input clock rates
114 * assuming delay_o is not absurd for a given SoC. We'll use
119 switch (ios->timing) {
120 case MMC_TIMING_MMC_DDR52:
122 * Since clock in rate with MMC_DDR52 is doubled when
123 * bus width is 8 we need to double the phase offset
124 * to get the same timings.
126 if (ios->bus_width == MMC_BUS_WIDTH_8)
129 case MMC_TIMING_UHS_SDR104:
130 case MMC_TIMING_MMC_HS200:
132 * In the case of 150 MHz clock (typical max for
133 * Rockchip SoCs), 90 degree offset will add a delay
134 * of 1.67 ns. That will meet min hold time of .8 ns
135 * as long as clock output delay is < .87 ns. On
136 * SoCs measured this seems to be OK, but it doesn't
137 * hurt to give margin here, so we use 180.
143 clk_set_phase(priv->drv_clk, phase);
147 #define NUM_PHASES 360
148 #define TUNING_ITERATION_TO_PHASE(i) (DIV_ROUND_UP((i) * 360, NUM_PHASES))
150 static int dw_mci_rk3288_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
152 struct dw_mci *host = slot->host;
153 struct dw_mci_rockchip_priv_data *priv = host->priv;
154 struct mmc_host *mmc = slot->mmc;
157 bool v, prev_v = 0, first_v;
160 int end; /* inclusive */
162 struct range_t *ranges;
163 unsigned int range_count = 0;
164 int longest_range_len = -1;
165 int longest_range = -1;
168 if (IS_ERR(priv->sample_clk)) {
169 dev_err(host->dev, "Tuning clock (sample_clk) not defined.\n");
173 ranges = kmalloc_array(NUM_PHASES / 2 + 1, sizeof(*ranges), GFP_KERNEL);
177 /* Try each phase and extract good ranges */
178 for (i = 0; i < NUM_PHASES; ) {
179 clk_set_phase(priv->sample_clk, TUNING_ITERATION_TO_PHASE(i));
181 v = !mmc_send_tuning(mmc, opcode, NULL);
186 if ((!prev_v) && v) {
188 ranges[range_count-1].start = i;
191 ranges[range_count-1].end = i;
193 } else if (i == NUM_PHASES - 1) {
194 /* No extra skipping rules if we're at the end */
198 * No need to check too close to an invalid
199 * one since testing bad phases is slow. Skip
202 i += DIV_ROUND_UP(20 * NUM_PHASES, 360);
204 /* Always test the last one */
212 if (range_count == 0) {
213 dev_warn(host->dev, "All phases bad!");
218 /* wrap around case, merge the end points */
219 if ((range_count > 1) && first_v && v) {
220 ranges[0].start = ranges[range_count-1].start;
224 if (ranges[0].start == 0 && ranges[0].end == NUM_PHASES - 1) {
225 clk_set_phase(priv->sample_clk, priv->default_sample_phase);
226 dev_info(host->dev, "All phases work, using default phase %d.",
227 priv->default_sample_phase);
231 /* Find the longest range */
232 for (i = 0; i < range_count; i++) {
233 int len = (ranges[i].end - ranges[i].start + 1);
238 if (longest_range_len < len) {
239 longest_range_len = len;
243 dev_dbg(host->dev, "Good phase range %d-%d (%d len)\n",
244 TUNING_ITERATION_TO_PHASE(ranges[i].start),
245 TUNING_ITERATION_TO_PHASE(ranges[i].end),
250 dev_dbg(host->dev, "Best phase range %d-%d (%d len)\n",
251 TUNING_ITERATION_TO_PHASE(ranges[longest_range].start),
252 TUNING_ITERATION_TO_PHASE(ranges[longest_range].end),
256 middle_phase = ranges[longest_range].start + longest_range_len / 2;
257 middle_phase %= NUM_PHASES;
258 dev_info(host->dev, "Successfully tuned phase to %d\n",
259 TUNING_ITERATION_TO_PHASE(middle_phase));
261 clk_set_phase(priv->sample_clk,
262 TUNING_ITERATION_TO_PHASE(middle_phase));
269 static int dw_mci_rk3288_parse_dt(struct dw_mci *host)
271 struct device_node *np = host->dev->of_node;
272 struct dw_mci_rockchip_priv_data *priv;
274 priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
278 if (of_property_read_u32(np, "rockchip,default-sample-phase",
279 &priv->default_sample_phase))
280 priv->default_sample_phase = 0;
282 priv->drv_clk = devm_clk_get(host->dev, "ciu-drive");
283 if (IS_ERR(priv->drv_clk))
284 dev_dbg(host->dev, "ciu_drv not available\n");
286 priv->sample_clk = devm_clk_get(host->dev, "ciu-sample");
287 if (IS_ERR(priv->sample_clk))
288 dev_dbg(host->dev, "ciu_sample not available\n");
295 static int dw_mci_rockchip_init(struct dw_mci *host)
297 /* It is slot 8 on Rockchip SoCs */
300 /* It needs this quirk on all Rockchip SoCs */
301 host->pdata->quirks |= DW_MCI_QUIRK_BROKEN_DTO;
306 /* Common capabilities of RK3288 SoC */
307 static unsigned long dw_mci_rk3288_dwmmc_caps[4] = {
308 MMC_CAP_RUNTIME_RESUME, /* emmc */
309 MMC_CAP_RUNTIME_RESUME, /* sdmmc */
310 MMC_CAP_RUNTIME_RESUME, /* sdio0 */
311 MMC_CAP_RUNTIME_RESUME, /* sdio1 */
313 static const struct dw_mci_drv_data rk2928_drv_data = {
314 .prepare_command = dw_mci_rockchip_prepare_command,
315 .init = dw_mci_rockchip_init,
318 static const struct dw_mci_drv_data rk3288_drv_data = {
319 .caps = dw_mci_rk3288_dwmmc_caps,
320 .prepare_command = dw_mci_rockchip_prepare_command,
321 .set_ios = dw_mci_rk3288_set_ios,
322 .execute_tuning = dw_mci_rk3288_execute_tuning,
323 .parse_dt = dw_mci_rk3288_parse_dt,
324 .setup_clock = dw_mci_rk3288_setup_clock,
325 .init = dw_mci_rockchip_init,
328 static const struct of_device_id dw_mci_rockchip_match[] = {
329 { .compatible = "rockchip,rk2928-dw-mshc",
330 .data = &rk2928_drv_data },
331 { .compatible = "rockchip,rk3288-dw-mshc",
332 .data = &rk3288_drv_data },
335 MODULE_DEVICE_TABLE(of, dw_mci_rockchip_match);
337 static int dw_mci_rockchip_probe(struct platform_device *pdev)
339 const struct dw_mci_drv_data *drv_data;
340 const struct of_device_id *match;
342 if (!pdev->dev.of_node)
345 match = of_match_node(dw_mci_rockchip_match, pdev->dev.of_node);
346 drv_data = match->data;
348 return dw_mci_pltfm_register(pdev, drv_data);
351 #ifdef CONFIG_PM_SLEEP
352 static int dw_mci_rockchip_suspend(struct device *dev)
354 struct dw_mci *host = dev_get_drvdata(dev);
356 return dw_mci_suspend(host);
359 static int dw_mci_rockchip_resume(struct device *dev)
361 struct dw_mci *host = dev_get_drvdata(dev);
363 return dw_mci_resume(host);
365 #endif /* CONFIG_PM_SLEEP */
367 static SIMPLE_DEV_PM_OPS(dw_mci_rockchip_pmops,
368 dw_mci_rockchip_suspend,
369 dw_mci_rockchip_resume);
371 static struct platform_driver dw_mci_rockchip_pltfm_driver = {
372 .probe = dw_mci_rockchip_probe,
373 .remove = dw_mci_pltfm_remove,
375 .name = "dwmmc_rockchip",
376 .of_match_table = dw_mci_rockchip_match,
377 .pm = &dw_mci_rockchip_pmops,
381 module_platform_driver(dw_mci_rockchip_pltfm_driver);
383 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
384 MODULE_DESCRIPTION("Rockchip Specific DW-MSHC Driver Extension");
385 MODULE_ALIAS("platform:dwmmc_rockchip");
386 MODULE_LICENSE("GPL v2");