2 * Copyright (c) 2016 Hisilicon Limited.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef _HNS_ROCE_EQ_H
34 #define _HNS_ROCE_EQ_H
36 #define HNS_ROCE_CEQ 1
37 #define HNS_ROCE_AEQ 2
39 #define HNS_ROCE_CEQ_ENTRY_SIZE 0x4
40 #define HNS_ROCE_AEQ_ENTRY_SIZE 0x10
41 #define HNS_ROCE_CEQC_REG_OFFSET 0x18
43 #define HNS_ROCE_CEQ_DEFAULT_INTERVAL 0x10
44 #define HNS_ROCE_CEQ_DEFAULT_BURST_NUM 0x10
46 #define HNS_ROCE_INT_MASK_DISABLE 0
47 #define HNS_ROCE_INT_MASK_ENABLE 1
51 #define CONS_INDEX_MASK 0xffff
53 #define CEQ_REG_OFFSET 0x18
56 HNS_ROCE_EQ_STAT_INVALID = 0,
57 HNS_ROCE_EQ_STAT_VALID = 2,
60 struct hns_roce_aeqe {
96 #define HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S 16
97 #define HNS_ROCE_AEQE_U32_4_EVENT_TYPE_M \
98 (((1UL << 8) - 1) << HNS_ROCE_AEQE_U32_4_EVENT_TYPE_S)
100 #define HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S 24
101 #define HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_M \
102 (((1UL << 7) - 1) << HNS_ROCE_AEQE_U32_4_EVENT_SUB_TYPE_S)
104 #define HNS_ROCE_AEQE_U32_4_OWNER_S 31
106 #define HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S 0
107 #define HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_M \
108 (((1UL << 24) - 1) << HNS_ROCE_AEQE_EVENT_QP_EVENT_QP_QPN_S)
110 #define HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S 25
111 #define HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_M \
112 (((1UL << 3) - 1) << HNS_ROCE_AEQE_EVENT_QP_EVENT_PORT_NUM_S)
114 #define HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S 0
115 #define HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_M \
116 (((1UL << 16) - 1) << HNS_ROCE_AEQE_EVENT_CQ_EVENT_CQ_CQN_S)
118 #define HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_S 0
119 #define HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_M \
120 (((1UL << 5) - 1) << HNS_ROCE_AEQE_EVENT_CE_EVENT_CEQE_CEQN_S)
122 struct hns_roce_ceqe {
128 #define HNS_ROCE_CEQE_CEQE_COMP_OWNER_S 0
130 #define HNS_ROCE_CEQE_CEQE_COMP_CQN_S 16
131 #define HNS_ROCE_CEQE_CEQE_COMP_CQN_M \
132 (((1UL << 16) - 1) << HNS_ROCE_CEQE_CEQE_COMP_CQN_S)
134 #endif /* _HNS_ROCE_EQ_H */