2 * Support for Intel Camera Imaging ISP subsystem.
3 * Copyright (c) 2015, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #ifndef _hive_isp_css_defs_h__
16 #define _hive_isp_css_defs_h__
18 #define _HIVE_ISP_CSS_2401_SYSTEM 1
19 #define HIVE_ISP_CTRL_DATA_WIDTH 32
20 #define HIVE_ISP_CTRL_ADDRESS_WIDTH 32
21 #define HIVE_ISP_CTRL_MAX_BURST_SIZE 1
22 #define HIVE_ISP_DDR_ADDRESS_WIDTH 36
24 #define HIVE_ISP_HOST_MAX_BURST_SIZE 8 /* host supports bursts in order to prevent repeating DDRAM accesses */
25 #define HIVE_ISP_NUM_GPIO_PINS 12
27 /* This list of vector num_elems/elem_bits pairs is valid both in C as initializer
28 and in the DMA parameter list */
29 #define HIVE_ISP_DDR_DMA_SPECS {{32, 8}, {16, 16}, {18, 14}, {25, 10}, {21, 12}}
30 #define HIVE_ISP_DDR_WORD_BITS 256
31 #define HIVE_ISP_DDR_WORD_BYTES (HIVE_ISP_DDR_WORD_BITS/8)
32 #define HIVE_ISP_DDR_BYTES (512 * 1024 * 1024)
33 #define HIVE_ISP_DDR_BYTES_RTL (127 * 1024 * 1024)
34 #define HIVE_ISP_DDR_SMALL_BYTES (128 * 256 / 8)
35 #define HIVE_ISP_PAGE_SHIFT 12
36 #define HIVE_ISP_PAGE_SIZE (1<<HIVE_ISP_PAGE_SHIFT)
38 #define CSS_DDR_WORD_BITS HIVE_ISP_DDR_WORD_BITS
39 #define CSS_DDR_WORD_BYTES HIVE_ISP_DDR_WORD_BYTES
41 /* settings used in applications */
42 #define HIVE_XMEM_WIDTH HIVE_ISP_DDR_WORD_BITS
43 #define HIVE_VMEM_VECTOR_ELEMENTS 64
44 #define HIVE_VMEM_ELEMENT_BITS 14
45 #define HIVE_XMEM_ELEMENT_BITS 16
46 #define HIVE_VMEM_VECTOR_BYTES (HIVE_VMEM_VECTOR_ELEMENTS*HIVE_XMEM_ELEMENT_BITS/8) /* used for # addr bytes for one vector */
47 #define HIVE_XMEM_PACKED_WORD_VMEM_ELEMENTS (HIVE_XMEM_WIDTH/HIVE_VMEM_ELEMENT_BITS)
48 #define HIVE_XMEM_WORD_VMEM_ELEMENTS (HIVE_XMEM_WIDTH/HIVE_XMEM_ELEMENT_BITS)
49 #define XMEM_INT_SIZE 4
53 #define HIVE_ISYS_INP_BUFFER_BYTES (64*1024) /* 64 kByte = 2k words (of 256 bits) */
55 /* If HIVE_ISP_DDR_BASE_OFFSET is set to a non-zero value, the wide bus just before the DDRAM gets an extra dummy port where */
56 /* address range 0 .. HIVE_ISP_DDR_BASE_OFFSET-1 maps onto. This effectively creates an offset for the DDRAM from system perspective */
57 #define HIVE_ISP_DDR_BASE_OFFSET 0x120000000 /* 0x200000 */
59 #define HIVE_DMA_ISP_BUS_CONN 0
60 #define HIVE_DMA_ISP_DDR_CONN 1
61 #define HIVE_DMA_BUS_DDR_CONN 2
62 #define HIVE_DMA_ISP_MASTER master_port0
63 #define HIVE_DMA_BUS_MASTER master_port1
64 #define HIVE_DMA_DDR_MASTER master_port2
66 #define HIVE_DMA_NUM_CHANNELS 32 /* old value was 8 */
67 #define HIVE_DMA_CMD_FIFO_DEPTH 24 /* old value was 12 */
69 #define HIVE_IF_PIXEL_WIDTH 12
71 #define HIVE_MMU_TLB_SETS 8
72 #define HIVE_MMU_TLB_SET_BLOCKS 8
73 #define HIVE_MMU_TLB_BLOCK_ELEMENTS 8
74 #define HIVE_MMU_PAGE_TABLE_LEVELS 2
75 #define HIVE_MMU_PAGE_BYTES HIVE_ISP_PAGE_SIZE
77 #define HIVE_ISP_CH_ID_BITS 2
78 #define HIVE_ISP_FMT_TYPE_BITS 5
79 #define HIVE_ISP_ISEL_SEL_BITS 2
81 #define HIVE_GP_REGS_SDRAM_WAKEUP_IDX 0
82 #define HIVE_GP_REGS_IDLE_IDX 1
83 #define HIVE_GP_REGS_IRQ_0_IDX 2
84 #define HIVE_GP_REGS_IRQ_1_IDX 3
85 #define HIVE_GP_REGS_SP_STREAM_STAT_IDX 4
86 #define HIVE_GP_REGS_SP_STREAM_STAT_B_IDX 5
87 #define HIVE_GP_REGS_ISP_STREAM_STAT_IDX 6
88 #define HIVE_GP_REGS_MOD_STREAM_STAT_IDX 7
89 #define HIVE_GP_REGS_SP_STREAM_STAT_IRQ_COND_IDX 8
90 #define HIVE_GP_REGS_SP_STREAM_STAT_B_IRQ_COND_IDX 9
91 #define HIVE_GP_REGS_ISP_STREAM_STAT_IRQ_COND_IDX 10
92 #define HIVE_GP_REGS_MOD_STREAM_STAT_IRQ_COND_IDX 11
93 #define HIVE_GP_REGS_SP_STREAM_STAT_IRQ_ENABLE_IDX 12
94 #define HIVE_GP_REGS_SP_STREAM_STAT_B_IRQ_ENABLE_IDX 13
95 #define HIVE_GP_REGS_ISP_STREAM_STAT_IRQ_ENABLE_IDX 14
96 #define HIVE_GP_REGS_MOD_STREAM_STAT_IRQ_ENABLE_IDX 15
97 #define HIVE_GP_REGS_SWITCH_PRIM_IF_IDX 16
98 #define HIVE_GP_REGS_SWITCH_GDC1_IDX 17
99 #define HIVE_GP_REGS_SWITCH_GDC2_IDX 18
100 #define HIVE_GP_REGS_SRST_IDX 19
101 #define HIVE_GP_REGS_SLV_REG_SRST_IDX 20
102 #define HIVE_GP_REGS_SWITCH_ISYS_IDX 21
104 /* Bit numbers of the soft reset register */
105 #define HIVE_GP_REGS_SRST_ISYS_CBUS 0
106 #define HIVE_GP_REGS_SRST_ISEL_CBUS 1
107 #define HIVE_GP_REGS_SRST_IFMT_CBUS 2
108 #define HIVE_GP_REGS_SRST_GPDEV_CBUS 3
109 #define HIVE_GP_REGS_SRST_GPIO 4
110 #define HIVE_GP_REGS_SRST_TC 5
111 #define HIVE_GP_REGS_SRST_GPTIMER 6
112 #define HIVE_GP_REGS_SRST_FACELLFIFOS 7
113 #define HIVE_GP_REGS_SRST_D_OSYS 8
114 #define HIVE_GP_REGS_SRST_IFT_SEC_PIPE 9
115 #define HIVE_GP_REGS_SRST_GDC1 10
116 #define HIVE_GP_REGS_SRST_GDC2 11
117 #define HIVE_GP_REGS_SRST_VEC_BUS 12
118 #define HIVE_GP_REGS_SRST_ISP 13
119 #define HIVE_GP_REGS_SRST_SLV_GRP_BUS 14
120 #define HIVE_GP_REGS_SRST_DMA 15
121 #define HIVE_GP_REGS_SRST_SF_ISP_SP 16
122 #define HIVE_GP_REGS_SRST_SF_PIF_CELLS 17
123 #define HIVE_GP_REGS_SRST_SF_SIF_SP 18
124 #define HIVE_GP_REGS_SRST_SF_MC_SP 19
125 #define HIVE_GP_REGS_SRST_SF_ISYS_SP 20
126 #define HIVE_GP_REGS_SRST_SF_DMA_CELLS 21
127 #define HIVE_GP_REGS_SRST_SF_GDC1_CELLS 22
128 #define HIVE_GP_REGS_SRST_SF_GDC2_CELLS 23
129 #define HIVE_GP_REGS_SRST_SP 24
130 #define HIVE_GP_REGS_SRST_OCP2CIO 25
131 #define HIVE_GP_REGS_SRST_NBUS 26
132 #define HIVE_GP_REGS_SRST_HOST12BUS 27
133 #define HIVE_GP_REGS_SRST_WBUS 28
134 #define HIVE_GP_REGS_SRST_IC_OSYS 29
135 #define HIVE_GP_REGS_SRST_WBUS_IC 30
136 #define HIVE_GP_REGS_SRST_ISYS_INP_BUF_BUS 31
138 /* Bit numbers of the slave register soft reset register */
139 #define HIVE_GP_REGS_SLV_REG_SRST_DMA 0
140 #define HIVE_GP_REGS_SLV_REG_SRST_GDC1 1
141 #define HIVE_GP_REGS_SLV_REG_SRST_GDC2 2
143 /* order of the input bits for the irq controller */
144 #define HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID 0
145 #define HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID 1
146 #define HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID 2
147 #define HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID 3
148 #define HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID 4
149 #define HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID 5
150 #define HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID 6
151 #define HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID 7
152 #define HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID 8
153 #define HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID 9
154 #define HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID 10
155 #define HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID 11
156 #define HIVE_GP_DEV_IRQ_SP_BIT_ID 12
157 #define HIVE_GP_DEV_IRQ_ISP_BIT_ID 13
158 #define HIVE_GP_DEV_IRQ_ISYS_BIT_ID 14
159 #define HIVE_GP_DEV_IRQ_ISEL_BIT_ID 15
160 #define HIVE_GP_DEV_IRQ_IFMT_BIT_ID 16
161 #define HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID 17
162 #define HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID 18
163 #define HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID 19
164 #define HIVE_GP_DEV_IRQ_IS2401_BIT_ID 20
165 #define HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID 21
166 #define HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID 22
167 #define HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID 23
168 #define HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID 24
169 #define HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID 25
170 #define HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID 26
171 #define HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID 27
172 #define HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID 28
173 #define HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID 29
174 #define HIVE_GP_DEV_IRQ_DMA_BIT_ID 30
175 #define HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID 31
177 #define HIVE_GP_REGS_NUM_SW_IRQ_REGS 2
179 /* order of the input bits for the timed controller */
180 #define HIVE_GP_DEV_TC_GPIO_PIN_0_BIT_ID 0
181 #define HIVE_GP_DEV_TC_GPIO_PIN_1_BIT_ID 1
182 #define HIVE_GP_DEV_TC_GPIO_PIN_2_BIT_ID 2
183 #define HIVE_GP_DEV_TC_GPIO_PIN_3_BIT_ID 3
184 #define HIVE_GP_DEV_TC_GPIO_PIN_4_BIT_ID 4
185 #define HIVE_GP_DEV_TC_GPIO_PIN_5_BIT_ID 5
186 #define HIVE_GP_DEV_TC_GPIO_PIN_6_BIT_ID 6
187 #define HIVE_GP_DEV_TC_GPIO_PIN_7_BIT_ID 7
188 #define HIVE_GP_DEV_TC_GPIO_PIN_8_BIT_ID 8
189 #define HIVE_GP_DEV_TC_GPIO_PIN_9_BIT_ID 9
190 #define HIVE_GP_DEV_TC_GPIO_PIN_10_BIT_ID 10
191 #define HIVE_GP_DEV_TC_GPIO_PIN_11_BIT_ID 11
192 #define HIVE_GP_DEV_TC_SP_BIT_ID 12
193 #define HIVE_GP_DEV_TC_ISP_BIT_ID 13
194 #define HIVE_GP_DEV_TC_ISYS_BIT_ID 14
195 #define HIVE_GP_DEV_TC_ISEL_BIT_ID 15
196 #define HIVE_GP_DEV_TC_IFMT_BIT_ID 16
197 #define HIVE_GP_DEV_TC_GP_TIMER_0_BIT_ID 17
198 #define HIVE_GP_DEV_TC_GP_TIMER_1_BIT_ID 18
199 #define HIVE_GP_DEV_TC_MIPI_SOL_BIT_ID 19
200 #define HIVE_GP_DEV_TC_MIPI_EOL_BIT_ID 20
201 #define HIVE_GP_DEV_TC_MIPI_SOF_BIT_ID 21
202 #define HIVE_GP_DEV_TC_MIPI_EOF_BIT_ID 22
203 #define HIVE_GP_DEV_TC_INPSYS_SM 23
205 /* definitions for the gp_timer block */
206 #define HIVE_GP_TIMER_0 0
207 #define HIVE_GP_TIMER_1 1
208 #define HIVE_GP_TIMER_2 2
209 #define HIVE_GP_TIMER_3 3
210 #define HIVE_GP_TIMER_4 4
211 #define HIVE_GP_TIMER_5 5
212 #define HIVE_GP_TIMER_6 6
213 #define HIVE_GP_TIMER_7 7
214 #define HIVE_GP_TIMER_NUM_COUNTERS 8
216 #define HIVE_GP_TIMER_IRQ_0 0
217 #define HIVE_GP_TIMER_IRQ_1 1
218 #define HIVE_GP_TIMER_NUM_IRQS 2
220 #define HIVE_GP_TIMER_GPIO_0_BIT_ID 0
221 #define HIVE_GP_TIMER_GPIO_1_BIT_ID 1
222 #define HIVE_GP_TIMER_GPIO_2_BIT_ID 2
223 #define HIVE_GP_TIMER_GPIO_3_BIT_ID 3
224 #define HIVE_GP_TIMER_GPIO_4_BIT_ID 4
225 #define HIVE_GP_TIMER_GPIO_5_BIT_ID 5
226 #define HIVE_GP_TIMER_GPIO_6_BIT_ID 6
227 #define HIVE_GP_TIMER_GPIO_7_BIT_ID 7
228 #define HIVE_GP_TIMER_GPIO_8_BIT_ID 8
229 #define HIVE_GP_TIMER_GPIO_9_BIT_ID 9
230 #define HIVE_GP_TIMER_GPIO_10_BIT_ID 10
231 #define HIVE_GP_TIMER_GPIO_11_BIT_ID 11
232 #define HIVE_GP_TIMER_INP_SYS_IRQ 12
233 #define HIVE_GP_TIMER_ISEL_IRQ 13
234 #define HIVE_GP_TIMER_IFMT_IRQ 14
235 #define HIVE_GP_TIMER_SP_STRMON_IRQ 15
236 #define HIVE_GP_TIMER_SP_B_STRMON_IRQ 16
237 #define HIVE_GP_TIMER_ISP_STRMON_IRQ 17
238 #define HIVE_GP_TIMER_MOD_STRMON_IRQ 18
239 #define HIVE_GP_TIMER_IS2401_IRQ 19
240 #define HIVE_GP_TIMER_ISP_BAMEM_ERROR_IRQ 20
241 #define HIVE_GP_TIMER_ISP_DMEM_ERROR_IRQ 21
242 #define HIVE_GP_TIMER_SP_ICACHE_MEM_ERROR_IRQ 22
243 #define HIVE_GP_TIMER_SP_DMEM_ERROR_IRQ 23
244 #define HIVE_GP_TIMER_SP_OUT_RUN_DP 24
245 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I0 25
246 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I1 26
247 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I2 27
248 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I3 28
249 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I4 29
250 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I5 30
251 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I6 31
252 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I7 32
253 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I8 33
254 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I9 34
255 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I0_I10 35
256 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I1_I0 36
257 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I2_I0 37
258 #define HIVE_GP_TIMER_SP_WIRE_DEBUG_LM_MSINK_RUN_I3_I0 38
259 #define HIVE_GP_TIMER_ISP_OUT_RUN_DP 39
260 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I0_I0 40
261 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I0_I1 41
262 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I1_I0 42
263 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I0 43
264 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I1 44
265 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I2 45
266 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I3 46
267 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I4 47
268 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I5 48
269 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I2_I6 49
270 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I3_I0 50
271 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I4_I0 51
272 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I5_I0 52
273 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I6_I0 53
274 #define HIVE_GP_TIMER_ISP_WIRE_DEBUG_LM_MSINK_RUN_I7_I0 54
275 #define HIVE_GP_TIMER_MIPI_SOL_BIT_ID 55
276 #define HIVE_GP_TIMER_MIPI_EOL_BIT_ID 56
277 #define HIVE_GP_TIMER_MIPI_SOF_BIT_ID 57
278 #define HIVE_GP_TIMER_MIPI_EOF_BIT_ID 58
279 #define HIVE_GP_TIMER_INPSYS_SM 59
280 #define HIVE_GP_TIMER_ISP_PMEM_ERROR_IRQ 60
282 /* port definitions for the streaming monitors */
283 /* port definititions SP streaming monitor, monitors the status of streaming ports at the SP side of the streaming FIFO's */
284 #define SP_STR_MON_PORT_SP2SIF 0
285 #define SP_STR_MON_PORT_SIF2SP 1
286 #define SP_STR_MON_PORT_SP2MC 2
287 #define SP_STR_MON_PORT_MC2SP 3
288 #define SP_STR_MON_PORT_SP2DMA 4
289 #define SP_STR_MON_PORT_DMA2SP 5
290 #define SP_STR_MON_PORT_SP2ISP 6
291 #define SP_STR_MON_PORT_ISP2SP 7
292 #define SP_STR_MON_PORT_SP2GPD 8
293 #define SP_STR_MON_PORT_FA2SP 9
294 #define SP_STR_MON_PORT_SP2ISYS 10
295 #define SP_STR_MON_PORT_ISYS2SP 11
296 #define SP_STR_MON_PORT_SP2PIFA 12
297 #define SP_STR_MON_PORT_PIFA2SP 13
298 #define SP_STR_MON_PORT_SP2PIFB 14
299 #define SP_STR_MON_PORT_PIFB2SP 15
301 #define SP_STR_MON_PORT_B_SP2GDC1 0
302 #define SP_STR_MON_PORT_B_GDC12SP 1
303 #define SP_STR_MON_PORT_B_SP2GDC2 2
304 #define SP_STR_MON_PORT_B_GDC22SP 3
306 /* previously used SP streaming monitor port identifiers, kept for backward compatibility */
307 #define SP_STR_MON_PORT_SND_SIF SP_STR_MON_PORT_SP2SIF
308 #define SP_STR_MON_PORT_RCV_SIF SP_STR_MON_PORT_SIF2SP
309 #define SP_STR_MON_PORT_SND_MC SP_STR_MON_PORT_SP2MC
310 #define SP_STR_MON_PORT_RCV_MC SP_STR_MON_PORT_MC2SP
311 #define SP_STR_MON_PORT_SND_DMA SP_STR_MON_PORT_SP2DMA
312 #define SP_STR_MON_PORT_RCV_DMA SP_STR_MON_PORT_DMA2SP
313 #define SP_STR_MON_PORT_SND_ISP SP_STR_MON_PORT_SP2ISP
314 #define SP_STR_MON_PORT_RCV_ISP SP_STR_MON_PORT_ISP2SP
315 #define SP_STR_MON_PORT_SND_GPD SP_STR_MON_PORT_SP2GPD
316 #define SP_STR_MON_PORT_RCV_GPD SP_STR_MON_PORT_FA2SP
318 #define SP_STR_MON_PORT_SND_PIF SP_STR_MON_PORT_SP2PIFA
319 #define SP_STR_MON_PORT_RCV_PIF SP_STR_MON_PORT_PIFA2SP
320 #define SP_STR_MON_PORT_SND_PIFB SP_STR_MON_PORT_SP2PIFB
321 #define SP_STR_MON_PORT_RCV_PIFB SP_STR_MON_PORT_PIFB2SP
323 #define SP_STR_MON_PORT_SND_PIF_A SP_STR_MON_PORT_SP2PIFA
324 #define SP_STR_MON_PORT_RCV_PIF_A SP_STR_MON_PORT_PIFA2SP
325 #define SP_STR_MON_PORT_SND_PIF_B SP_STR_MON_PORT_SP2PIFB
326 #define SP_STR_MON_PORT_RCV_PIF_B SP_STR_MON_PORT_PIFB2SP
328 /* port definititions ISP streaming monitor, monitors the status of streaming ports at the ISP side of the streaming FIFO's */
329 #define ISP_STR_MON_PORT_ISP2PIFA 0
330 #define ISP_STR_MON_PORT_PIFA2ISP 1
331 #define ISP_STR_MON_PORT_ISP2PIFB 2
332 #define ISP_STR_MON_PORT_PIFB2ISP 3
333 #define ISP_STR_MON_PORT_ISP2DMA 4
334 #define ISP_STR_MON_PORT_DMA2ISP 5
335 #define ISP_STR_MON_PORT_ISP2GDC1 6
336 #define ISP_STR_MON_PORT_GDC12ISP 7
337 #define ISP_STR_MON_PORT_ISP2GDC2 8
338 #define ISP_STR_MON_PORT_GDC22ISP 9
339 #define ISP_STR_MON_PORT_ISP2GPD 10
340 #define ISP_STR_MON_PORT_FA2ISP 11
341 #define ISP_STR_MON_PORT_ISP2SP 12
342 #define ISP_STR_MON_PORT_SP2ISP 13
344 /* previously used ISP streaming monitor port identifiers, kept for backward compatibility */
345 #define ISP_STR_MON_PORT_SND_PIF_A ISP_STR_MON_PORT_ISP2PIFA
346 #define ISP_STR_MON_PORT_RCV_PIF_A ISP_STR_MON_PORT_PIFA2ISP
347 #define ISP_STR_MON_PORT_SND_PIF_B ISP_STR_MON_PORT_ISP2PIFB
348 #define ISP_STR_MON_PORT_RCV_PIF_B ISP_STR_MON_PORT_PIFB2ISP
349 #define ISP_STR_MON_PORT_SND_DMA ISP_STR_MON_PORT_ISP2DMA
350 #define ISP_STR_MON_PORT_RCV_DMA ISP_STR_MON_PORT_DMA2ISP
351 #define ISP_STR_MON_PORT_SND_GDC ISP_STR_MON_PORT_ISP2GDC1
352 #define ISP_STR_MON_PORT_RCV_GDC ISP_STR_MON_PORT_GDC12ISP
353 #define ISP_STR_MON_PORT_SND_GPD ISP_STR_MON_PORT_ISP2GPD
354 #define ISP_STR_MON_PORT_RCV_GPD ISP_STR_MON_PORT_FA2ISP
355 #define ISP_STR_MON_PORT_SND_SP ISP_STR_MON_PORT_ISP2SP
356 #define ISP_STR_MON_PORT_RCV_SP ISP_STR_MON_PORT_SP2ISP
358 /* port definititions MOD streaming monitor, monitors the status of streaming ports at the module side of the streaming FIFO's */
360 #define MOD_STR_MON_PORT_PIFA2CELLS 0
361 #define MOD_STR_MON_PORT_CELLS2PIFA 1
362 #define MOD_STR_MON_PORT_PIFB2CELLS 2
363 #define MOD_STR_MON_PORT_CELLS2PIFB 3
364 #define MOD_STR_MON_PORT_SIF2SP 4
365 #define MOD_STR_MON_PORT_SP2SIF 5
366 #define MOD_STR_MON_PORT_MC2SP 6
367 #define MOD_STR_MON_PORT_SP2MC 7
368 #define MOD_STR_MON_PORT_DMA2ISP 8
369 #define MOD_STR_MON_PORT_ISP2DMA 9
370 #define MOD_STR_MON_PORT_DMA2SP 10
371 #define MOD_STR_MON_PORT_SP2DMA 11
372 #define MOD_STR_MON_PORT_GDC12CELLS 12
373 #define MOD_STR_MON_PORT_CELLS2GDC1 13
374 #define MOD_STR_MON_PORT_GDC22CELLS 14
375 #define MOD_STR_MON_PORT_CELLS2GDC2 15
377 #define MOD_STR_MON_PORT_SND_PIF_A 0
378 #define MOD_STR_MON_PORT_RCV_PIF_A 1
379 #define MOD_STR_MON_PORT_SND_PIF_B 2
380 #define MOD_STR_MON_PORT_RCV_PIF_B 3
381 #define MOD_STR_MON_PORT_SND_SIF 4
382 #define MOD_STR_MON_PORT_RCV_SIF 5
383 #define MOD_STR_MON_PORT_SND_MC 6
384 #define MOD_STR_MON_PORT_RCV_MC 7
385 #define MOD_STR_MON_PORT_SND_DMA2ISP 8
386 #define MOD_STR_MON_PORT_RCV_DMA_FR_ISP 9
387 #define MOD_STR_MON_PORT_SND_DMA2SP 10
388 #define MOD_STR_MON_PORT_RCV_DMA_FR_SP 11
389 #define MOD_STR_MON_PORT_SND_GDC 12
390 #define MOD_STR_MON_PORT_RCV_GDC 13
393 /* testbench signals: */
395 /* testbench GP adapter register ids */
396 #define HIVE_TESTBENCH_GPIO_DATA_OUT_REG_IDX 0
397 #define HIVE_TESTBENCH_GPIO_DIR_OUT_REG_IDX 1
398 #define HIVE_TESTBENCH_IRQ_REG_IDX 2
399 #define HIVE_TESTBENCH_SDRAM_WAKEUP_REG_IDX 3
400 #define HIVE_TESTBENCH_IDLE_REG_IDX 4
401 #define HIVE_TESTBENCH_GPIO_DATA_IN_REG_IDX 5
402 #define HIVE_TESTBENCH_MIPI_BFM_EN_REG_IDX 6
403 #define HIVE_TESTBENCH_CSI_CONFIG_REG_IDX 7
404 #define HIVE_TESTBENCH_DDR_STALL_EN_REG_IDX 8
406 #define HIVE_TESTBENCH_ISP_PMEM_ERROR_IRQ_REG_IDX 9
407 #define HIVE_TESTBENCH_ISP_BAMEM_ERROR_IRQ_REG_IDX 10
408 #define HIVE_TESTBENCH_ISP_DMEM_ERROR_IRQ_REG_IDX 11
409 #define HIVE_TESTBENCH_SP_ICACHE_MEM_ERROR_IRQ_REG_IDX 12
410 #define HIVE_TESTBENCH_SP_DMEM_ERROR_IRQ_REG_IDX 13
412 #define HIVE_TESTBENCH_MIPI_PARPATHEN_REG_IDX 14
413 #define HIVE_TESTBENCH_FB_HPLL_FREQ_REG_IDX 15
414 #define HIVE_TESTBENCH_ISCLK_RATIO_REG_IDX 16
416 /* Signal monitor input bit ids */
417 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_O_BIT_ID 0
418 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_1_BIT_ID 1
419 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_2_BIT_ID 2
420 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_3_BIT_ID 3
421 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_4_BIT_ID 4
422 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_5_BIT_ID 5
423 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_6_BIT_ID 6
424 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_7_BIT_ID 7
425 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_8_BIT_ID 8
426 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_9_BIT_ID 9
427 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_10_BIT_ID 10
428 #define HIVE_TESTBENCH_SIG_MON_GPIO_PIN_11_BIT_ID 11
429 #define HIVE_TESTBENCH_SIG_MON_IRQ_PIN_BIT_ID 12
430 #define HIVE_TESTBENCH_SIG_MON_SDRAM_WAKEUP_PIN_BIT_ID 13
431 #define HIVE_TESTBENCH_SIG_MON_IDLE_PIN_BIT_ID 14
433 #define ISP2400_DEBUG_NETWORK 1
435 #endif /* _hive_isp_css_defs_h__ */