2 * linux/sound/soc/m8m/hi6210_i2s.c - I2S IP driver
4 * Copyright (C) 2015 Linaro, Ltd
5 * Author: Andy Green <andy.green@linaro.org>
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * This driver only deals with S2 interface (BT)
19 #include <linux/init.h>
20 #include <linux/module.h>
21 #include <linux/device.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <linux/jiffies.h>
26 #include <linux/gpio.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/dmaengine_pcm.h>
31 #include <sound/initval.h>
32 #include <sound/soc.h>
33 #include <linux/interrupt.h>
34 #include <linux/reset.h>
35 #include <linux/of_address.h>
36 #include <linux/of_irq.h>
37 #include <linux/mfd/syscon.h>
38 #include <linux/reset-controller.h>
40 #include "hi6210-i2s.h"
44 struct reset_control *rc;
47 struct snd_soc_dai_driver dai;
49 struct regmap *sysctrl;
50 phys_addr_t base_phys;
51 struct snd_dmaengine_dai_dma_data dma_data[2];
65 #define SC_PERIPH_CLKEN1 0x210
66 #define SC_PERIPH_CLKDIS1 0x214
68 #define SC_PERIPH_CLKEN3 0x230
69 #define SC_PERIPH_CLKDIS3 0x234
71 #define SC_PERIPH_CLKEN12 0x270
72 #define SC_PERIPH_CLKDIS12 0x274
74 #define SC_PERIPH_RSTEN1 0x310
75 #define SC_PERIPH_RSTDIS1 0x314
76 #define SC_PERIPH_RSTSTAT1 0x318
78 #define SC_PERIPH_RSTEN2 0x320
79 #define SC_PERIPH_RSTDIS2 0x324
80 #define SC_PERIPH_RSTSTAT2 0x328
82 #define SOC_PMCTRL_BBPPLLALIAS 0x48
89 static inline void hi6210_write_reg(struct hi6210_i2s *i2s, int reg, u32 val)
91 writel(val, i2s->base + reg);
94 static inline u32 hi6210_read_reg(struct hi6210_i2s *i2s, int reg)
96 return readl(i2s->base + reg);
99 static int hi6210_i2s_startup(struct snd_pcm_substream *substream,
100 struct snd_soc_dai *cpu_dai)
102 struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
106 /* deassert reset on ABB */
107 regmap_read(i2s->sysctrl, SC_PERIPH_RSTSTAT2, &val);
109 regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS2, BIT(4));
111 for (n = 0; n < i2s->clocks; n++) {
112 ret = clk_prepare_enable(i2s->clk[n]);
114 goto err_unprepare_clk;
117 ret = clk_set_rate(i2s->clk[CLK_I2S_BASE], 49152000);
119 dev_err(i2s->dev, "%s: setting 49.152MHz base rate failed %d\n",
121 goto err_unprepare_clk;
124 /* enable clock before frequency division */
125 regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN12, BIT(9));
127 /* enable codec working clock / == "codec bus clock" */
128 regmap_write(i2s->sysctrl, SC_PERIPH_CLKEN1, BIT(5));
130 /* deassert reset on codec / interface clock / working clock */
131 regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));
132 regmap_write(i2s->sysctrl, SC_PERIPH_RSTDIS1, BIT(5));
134 /* not interested in i2s irqs */
135 val = hi6210_read_reg(i2s, HII2S_CODEC_IRQ_MASK);
137 hi6210_write_reg(i2s, HII2S_CODEC_IRQ_MASK, val);
140 /* reset the stereo downlink fifo */
141 val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);
142 val |= (BIT(5) | BIT(4));
143 hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);
145 val = hi6210_read_reg(i2s, HII2S_APB_AFIFO_CFG_1);
146 val &= ~(BIT(5) | BIT(4));
147 hi6210_write_reg(i2s, HII2S_APB_AFIFO_CFG_1, val);
150 val = hi6210_read_reg(i2s, HII2S_SW_RST_N);
151 val &= ~(HII2S_SW_RST_N__ST_DL_WORDLEN_MASK <<
152 HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT);
153 val |= (HII2S_BITS_16 << HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT);
154 hi6210_write_reg(i2s, HII2S_SW_RST_N, val);
156 val = hi6210_read_reg(i2s, HII2S_MISC_CFG);
157 /* mux 11/12 = APB not i2s */
158 val &= ~HII2S_MISC_CFG__ST_DL_TEST_SEL;
159 /* BT R ch 0 = mixer op of DACR ch */
160 val &= ~HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL;
161 val &= ~HII2S_MISC_CFG__S2_DOUT_TEST_SEL;
163 val |= HII2S_MISC_CFG__S2_DOUT_RIGHT_SEL;
164 /* BT L ch = 1 = mux 7 = "mixer output of DACL */
165 val |= HII2S_MISC_CFG__S2_DOUT_TEST_SEL;
166 hi6210_write_reg(i2s, HII2S_MISC_CFG, val);
168 val = hi6210_read_reg(i2s, HII2S_SW_RST_N);
169 val |= HII2S_SW_RST_N__SW_RST_N;
170 hi6210_write_reg(i2s, HII2S_SW_RST_N, val);
176 clk_disable_unprepare(i2s->clk[n]);
180 static void hi6210_i2s_shutdown(struct snd_pcm_substream *substream,
181 struct snd_soc_dai *cpu_dai)
183 struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
186 for (n = 0; n < i2s->clocks; n++)
187 clk_disable_unprepare(i2s->clk[n]);
189 regmap_write(i2s->sysctrl, SC_PERIPH_RSTEN1, BIT(5));
192 static void hi6210_i2s_txctrl(struct snd_soc_dai *cpu_dai, int on)
194 struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
197 spin_lock(&i2s->lock);
200 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
201 val |= HII2S_I2S_CFG__S2_IF_TX_EN;
202 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
205 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
206 val &= ~HII2S_I2S_CFG__S2_IF_TX_EN;
207 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
209 spin_unlock(&i2s->lock);
212 static void hi6210_i2s_rxctrl(struct snd_soc_dai *cpu_dai, int on)
214 struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
217 spin_lock(&i2s->lock);
219 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
220 val |= HII2S_I2S_CFG__S2_IF_RX_EN;
221 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
223 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
224 val &= ~HII2S_I2S_CFG__S2_IF_RX_EN;
225 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
227 spin_unlock(&i2s->lock);
230 static int hi6210_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
232 struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
235 * We don't actually set the hardware until the hw_params
236 * call, but we need to validate the user input here.
238 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
239 case SND_SOC_DAIFMT_CBM_CFM:
240 case SND_SOC_DAIFMT_CBS_CFS:
246 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
247 case SND_SOC_DAIFMT_I2S:
248 case SND_SOC_DAIFMT_LEFT_J:
249 case SND_SOC_DAIFMT_RIGHT_J:
256 i2s->master = (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) ==
257 SND_SOC_DAIFMT_CBS_CFS;
262 static int hi6210_i2s_hw_params(struct snd_pcm_substream *substream,
263 struct snd_pcm_hw_params *params,
264 struct snd_soc_dai *cpu_dai)
266 struct hi6210_i2s *i2s = dev_get_drvdata(cpu_dai->dev);
267 u32 bits = 0, rate = 0, signed_data = 0, fmt = 0;
269 struct snd_dmaengine_dai_dma_data *dma_data;
271 switch (params_format(params)) {
272 case SNDRV_PCM_FORMAT_U16_LE:
273 signed_data = HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
275 case SNDRV_PCM_FORMAT_S16_LE:
276 bits = HII2S_BITS_16;
278 case SNDRV_PCM_FORMAT_U24_LE:
279 signed_data = HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
281 case SNDRV_PCM_FORMAT_S24_LE:
282 bits = HII2S_BITS_24;
285 dev_err(cpu_dai->dev, "Bad format\n");
290 switch (params_rate(params)) {
292 rate = HII2S_FS_RATE_8KHZ;
295 rate = HII2S_FS_RATE_16KHZ;
298 rate = HII2S_FS_RATE_32KHZ;
301 rate = HII2S_FS_RATE_48KHZ;
304 rate = HII2S_FS_RATE_96KHZ;
307 rate = HII2S_FS_RATE_192KHZ;
310 dev_err(cpu_dai->dev, "Bad rate: %d\n", params_rate(params));
314 if (!(params_channels(params))) {
315 dev_err(cpu_dai->dev, "Bad channels\n");
319 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
324 dma_data->addr_width = 3;
328 dma_data->addr_width = 2;
331 i2s->rate = params_rate(params);
332 i2s->channels = params_channels(params);
333 i2s->channel_length = i2s->channels * i2s->bits;
335 val = hi6210_read_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG);
336 val &= ~((HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_MASK <<
337 HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT) |
338 (HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_MASK <<
339 HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT) |
340 (HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_MASK <<
341 HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT) |
342 (HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_MASK <<
343 HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT));
344 val |= ((16 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AEMPTY_SHIFT) |
345 (30 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_R_AFULL_SHIFT) |
346 (16 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AEMPTY_SHIFT) |
347 (30 << HII2S_ST_DL_FIFO_TH_CFG__ST_DL_L_AFULL_SHIFT));
348 hi6210_write_reg(i2s, HII2S_ST_DL_FIFO_TH_CFG, val);
351 val = hi6210_read_reg(i2s, HII2S_IF_CLK_EN_CFG);
352 val |= (BIT(19) | BIT(18) | BIT(17) |
353 HII2S_IF_CLK_EN_CFG__S2_IF_CLK_EN |
354 HII2S_IF_CLK_EN_CFG__S2_OL_MIXER_EN |
355 HII2S_IF_CLK_EN_CFG__S2_OL_SRC_EN |
356 HII2S_IF_CLK_EN_CFG__ST_DL_R_EN |
357 HII2S_IF_CLK_EN_CFG__ST_DL_L_EN);
358 hi6210_write_reg(i2s, HII2S_IF_CLK_EN_CFG, val);
361 val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG);
362 val &= ~(HII2S_DIG_FILTER_CLK_EN_CFG__DACR_SDM_EN |
363 HII2S_DIG_FILTER_CLK_EN_CFG__DACR_HBF2I_EN |
364 HII2S_DIG_FILTER_CLK_EN_CFG__DACR_AGC_EN |
365 HII2S_DIG_FILTER_CLK_EN_CFG__DACL_SDM_EN |
366 HII2S_DIG_FILTER_CLK_EN_CFG__DACL_HBF2I_EN |
367 HII2S_DIG_FILTER_CLK_EN_CFG__DACL_AGC_EN);
368 val |= (HII2S_DIG_FILTER_CLK_EN_CFG__DACR_MIXER_EN |
369 HII2S_DIG_FILTER_CLK_EN_CFG__DACL_MIXER_EN);
370 hi6210_write_reg(i2s, HII2S_DIG_FILTER_CLK_EN_CFG, val);
373 val = hi6210_read_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG);
374 val &= ~(HII2S_DIG_FILTER_MODULE_CFG__DACR_MIXER_IN2_MUTE |
375 HII2S_DIG_FILTER_MODULE_CFG__DACL_MIXER_IN2_MUTE);
376 hi6210_write_reg(i2s, HII2S_DIG_FILTER_MODULE_CFG, val);
378 val = hi6210_read_reg(i2s, HII2S_MUX_TOP_MODULE_CFG);
379 val &= ~(HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN1_MUTE |
380 HII2S_MUX_TOP_MODULE_CFG__S2_OL_MIXER_IN2_MUTE |
381 HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN1_MUTE |
382 HII2S_MUX_TOP_MODULE_CFG__VOICE_DLINK_MIXER_IN2_MUTE);
383 hi6210_write_reg(i2s, HII2S_MUX_TOP_MODULE_CFG, val);
386 switch (i2s->format & SND_SOC_DAIFMT_MASTER_MASK) {
387 case SND_SOC_DAIFMT_CBM_CFM:
389 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
390 val |= HII2S_I2S_CFG__S2_MST_SLV;
391 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
393 case SND_SOC_DAIFMT_CBS_CFS:
395 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
396 val &= ~HII2S_I2S_CFG__S2_MST_SLV;
397 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
400 WARN_ONCE(1, "Invalid i2s->fmt MASTER_MASK. This shouldn't happen\n");
404 switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
405 case SND_SOC_DAIFMT_I2S:
406 fmt = HII2S_FORMAT_I2S;
408 case SND_SOC_DAIFMT_LEFT_J:
409 fmt = HII2S_FORMAT_LEFT_JUST;
411 case SND_SOC_DAIFMT_RIGHT_J:
412 fmt = HII2S_FORMAT_RIGHT_JUST;
415 WARN_ONCE(1, "Invalid i2s->fmt FORMAT_MASK. This shouldn't happen\n");
419 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
420 val &= ~(HII2S_I2S_CFG__S2_FUNC_MODE_MASK <<
421 HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT);
422 val |= fmt << HII2S_I2S_CFG__S2_FUNC_MODE_SHIFT;
423 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
426 val = hi6210_read_reg(i2s, HII2S_CLK_SEL);
427 val &= ~(HII2S_CLK_SEL__I2S_BT_FM_SEL | /* BT gets the I2S */
428 HII2S_CLK_SEL__EXT_12_288MHZ_SEL);
429 hi6210_write_reg(i2s, HII2S_CLK_SEL, val);
431 dma_data->maxburst = 2;
433 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
434 dma_data->addr = i2s->base_phys + HII2S_ST_DL_CHANNEL;
436 dma_data->addr = i2s->base_phys + HII2S_STEREO_UPLINK_CHANNEL;
438 switch (i2s->channels) {
440 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
441 val |= HII2S_I2S_CFG__S2_FRAME_MODE;
442 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
445 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
446 val &= ~HII2S_I2S_CFG__S2_FRAME_MODE;
447 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
451 /* clear loopback, set signed type and word length */
452 val = hi6210_read_reg(i2s, HII2S_I2S_CFG);
453 val &= ~HII2S_I2S_CFG__S2_CODEC_DATA_FORMAT;
454 val &= ~(HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_MASK <<
455 HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT);
456 val &= ~(HII2S_I2S_CFG__S2_DIRECT_LOOP_MASK <<
457 HII2S_I2S_CFG__S2_DIRECT_LOOP_SHIFT);
459 val |= (bits << HII2S_I2S_CFG__S2_CODEC_IO_WORDLENGTH_SHIFT);
460 hi6210_write_reg(i2s, HII2S_I2S_CFG, val);
466 /* set DAC and related units to correct rate */
467 val = hi6210_read_reg(i2s, HII2S_FS_CFG);
468 val &= ~(HII2S_FS_CFG__FS_S2_MASK << HII2S_FS_CFG__FS_S2_SHIFT);
469 val &= ~(HII2S_FS_CFG__FS_DACLR_MASK << HII2S_FS_CFG__FS_DACLR_SHIFT);
470 val &= ~(HII2S_FS_CFG__FS_ST_DL_R_MASK <<
471 HII2S_FS_CFG__FS_ST_DL_R_SHIFT);
472 val &= ~(HII2S_FS_CFG__FS_ST_DL_L_MASK <<
473 HII2S_FS_CFG__FS_ST_DL_L_SHIFT);
474 val |= (rate << HII2S_FS_CFG__FS_S2_SHIFT);
475 val |= (rate << HII2S_FS_CFG__FS_DACLR_SHIFT);
476 val |= (rate << HII2S_FS_CFG__FS_ST_DL_R_SHIFT);
477 val |= (rate << HII2S_FS_CFG__FS_ST_DL_L_SHIFT);
478 hi6210_write_reg(i2s, HII2S_FS_CFG, val);
483 static int hi6210_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
484 struct snd_soc_dai *cpu_dai)
486 pr_debug("%s\n", __func__);
488 case SNDRV_PCM_TRIGGER_START:
489 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
490 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
491 hi6210_i2s_rxctrl(cpu_dai, 1);
493 hi6210_i2s_txctrl(cpu_dai, 1);
495 case SNDRV_PCM_TRIGGER_STOP:
496 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
497 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
498 hi6210_i2s_rxctrl(cpu_dai, 0);
500 hi6210_i2s_txctrl(cpu_dai, 0);
503 dev_err(cpu_dai->dev, "unknown cmd\n");
509 static int hi6210_i2s_dai_probe(struct snd_soc_dai *dai)
511 struct hi6210_i2s *i2s = snd_soc_dai_get_drvdata(dai);
513 snd_soc_dai_init_dma_data(dai,
514 &i2s->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
515 &i2s->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
521 static const struct snd_soc_dai_ops hi6210_i2s_dai_ops = {
522 .trigger = hi6210_i2s_trigger,
523 .hw_params = hi6210_i2s_hw_params,
524 .set_fmt = hi6210_i2s_set_fmt,
525 .startup = hi6210_i2s_startup,
526 .shutdown = hi6210_i2s_shutdown,
529 static const struct snd_soc_dai_driver hi6210_i2s_dai_init = {
530 .probe = hi6210_i2s_dai_probe,
534 .formats = SNDRV_PCM_FMTBIT_S16_LE |
535 SNDRV_PCM_FMTBIT_U16_LE,
536 .rates = SNDRV_PCM_RATE_48000,
541 .formats = SNDRV_PCM_FMTBIT_S16_LE |
542 SNDRV_PCM_FMTBIT_U16_LE,
543 .rates = SNDRV_PCM_RATE_48000,
545 .ops = &hi6210_i2s_dai_ops,
548 static const struct snd_soc_component_driver hi6210_i2s_i2s_comp = {
549 .name = "hi6210_i2s-i2s",
552 static int hi6210_i2s_probe(struct platform_device *pdev)
554 struct device_node *node = pdev->dev.of_node;
555 struct device *dev = &pdev->dev;
556 struct hi6210_i2s *i2s;
557 struct resource *res;
560 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
565 spin_lock_init(&i2s->lock);
567 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
568 i2s->base = devm_ioremap_resource(dev, res);
569 if (IS_ERR(i2s->base))
570 return PTR_ERR(i2s->base);
572 i2s->base_phys = (phys_addr_t)res->start;
573 i2s->dai = hi6210_i2s_dai_init;
575 dev_set_drvdata(&pdev->dev, i2s);
577 i2s->sysctrl = syscon_regmap_lookup_by_phandle(node,
578 "hisilicon,sysctrl-syscon");
579 if (IS_ERR(i2s->sysctrl))
580 return PTR_ERR(i2s->sysctrl);
582 i2s->clk[CLK_DACODEC] = devm_clk_get(&pdev->dev, "dacodec");
583 if (IS_ERR_OR_NULL(i2s->clk[CLK_DACODEC]))
584 return PTR_ERR(i2s->clk[CLK_DACODEC]);
587 i2s->clk[CLK_I2S_BASE] = devm_clk_get(&pdev->dev, "i2s-base");
588 if (IS_ERR_OR_NULL(i2s->clk[CLK_I2S_BASE]))
589 return PTR_ERR(i2s->clk[CLK_I2S_BASE]);
592 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
596 ret = devm_snd_soc_register_component(&pdev->dev, &hi6210_i2s_i2s_comp,
601 static const struct of_device_id hi6210_i2s_dt_ids[] = {
602 { .compatible = "hisilicon,hi6210-i2s" },
606 MODULE_DEVICE_TABLE(of, hi6210_i2s_dt_ids);
608 static struct platform_driver hi6210_i2s_driver = {
609 .probe = hi6210_i2s_probe,
611 .name = "hi6210_i2s",
612 .of_match_table = hi6210_i2s_dt_ids,
616 module_platform_driver(hi6210_i2s_driver);
618 MODULE_DESCRIPTION("Hisilicon HI6210 I2S driver");
619 MODULE_AUTHOR("Andy Green <andy.green@linaro.org>");
620 MODULE_LICENSE("GPL");