3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
15 * This file contains the entry point for the 64-bit kernel along
16 * with some early initialization code common to all 64-bit powerpc
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
25 #include <linux/threads.h>
26 #include <linux/init.h>
30 #include <asm/ppc_asm.h>
31 #include <asm/head-64.h>
32 #include <asm/asm-offsets.h>
34 #include <asm/cputable.h>
35 #include <asm/setup.h>
36 #include <asm/hvcall.h>
37 #include <asm/thread_info.h>
38 #include <asm/firmware.h>
39 #include <asm/page_64.h>
40 #include <asm/irqflags.h>
41 #include <asm/kvm_book3s_asm.h>
42 #include <asm/ptrace.h>
43 #include <asm/hw_irq.h>
44 #include <asm/cputhreads.h>
45 #include <asm/ppc-opcode.h>
46 #include <asm/export.h>
47 #include <asm/feature-fixups.h>
49 /* The physical memory is laid out such that the secondary processor
50 * spin code sits at 0x0000...0x00ff. On server, the vectors follow
51 * using the layout described in exceptions-64s.S
55 * Entering into this code we make the following assumptions:
57 * For pSeries or server processors:
58 * 1. The MMU is off & open firmware is running in real mode.
59 * 2. The primary CPU enters at __start.
60 * 3. If the RTAS supports "query-cpu-stopped-state", then secondary
61 * CPUs will enter as directed by "start-cpu" RTAS call, which is
62 * generic_secondary_smp_init, with PIR in r3.
63 * 4. Else the secondary CPUs will enter at secondary_hold (0x60) as
64 * directed by the "start-cpu" RTS call, with PIR in r3.
65 * -or- For OPAL entry:
66 * 1. The MMU is off, processor in HV mode.
67 * 2. The primary CPU enters at 0 with device-tree in r3, OPAL base
68 * in r8, and entry in r9 for debugging purposes.
69 * 3. Secondary CPUs enter as directed by OPAL_START_CPU call, which
70 * is at generic_secondary_smp_init, with PIR in r3.
72 * For Book3E processors:
73 * 1. The MMU is on running in AS0 in a state defined in ePAPR
74 * 2. The kernel is entered at __start
77 OPEN_FIXED_SECTION(first_256B, 0x0, 0x100)
78 USE_FIXED_SECTION(first_256B)
80 * Offsets are relative from the start of fixed section, and
81 * first_256B starts at 0. Offsets are a bit easier to use here
82 * than the fixed section entry macros.
86 /* NOP this out unconditionally */
89 b __start_initialization_multiplatform
92 /* Catch branch to 0 in real mode */
95 /* Secondary processors spin on this value until it becomes non-zero.
96 * When non-zero, it contains the real address of the function the cpu
100 .globl __secondary_hold_spinloop
101 __secondary_hold_spinloop:
104 /* Secondary processors write this value with their cpu # */
105 /* after they enter the spin loop immediately below. */
106 .globl __secondary_hold_acknowledge
107 __secondary_hold_acknowledge:
110 #ifdef CONFIG_RELOCATABLE
111 /* This flag is set to 1 by a loader if the kernel should run
112 * at the loaded address instead of the linked address. This
113 * is used by kexec-tools to keep the the kdump kernel in the
114 * crash_kernel region. The loader is responsible for
115 * observing the alignment requirement.
118 #ifdef CONFIG_RELOCATABLE_TEST
119 #define RUN_AT_LOAD_DEFAULT 1 /* Test relocation, do not copy to 0 */
121 #define RUN_AT_LOAD_DEFAULT 0x72756e30 /* "run0" -- relocate to 0 by default */
124 /* Do not move this variable as kexec-tools knows about it. */
128 DEFINE_FIXED_SYMBOL(__run_at_load)
129 .long RUN_AT_LOAD_DEFAULT
134 * The following code is used to hold secondary processors
135 * in a spin loop after they have entered the kernel, but
136 * before the bulk of the kernel has been relocated. This code
137 * is relocated to physical address 0x60 before prom_init is run.
138 * All of it must fit below the first exception vector at 0x100.
139 * Use .globl here not _GLOBAL because we want __secondary_hold
140 * to be the actual text address, not a descriptor.
142 .globl __secondary_hold
145 #ifndef CONFIG_PPC_BOOK3E
148 mtmsrd r24 /* RI on */
150 /* Grab our physical cpu number */
152 /* stash r4 for book3e */
155 /* Tell the master cpu we're here */
156 /* Relocation is off & we are located at an address less */
157 /* than 0x100, so only need to grab low order offset. */
158 std r24,(ABS_ADDR(__secondary_hold_acknowledge))(0)
162 #ifdef CONFIG_PPC_BOOK3E
165 /* All secondary cpus wait here until told to start. */
166 100: ld r12,(ABS_ADDR(__secondary_hold_spinloop))(r26)
170 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
171 #ifdef CONFIG_PPC_BOOK3E
177 * it may be the case that other platforms have r4 right to
178 * begin with, this gives us some safety in case it is not
180 #ifdef CONFIG_PPC_BOOK3E
185 /* Make sure that patched code is visible */
191 CLOSE_FIXED_SECTION(first_256B)
193 /* This value is used to mark exception frames on the stack. */
196 .tc ID_72656773_68657265[TC],0x7265677368657265
200 * On server, we include the exception vectors code here as it
201 * relies on absolute addressing which is only possible within
202 * this compilation unit
204 #ifdef CONFIG_PPC_BOOK3S
205 #include "exceptions-64s.S"
207 OPEN_TEXT_SECTION(0x100)
212 #ifdef CONFIG_PPC_BOOK3E
214 * The booting_thread_hwid holds the thread id we want to boot in cpu
215 * hotplug case. It is set by cpu hotplug code, and is invalid by default.
216 * The thread id is the same as the initial value of SPRN_PIR[THREAD_ID]
219 .globl booting_thread_hwid
221 .long INVALID_THREAD_HWID
224 * start a thread in the same core
226 * r3 = the thread physical id
227 * r4 = the entry point where thread starts
229 _GLOBAL(book3e_start_thread)
230 LOAD_REG_IMMEDIATE(r5, MSR_KERNEL)
235 /* If the thread id is invalid, just exit. */
253 * stop a thread in the same core
255 * r3 = the thread physical id
257 _GLOBAL(book3e_stop_thread)
262 /* If the thread id is invalid, just exit. */
271 _GLOBAL(fsl_secondary_thread_init)
274 /* Enable branch prediction */
276 ori r3,r3,BUCSR_INIT@l
281 * Fix PIR to match the linear numbering in the device tree.
283 * On e6500, the reset value of PIR uses the low three bits for
284 * the thread within a core, and the upper bits for the core
285 * number. There are two threads per core, so shift everything
286 * but the low bit right by two bits so that the cpu numbering is
289 * If the old value of BUCSR is non-zero, this thread has run
290 * before. Thus, we assume we are coming from kexec or a similar
291 * scenario, and PIR is already set to the correct value. This
292 * is a bit of a hack, but there are limited opportunities for
293 * getting information into the thread and the alternatives
294 * seemed like they'd be overkill. We can't tell just by looking
295 * at the old PIR value which state it's in, since the same value
296 * could be valid for one thread out of reset and for a different
303 rlwimi r3, r3, 30, 2, 30
308 _GLOBAL(generic_secondary_thread_init)
311 /* turn on 64-bit mode */
314 /* get a valid TOC pointer, wherever we're mapped at */
318 #ifdef CONFIG_PPC_BOOK3E
319 /* Book3E initialization */
321 bl book3e_secondary_thread_init
323 b generic_secondary_common_init
326 * On pSeries and most other platforms, secondary processors spin
327 * in the following code.
328 * At entry, r3 = this processor's number (physical cpu id)
330 * On Book3E, r4 = 1 to indicate that the initial TLB entry for
331 * this core already exists (setup via some other mechanism such
332 * as SCOM before entry).
334 _GLOBAL(generic_secondary_smp_init)
339 /* turn on 64-bit mode */
342 /* get a valid TOC pointer, wherever we're mapped at */
346 #ifdef CONFIG_PPC_BOOK3E
347 /* Book3E initialization */
350 bl book3e_secondary_core_init
353 * After common core init has finished, check if the current thread is the
354 * one we wanted to boot. If not, start the specified thread and stop the
357 LOAD_REG_ADDR(r4, booting_thread_hwid)
359 li r5, INVALID_THREAD_HWID
364 * The value of booting_thread_hwid has been stored in r3,
365 * so make it invalid.
370 * Get the current thread id and check if it is the one we wanted.
371 * If not, start the one specified in booting_thread_hwid and stop
372 * the current thread.
378 /* start the specified thread */
379 LOAD_REG_ADDR(r5, fsl_secondary_thread_init)
381 bl book3e_start_thread
383 /* stop the current thread */
385 bl book3e_stop_thread
391 generic_secondary_common_init:
392 /* Set up a paca value for this processor. Since we have the
393 * physical cpu id in r24, we need to search the pacas to find
394 * which logical id maps to our physical one.
397 b kexec_wait /* wait for next kernel if !SMP */
399 LOAD_REG_ADDR(r8, paca_ptrs) /* Load paca_ptrs pointe */
400 ld r8,0(r8) /* Get base vaddr of array */
401 LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */
402 lwz r7,0(r7) /* also the max paca allocated */
403 li r5,0 /* logical cpu id */
405 sldi r9,r5,3 /* get paca_ptrs[] index from cpu id */
406 ldx r13,r9,r8 /* r13 = paca_ptrs[cpu id] */
407 lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
408 cmpw r6,r24 /* Compare to our id */
411 cmpw r5,r7 /* Check if more pacas exist */
414 mr r3,r24 /* not found, copy phys to r3 */
415 b kexec_wait /* next kernel might do better */
418 #ifdef CONFIG_PPC_BOOK3E
419 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */
420 mtspr SPRN_SPRG_TLB_EXFRAME,r12
423 /* From now on, r24 is expected to be logical cpuid */
426 /* Create a temp kernel stack for use before relocation is on. */
427 ld r1,PACAEMERGSP(r13)
428 subi r1,r1,STACK_FRAME_OVERHEAD
430 /* See if we need to call a cpu state restore handler */
431 LOAD_REG_ADDR(r23, cur_cpu_spec)
433 ld r12,CPU_SPEC_RESTORE(r23)
436 #ifdef PPC64_ELF_ABI_v1
442 3: LOAD_REG_ADDR(r3, spinning_secondaries) /* Decrement spinning_secondaries */
450 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
453 beq 4b /* Loop until told to go */
455 sync /* order paca.run and cur_cpu_spec */
456 isync /* In case code patching happened */
463 * Assumes we're mapped EA == RA if the MMU is on.
465 #ifdef CONFIG_PPC_BOOK3S
468 andi. r0,r3,MSR_IR|MSR_DR
476 b . /* prevent speculative execution */
481 * Here is our main kernel entry point. We support currently 2 kind of entries
482 * depending on the value of r5.
484 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
487 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
488 * DT block, r4 is a physical pointer to the kernel itself
491 __start_initialization_multiplatform:
492 /* Make sure we are running in 64 bits mode */
495 /* Get TOC pointer (current runtime address) */
498 /* find out where we are now */
500 0: mflr r26 /* r26 = runtime addr here */
501 addis r26,r26,(_stext - 0b)@ha
502 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
505 * Are we booted from a PROM Of-type client-interface ?
509 b __boot_from_prom /* yes -> prom */
511 /* Save parameters */
514 #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
515 /* Save OPAL entry */
520 #ifdef CONFIG_PPC_BOOK3E
521 bl start_initialization_book3e
524 /* Setup some critical 970 SPRs before switching MMU off */
527 cmpwi r0,0x39 /* 970 */
529 cmpwi r0,0x3c /* 970FX */
531 cmpwi r0,0x44 /* 970MP */
533 cmpwi r0,0x45 /* 970GX */
535 1: bl __cpu_preinit_ppc970
538 /* Switch off MMU if not already off */
541 #endif /* CONFIG_PPC_BOOK3E */
544 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
545 /* Save parameters */
553 * Align the stack to 16-byte boundary
554 * Depending on the size and layout of the ELF sections in the initial
555 * boot binary, the stack pointer may be unaligned on PowerMac
559 #ifdef CONFIG_RELOCATABLE
560 /* Relocate code for where we are now */
565 /* Restore parameters */
572 /* Do all of the interaction with OF client interface */
575 #endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */
577 /* We never return. We also hit that trap if trying to boot
578 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
582 #ifdef CONFIG_RELOCATABLE
583 /* process relocations for the final address of the kernel */
584 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */
586 #if defined(CONFIG_PPC_BOOK3E)
587 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
589 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
590 #if defined(CONFIG_PPC_BOOK3E)
593 cmplwi cr0,r7,1 /* flagged to stay where we are ? */
598 #if defined(CONFIG_PPC_BOOK3E)
599 /* IVPR needs to be set after relocation. */
605 * We need to run with _stext at physical address PHYSICAL_START.
606 * This will leave some code in the first 256B of
607 * real memory, which are reserved for software use.
609 * Note: This process overwrites the OF exception vectors.
611 li r3,0 /* target addr */
612 #ifdef CONFIG_PPC_BOOK3E
613 tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */
615 mr. r4,r26 /* In some cases the loader may */
616 #if defined(CONFIG_PPC_BOOK3E)
619 beq 9f /* have already put us at zero */
620 li r6,0x100 /* Start offset, the first 0x100 */
621 /* bytes were copied earlier. */
623 #ifdef CONFIG_RELOCATABLE
625 * Check if the kernel has to be running as relocatable kernel based on the
626 * variable __run_at_load, if it is set the kernel is treated as relocatable
627 * kernel, otherwise it will be moved to PHYSICAL_START
629 #if defined(CONFIG_PPC_BOOK3E)
630 tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
632 lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
636 #ifdef CONFIG_PPC_BOOK3E
637 LOAD_REG_ADDR(r5, __end_interrupts)
638 LOAD_REG_ADDR(r11, _stext)
641 /* just copy interrupts */
642 LOAD_REG_IMMEDIATE(r5, FIXED_SYMBOL_ABS_ADDR(__end_interrupts))
647 /* # bytes of memory to copy */
648 lis r5,(ABS_ADDR(copy_to_here))@ha
649 addi r5,r5,(ABS_ADDR(copy_to_here))@l
651 bl copy_and_flush /* copy the first n bytes */
652 /* this includes the code being */
654 /* Jump to the copy of this code that we just made */
655 addis r8,r3,(ABS_ADDR(4f))@ha
656 addi r12,r8,(ABS_ADDR(4f))@l
661 p_end: .8byte _end - copy_to_here
665 * Now copy the rest of the kernel up to _end, add
666 * _end - copy_to_here to the copy limit and run again.
668 addis r8,r26,(ABS_ADDR(p_end))@ha
669 ld r8,(ABS_ADDR(p_end))@l(r8)
671 5: bl copy_and_flush /* copy the rest */
673 9: b start_here_multiplatform
676 * Copy routine used to copy the kernel to start at physical address 0
677 * and flush and invalidate the caches as needed.
678 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
679 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
681 * Note: this routine *only* clobbers r0, r6 and lr
683 _GLOBAL(copy_and_flush)
686 4: li r0,8 /* Use the smallest common */
687 /* denominator cache line */
688 /* size. This results in */
689 /* extra cache line flushes */
690 /* but operation is correct. */
691 /* Can't get cache line size */
692 /* from NACA as it is being */
695 mtctr r0 /* put # words/line in ctr */
696 3: addi r6,r6,8 /* copy a cache line */
700 dcbst r6,r3 /* write it to memory */
702 icbi r6,r3 /* flush the icache line */
715 #ifdef CONFIG_PPC_PMAC
717 * On PowerMac, secondary processors starts from the reset vector, which
718 * is temporarily turned into a call to one of the functions below.
723 .globl __secondary_start_pmac_0
724 __secondary_start_pmac_0:
725 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
735 _GLOBAL(pmac_secondary_start)
736 /* turn on 64-bit mode */
741 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
748 /* get TOC pointer (real address) */
752 /* Copy some CPU settings from CPU 0 */
753 bl __restore_cpu_ppc970
755 /* pSeries do that early though I don't think we really need it */
758 mtmsrd r3 /* RI on */
760 /* Set up a paca value for this processor. */
761 LOAD_REG_ADDR(r4,paca_ptrs) /* Load paca pointer */
762 ld r4,0(r4) /* Get base vaddr of paca_ptrs array */
763 sldi r5,r24,3 /* get paca_ptrs[] index from cpu id */
764 ldx r13,r5,r4 /* r13 = paca_ptrs[cpu id] */
765 SET_PACA(r13) /* Save vaddr of paca in an SPRG*/
767 /* Mark interrupts soft and hard disabled (they might be enabled
768 * in the PACA when doing hotplug)
771 stb r0,PACAIRQSOFTMASK(r13)
772 li r0,PACA_IRQ_HARD_DIS
773 stb r0,PACAIRQHAPPENED(r13)
775 /* Create a temp kernel stack for use before relocation is on. */
776 ld r1,PACAEMERGSP(r13)
777 subi r1,r1,STACK_FRAME_OVERHEAD
781 #endif /* CONFIG_PPC_PMAC */
784 * This function is called after the master CPU has released the
785 * secondary processors. The execution environment is relocation off.
786 * The paca for this processor has the following fields initialized at
788 * 1. Processor number
789 * 2. Segment table pointer (virtual address)
790 * On entry the following are set:
791 * r1 = stack pointer (real addr of temp stack)
792 * r24 = cpu# (in Linux terms)
793 * r13 = paca virtual address
794 * SPRG_PACA = paca virtual address
799 .globl __secondary_start
801 /* Set thread priority to MEDIUM */
804 /* Initialize the kernel stack */
805 LOAD_REG_ADDR(r3, current_set)
806 sldi r28,r24,3 /* get current_set[cpu#] */
808 addi r14,r14,THREAD_SIZE-STACK_FRAME_OVERHEAD
809 std r14,PACAKSAVE(r13)
811 /* Do early setup for that CPU (SLB and hash table pointer) */
812 bl early_setup_secondary
815 * setup the new stack pointer, but *don't* use this until
820 /* Clear backchain so we get nice backtraces */
824 /* Mark interrupts soft and hard disabled (they might be enabled
825 * in the PACA when doing hotplug)
828 stb r7,PACAIRQSOFTMASK(r13)
829 li r0,PACA_IRQ_HARD_DIS
830 stb r0,PACAIRQHAPPENED(r13)
832 /* enable MMU and jump to start_secondary */
833 LOAD_REG_ADDR(r3, start_secondary_prolog)
834 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
839 b . /* prevent speculative execution */
842 * Running with relocation on at this point. All we want to do is
843 * zero the stack back-chain pointer and get the TOC virtual address
844 * before going into C code.
846 start_secondary_prolog:
849 std r3,0(r1) /* Zero the stack frame pointer */
853 * Reset stack pointer and call start_secondary
854 * to continue with online operation when woken up
855 * from cede in cpu offline.
857 _GLOBAL(start_secondary_resume)
858 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */
860 std r3,0(r1) /* Zero the stack frame pointer */
866 * This subroutine clobbers r11 and r12
869 mfmsr r11 /* grab the current MSR */
870 #ifdef CONFIG_PPC_BOOK3E
871 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */
873 #else /* CONFIG_PPC_BOOK3E */
874 li r12,(MSR_64BIT | MSR_ISF)@highest
883 * This puts the TOC pointer into r2, offset by 0x8000 (as expected
884 * by the toolchain). It computes the correct value for wherever we
885 * are running at the moment, using position-independent code.
887 * Note: The compiler constructs pointers using offsets from the
888 * TOC in -mcmodel=medium mode. After we relocate to 0 but before
889 * the MMU is on we need our TOC to be a virtual address otherwise
890 * these pointers will be real addresses which may get stored and
891 * accessed later with the MMU on. We use tovirt() at the call
892 * sites to handle this.
894 _GLOBAL(relative_toc)
898 ld r2,(p_toc - 0b)(r11)
904 p_toc: .8byte __toc_start + 0x8000 - 0b
907 * This is where the main kernel code starts.
910 start_here_multiplatform:
915 /* Clear out the BSS. It may have been done in prom_init,
916 * already but that's irrelevant since prom_init will soon
917 * be detached from the kernel completely. Besides, we need
918 * to clear it now for kexec-style entry.
920 LOAD_REG_ADDR(r11,__bss_stop)
921 LOAD_REG_ADDR(r8,__bss_start)
922 sub r11,r11,r8 /* bss size */
923 addi r11,r11,7 /* round up to an even double word */
924 srdi. r11,r11,3 /* shift right by 3 */
928 mtctr r11 /* zero this many doublewords */
933 #ifdef CONFIG_PPC_EARLY_DEBUG_OPAL
934 /* Setup OPAL entry */
935 LOAD_REG_ADDR(r11, opal)
940 #ifndef CONFIG_PPC_BOOK3E
943 mtmsrd r6 /* RI on */
946 #ifdef CONFIG_RELOCATABLE
947 /* Save the physical address we're running at in kernstart_addr */
948 LOAD_REG_ADDR(r4, kernstart_addr)
953 /* set up a stack pointer */
954 LOAD_REG_ADDR(r3,init_thread_union)
955 LOAD_REG_IMMEDIATE(r1,THREAD_SIZE)
958 stdu r0,-STACK_FRAME_OVERHEAD(r1)
961 * Do very early kernel initializations, including initial hash table
962 * and SLB setup before we turn on relocation.
965 /* Restore parameters passed from prom_init/kexec */
967 LOAD_REG_ADDR(r12, DOTSYM(early_setup))
969 bctrl /* also sets r13 and SPRG_PACA */
971 LOAD_REG_ADDR(r3, start_here_common)
976 b . /* prevent speculative execution */
979 /* This is where all platforms converge execution */
982 /* relocation is on at this point */
983 std r1,PACAKSAVE(r13)
985 /* Load the TOC (virtual address) */
988 /* Mark interrupts soft and hard disabled (they might be enabled
989 * in the PACA when doing hotplug)
992 stb r0,PACAIRQSOFTMASK(r13)
993 li r0,PACA_IRQ_HARD_DIS
994 stb r0,PACAIRQHAPPENED(r13)
996 /* Generic kernel entry */
1003 * We put a few things here that have to be page-aligned.
1004 * This stuff goes at the beginning of the bss, which is page-aligned.
1008 * pgd dir should be aligned to PGD_TABLE_SIZE which is 64K.
1009 * We will need to find a better way to fix this
1013 .globl swapper_pg_dir
1015 .space PGD_TABLE_SIZE
1017 .globl empty_zero_page
1020 EXPORT_SYMBOL(empty_zero_page)