4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
8 * Modifications for the OpenRISC architecture:
9 * Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
10 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
18 #include <linux/linkage.h>
19 #include <linux/threads.h>
20 #include <linux/errno.h>
21 #include <linux/init.h>
22 #include <linux/serial_reg.h>
23 #include <asm/processor.h>
26 #include <asm/pgtable.h>
27 #include <asm/thread_info.h>
28 #include <asm/cache.h>
29 #include <asm/spr_defs.h>
30 #include <asm/asm-offsets.h>
31 #include <linux/of_fdt.h>
33 #define tophys(rd,rs) \
34 l.movhi rd,hi(-KERNELBASE) ;\
37 #define CLEAR_GPR(gpr) \
40 #define LOAD_SYMBOL_2_GPR(gpr,symbol) \
41 l.movhi gpr,hi(symbol) ;\
42 l.ori gpr,gpr,lo(symbol)
45 #define UART_BASE_ADD 0x90000000
47 #define EXCEPTION_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_SM)
48 #define SYSCALL_SR (SPR_SR_DME | SPR_SR_IME | SPR_SR_DCE | SPR_SR_ICE | SPR_SR_IEE | SPR_SR_TEE | SPR_SR_SM)
50 /* ============================================[ tmp store locations ]=== */
52 #define SPR_SHADOW_GPR(x) ((x) + SPR_GPR_BASE + 32)
55 * emergency_print temporary stores
57 #ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
58 #define EMERGENCY_PRINT_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(14)
59 #define EMERGENCY_PRINT_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(14)
61 #define EMERGENCY_PRINT_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(15)
62 #define EMERGENCY_PRINT_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(15)
64 #define EMERGENCY_PRINT_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(16)
65 #define EMERGENCY_PRINT_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(16)
67 #define EMERGENCY_PRINT_STORE_GPR7 l.mtspr r0,r7,SPR_SHADOW_GPR(7)
68 #define EMERGENCY_PRINT_LOAD_GPR7 l.mfspr r7,r0,SPR_SHADOW_GPR(7)
70 #define EMERGENCY_PRINT_STORE_GPR8 l.mtspr r0,r8,SPR_SHADOW_GPR(8)
71 #define EMERGENCY_PRINT_LOAD_GPR8 l.mfspr r8,r0,SPR_SHADOW_GPR(8)
73 #define EMERGENCY_PRINT_STORE_GPR9 l.mtspr r0,r9,SPR_SHADOW_GPR(9)
74 #define EMERGENCY_PRINT_LOAD_GPR9 l.mfspr r9,r0,SPR_SHADOW_GPR(9)
76 #else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
77 #define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
78 #define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0)
80 #define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5
81 #define EMERGENCY_PRINT_LOAD_GPR5 l.lwz r5,0x24(r0)
83 #define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6
84 #define EMERGENCY_PRINT_LOAD_GPR6 l.lwz r6,0x28(r0)
86 #define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7
87 #define EMERGENCY_PRINT_LOAD_GPR7 l.lwz r7,0x2c(r0)
89 #define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8
90 #define EMERGENCY_PRINT_LOAD_GPR8 l.lwz r8,0x30(r0)
92 #define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9
93 #define EMERGENCY_PRINT_LOAD_GPR9 l.lwz r9,0x34(r0)
98 * TLB miss handlers temorary stores
100 #ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
101 #define EXCEPTION_STORE_GPR2 l.mtspr r0,r2,SPR_SHADOW_GPR(2)
102 #define EXCEPTION_LOAD_GPR2 l.mfspr r2,r0,SPR_SHADOW_GPR(2)
104 #define EXCEPTION_STORE_GPR3 l.mtspr r0,r3,SPR_SHADOW_GPR(3)
105 #define EXCEPTION_LOAD_GPR3 l.mfspr r3,r0,SPR_SHADOW_GPR(3)
107 #define EXCEPTION_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(4)
108 #define EXCEPTION_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(4)
110 #define EXCEPTION_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(5)
111 #define EXCEPTION_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(5)
113 #define EXCEPTION_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(6)
114 #define EXCEPTION_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(6)
116 #else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
117 #define EXCEPTION_STORE_GPR2 l.sw 0x64(r0),r2
118 #define EXCEPTION_LOAD_GPR2 l.lwz r2,0x64(r0)
120 #define EXCEPTION_STORE_GPR3 l.sw 0x68(r0),r3
121 #define EXCEPTION_LOAD_GPR3 l.lwz r3,0x68(r0)
123 #define EXCEPTION_STORE_GPR4 l.sw 0x6c(r0),r4
124 #define EXCEPTION_LOAD_GPR4 l.lwz r4,0x6c(r0)
126 #define EXCEPTION_STORE_GPR5 l.sw 0x70(r0),r5
127 #define EXCEPTION_LOAD_GPR5 l.lwz r5,0x70(r0)
129 #define EXCEPTION_STORE_GPR6 l.sw 0x74(r0),r6
130 #define EXCEPTION_LOAD_GPR6 l.lwz r6,0x74(r0)
135 * EXCEPTION_HANDLE temporary stores
138 #ifdef CONFIG_OPENRISC_HAVE_SHADOW_GPRS
139 #define EXCEPTION_T_STORE_GPR30 l.mtspr r0,r30,SPR_SHADOW_GPR(30)
140 #define EXCEPTION_T_LOAD_GPR30(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(30)
142 #define EXCEPTION_T_STORE_GPR10 l.mtspr r0,r10,SPR_SHADOW_GPR(10)
143 #define EXCEPTION_T_LOAD_GPR10(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(10)
145 #define EXCEPTION_T_STORE_SP l.mtspr r0,r1,SPR_SHADOW_GPR(1)
146 #define EXCEPTION_T_LOAD_SP(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(1)
148 #else /* !CONFIG_OPENRISC_HAVE_SHADOW_GPRS */
149 #define EXCEPTION_T_STORE_GPR30 l.sw 0x78(r0),r30
150 #define EXCEPTION_T_LOAD_GPR30(reg) l.lwz reg,0x78(r0)
152 #define EXCEPTION_T_STORE_GPR10 l.sw 0x7c(r0),r10
153 #define EXCEPTION_T_LOAD_GPR10(reg) l.lwz reg,0x7c(r0)
155 #define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1
156 #define EXCEPTION_T_LOAD_SP(reg) l.lwz reg,0x80(r0)
159 /* =========================================================[ macros ]=== */
162 #define GET_CURRENT_PGD(reg,t1) \
163 LOAD_SYMBOL_2_GPR(reg,current_pgd) ;\
164 l.mfspr t1,r0,SPR_COREID ;\
170 #define GET_CURRENT_PGD(reg,t1) \
171 LOAD_SYMBOL_2_GPR(reg,current_pgd) ;\
176 /* Load r10 from current_thread_info_set - clobbers r1 and r30 */
178 #define GET_CURRENT_THREAD_INFO \
179 LOAD_SYMBOL_2_GPR(r1,current_thread_info_set) ;\
181 l.mfspr r10,r0,SPR_COREID ;\
184 /* r10: current_thread_info */ ;\
187 #define GET_CURRENT_THREAD_INFO \
188 LOAD_SYMBOL_2_GPR(r1,current_thread_info_set) ;\
190 /* r10: current_thread_info */ ;\
195 * DSCR: this is a common hook for handling exceptions. it will save
196 * the needed registers, set up stack and pointer to current
197 * then jump to the handler while enabling MMU
199 * PRMS: handler - a function to jump to. it has to save the
200 * remaining registers to kernel stack, call
201 * appropriate arch-independant exception handler
202 * and finaly jump to ret_from_except
204 * PREQ: unchanged state from the time exception happened
206 * POST: SAVED the following registers original value
207 * to the new created exception frame pointed to by r1
209 * r1 - ksp pointing to the new (exception) frame
210 * r4 - EEAR exception EA
211 * r10 - current pointing to current_thread_info struct
212 * r12 - syscall 0, since we didn't come from syscall
213 * r30 - handler address of the handler we'll jump to
215 * handler has to save remaining registers to the exception
216 * ksp frame *before* tainting them!
218 * NOTE: this function is not reentrant per se. reentrancy is guaranteed
219 * by processor disabling all exceptions/interrupts when exception
222 * OPTM: no need to make it so wasteful to extract ksp when in user mode
225 #define EXCEPTION_HANDLE(handler) \
226 EXCEPTION_T_STORE_GPR30 ;\
227 l.mfspr r30,r0,SPR_ESR_BASE ;\
228 l.andi r30,r30,SPR_SR_SM ;\
230 EXCEPTION_T_STORE_GPR10 ;\
231 l.bnf 2f /* kernel_mode */ ;\
232 EXCEPTION_T_STORE_SP /* delay slot */ ;\
233 1: /* user_mode: */ ;\
234 GET_CURRENT_THREAD_INFO ;\
236 l.lwz r1,(TI_KSP)(r30) ;\
237 /* fall through */ ;\
238 2: /* kernel_mode: */ ;\
239 /* create new stack frame, save only needed gprs */ ;\
240 /* r1: KSP, r10: current, r4: EEAR, r31: __pa(KSP) */ ;\
241 /* r12: temp, syscall indicator */ ;\
242 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
243 /* r1 is KSP, r30 is __pa(KSP) */ ;\
245 l.sw PT_GPR12(r30),r12 ;\
246 /* r4 use for tmp before EA */ ;\
247 l.mfspr r12,r0,SPR_EPCR_BASE ;\
248 l.sw PT_PC(r30),r12 ;\
249 l.mfspr r12,r0,SPR_ESR_BASE ;\
250 l.sw PT_SR(r30),r12 ;\
252 EXCEPTION_T_LOAD_GPR30(r12) ;\
253 l.sw PT_GPR30(r30),r12 ;\
254 /* save r10 as was prior to exception */ ;\
255 EXCEPTION_T_LOAD_GPR10(r12) ;\
256 l.sw PT_GPR10(r30),r12 ;\
257 /* save PT_SP as was prior to exception */ ;\
258 EXCEPTION_T_LOAD_SP(r12) ;\
259 l.sw PT_SP(r30),r12 ;\
260 /* save exception r4, set r4 = EA */ ;\
261 l.sw PT_GPR4(r30),r4 ;\
262 l.mfspr r4,r0,SPR_EEAR_BASE ;\
263 /* r12 == 1 if we come from syscall */ ;\
265 /* ----- turn on MMU ----- */ ;\
266 /* Carry DSX into exception SR */ ;\
267 l.mfspr r30,r0,SPR_SR ;\
268 l.andi r30,r30,SPR_SR_DSX ;\
269 l.ori r30,r30,(EXCEPTION_SR) ;\
270 l.mtspr r0,r30,SPR_ESR_BASE ;\
271 /* r30: EA address of handler */ ;\
272 LOAD_SYMBOL_2_GPR(r30,handler) ;\
273 l.mtspr r0,r30,SPR_EPCR_BASE ;\
280 * #ifdef CONFIG_JUMP_UPON_UNHANDLED_EXCEPTION
281 * #define UNHANDLED_EXCEPTION(handler) \
283 * l.mtspr r0,r3,SPR_SR ;\
284 * l.movhi r3,hi(0xf0000100) ;\
285 * l.ori r3,r3,lo(0xf0000100) ;\
292 /* DSCR: this is the same as EXCEPTION_HANDLE(), we are just
293 * a bit more carefull (if we have a PT_SP or current pointer
294 * corruption) and set them up from 'current_set'
297 #define UNHANDLED_EXCEPTION(handler) \
298 EXCEPTION_T_STORE_GPR30 ;\
299 EXCEPTION_T_STORE_GPR10 ;\
300 EXCEPTION_T_STORE_SP ;\
301 /* temporary store r3, r9 into r1, r10 */ ;\
304 /* the string referenced by r3 must be low enough */ ;\
305 l.jal _emergency_print ;\
306 l.ori r3,r0,lo(_string_unhandled_exception) ;\
307 l.mfspr r3,r0,SPR_NPC ;\
308 l.jal _emergency_print_nr ;\
309 l.andi r3,r3,0x1f00 ;\
310 /* the string referenced by r3 must be low enough */ ;\
311 l.jal _emergency_print ;\
312 l.ori r3,r0,lo(_string_epc_prefix) ;\
313 l.jal _emergency_print_nr ;\
314 l.mfspr r3,r0,SPR_EPCR_BASE ;\
315 l.jal _emergency_print ;\
316 l.ori r3,r0,lo(_string_nl) ;\
317 /* end of printing */ ;\
320 /* extract current, ksp from current_set */ ;\
321 LOAD_SYMBOL_2_GPR(r1,_unhandled_stack_top) ;\
322 LOAD_SYMBOL_2_GPR(r10,init_thread_union) ;\
323 /* create new stack frame, save only needed gprs */ ;\
324 /* r1: KSP, r10: current, r31: __pa(KSP) */ ;\
325 /* r12: temp, syscall indicator, r13 temp */ ;\
326 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
327 /* r1 is KSP, r30 is __pa(KSP) */ ;\
329 l.sw PT_GPR12(r30),r12 ;\
330 l.mfspr r12,r0,SPR_EPCR_BASE ;\
331 l.sw PT_PC(r30),r12 ;\
332 l.mfspr r12,r0,SPR_ESR_BASE ;\
333 l.sw PT_SR(r30),r12 ;\
335 EXCEPTION_T_LOAD_GPR30(r12) ;\
336 l.sw PT_GPR30(r30),r12 ;\
337 /* save r10 as was prior to exception */ ;\
338 EXCEPTION_T_LOAD_GPR10(r12) ;\
339 l.sw PT_GPR10(r30),r12 ;\
340 /* save PT_SP as was prior to exception */ ;\
341 EXCEPTION_T_LOAD_SP(r12) ;\
342 l.sw PT_SP(r30),r12 ;\
343 l.sw PT_GPR13(r30),r13 ;\
345 /* save exception r4, set r4 = EA */ ;\
346 l.sw PT_GPR4(r30),r4 ;\
347 l.mfspr r4,r0,SPR_EEAR_BASE ;\
348 /* r12 == 1 if we come from syscall */ ;\
350 /* ----- play a MMU trick ----- */ ;\
351 l.ori r30,r0,(EXCEPTION_SR) ;\
352 l.mtspr r0,r30,SPR_ESR_BASE ;\
353 /* r31: EA address of handler */ ;\
354 LOAD_SYMBOL_2_GPR(r30,handler) ;\
355 l.mtspr r0,r30,SPR_EPCR_BASE ;\
358 /* =====================================================[ exceptions] === */
360 /* ---[ 0x100: RESET exception ]----------------------------------------- */
362 /* Jump to .init code at _start which lives in the .head section
363 * and will be discarded after boot.
365 LOAD_SYMBOL_2_GPR(r15, _start)
366 tophys (r13,r15) /* MMU disabled */
370 /* ---[ 0x200: BUS exception ]------------------------------------------- */
373 EXCEPTION_HANDLE(_bus_fault_handler)
375 /* ---[ 0x300: Data Page Fault exception ]------------------------------- */
377 _dispatch_do_dpage_fault:
378 // totaly disable timer interrupt
379 // l.mtspr r0,r0,SPR_TTMR
380 // DEBUG_TLB_PROBE(0x300)
381 // EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x300)
382 EXCEPTION_HANDLE(_data_page_fault_handler)
384 /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
386 _dispatch_do_ipage_fault:
387 // totaly disable timer interrupt
388 // l.mtspr r0,r0,SPR_TTMR
389 // DEBUG_TLB_PROBE(0x400)
390 // EXCEPTION_DEBUG_VALUE_ER_ENABLED(0x400)
391 EXCEPTION_HANDLE(_insn_page_fault_handler)
393 /* ---[ 0x500: Timer exception ]----------------------------------------- */
395 EXCEPTION_HANDLE(_timer_handler)
397 /* ---[ 0x600: Alignment exception ]-------------------------------------- */
399 EXCEPTION_HANDLE(_alignment_handler)
401 /* ---[ 0x700: Illegal insn exception ]---------------------------------- */
403 EXCEPTION_HANDLE(_illegal_instruction_handler)
405 /* ---[ 0x800: External interrupt exception ]---------------------------- */
407 EXCEPTION_HANDLE(_external_irq_handler)
409 /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
411 l.j boot_dtlb_miss_handler
414 /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
416 l.j boot_itlb_miss_handler
419 /* ---[ 0xb00: Range exception ]----------------------------------------- */
421 UNHANDLED_EXCEPTION(_vector_0xb00)
423 /* ---[ 0xc00: Syscall exception ]--------------------------------------- */
425 EXCEPTION_HANDLE(_sys_call_handler)
427 /* ---[ 0xd00: Trap exception ]------------------------------------------ */
429 UNHANDLED_EXCEPTION(_vector_0xd00)
431 /* ---[ 0xe00: Trap exception ]------------------------------------------ */
433 // UNHANDLED_EXCEPTION(_vector_0xe00)
434 EXCEPTION_HANDLE(_trap_handler)
436 /* ---[ 0xf00: Reserved exception ]-------------------------------------- */
438 UNHANDLED_EXCEPTION(_vector_0xf00)
440 /* ---[ 0x1000: Reserved exception ]------------------------------------- */
442 UNHANDLED_EXCEPTION(_vector_0x1000)
444 /* ---[ 0x1100: Reserved exception ]------------------------------------- */
446 UNHANDLED_EXCEPTION(_vector_0x1100)
448 /* ---[ 0x1200: Reserved exception ]------------------------------------- */
450 UNHANDLED_EXCEPTION(_vector_0x1200)
452 /* ---[ 0x1300: Reserved exception ]------------------------------------- */
454 UNHANDLED_EXCEPTION(_vector_0x1300)
456 /* ---[ 0x1400: Reserved exception ]------------------------------------- */
458 UNHANDLED_EXCEPTION(_vector_0x1400)
460 /* ---[ 0x1500: Reserved exception ]------------------------------------- */
462 UNHANDLED_EXCEPTION(_vector_0x1500)
464 /* ---[ 0x1600: Reserved exception ]------------------------------------- */
466 UNHANDLED_EXCEPTION(_vector_0x1600)
468 /* ---[ 0x1700: Reserved exception ]------------------------------------- */
470 UNHANDLED_EXCEPTION(_vector_0x1700)
472 /* ---[ 0x1800: Reserved exception ]------------------------------------- */
474 UNHANDLED_EXCEPTION(_vector_0x1800)
476 /* ---[ 0x1900: Reserved exception ]------------------------------------- */
478 UNHANDLED_EXCEPTION(_vector_0x1900)
480 /* ---[ 0x1a00: Reserved exception ]------------------------------------- */
482 UNHANDLED_EXCEPTION(_vector_0x1a00)
484 /* ---[ 0x1b00: Reserved exception ]------------------------------------- */
486 UNHANDLED_EXCEPTION(_vector_0x1b00)
488 /* ---[ 0x1c00: Reserved exception ]------------------------------------- */
490 UNHANDLED_EXCEPTION(_vector_0x1c00)
492 /* ---[ 0x1d00: Reserved exception ]------------------------------------- */
494 UNHANDLED_EXCEPTION(_vector_0x1d00)
496 /* ---[ 0x1e00: Reserved exception ]------------------------------------- */
498 UNHANDLED_EXCEPTION(_vector_0x1e00)
500 /* ---[ 0x1f00: Reserved exception ]------------------------------------- */
502 UNHANDLED_EXCEPTION(_vector_0x1f00)
505 /* ===================================================[ kernel start ]=== */
509 /* This early stuff belongs in HEAD, but some of the functions below definitely
515 /* Init r0 to zero as per spec */
518 /* save kernel parameters */
519 l.or r25,r0,r3 /* pointer to fdt */
522 * ensure a deterministic start
529 * Start the TTCR as early as possible, so that the RNG can make use of
530 * measurements of boot time from the earliest opportunity. Especially
531 * important is that the TTCR does not return zero by the time we reach
534 l.movhi r3,hi(SPR_TTMR_CR)
535 l.mtspr r0,r3,SPR_TTMR
569 l.mfspr r26,r0,SPR_COREID
575 * set up initial ksp and current
577 /* setup kernel stack */
578 LOAD_SYMBOL_2_GPR(r1,init_thread_union + THREAD_SIZE)
579 LOAD_SYMBOL_2_GPR(r10,init_thread_union) // setup current
587 * .data contains initialized data,
588 * .bss contains uninitialized data - clear it up
591 LOAD_SYMBOL_2_GPR(r24, __bss_start)
592 LOAD_SYMBOL_2_GPR(r26, _end)
615 /* The MMU needs to be enabled before or32_early_setup is called */
620 * SR[5] = 0, SR[6] = 0, 6th and 7th bit of SR set to 0
622 l.mfspr r30,r0,SPR_SR
623 l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME)
624 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
626 l.mtspr r0,r30,SPR_SR
644 // reset the simulation counters
647 /* check fdt header magic word */
648 l.lwz r3,0(r25) /* load magic from fdt into r3 */
649 l.movhi r4,hi(OF_DT_HEADER)
650 l.ori r4,r4,lo(OF_DT_HEADER)
654 /* magic number mismatch, set fdt pointer to null */
657 /* pass fdt pointer to or32_early_setup in r3 */
659 LOAD_SYMBOL_2_GPR(r24, or32_early_setup)
665 * clear all GPRS to increase determinism
699 * jump to kernel entry (start_kernel)
701 LOAD_SYMBOL_2_GPR(r30, start_kernel)
707 * I N V A L I D A T E T L B e n t r i e s
709 LOAD_SYMBOL_2_GPR(r5,SPR_DTLBMR_BASE(0))
710 LOAD_SYMBOL_2_GPR(r6,SPR_ITLBMR_BASE(0))
711 l.addi r7,r0,128 /* Maximum number of sets */
727 /* Doze the cpu until we are asked to run */
728 /* If we dont have power management skip doze */
729 l.mfspr r25,r0,SPR_UPR
730 l.andi r25,r25,SPR_UPR_PMP
732 l.bf secondary_check_release
735 /* Setup special secondary exception handler */
736 LOAD_SYMBOL_2_GPR(r3, _secondary_evbar)
738 l.mtspr r0,r25,SPR_EVBAR
740 /* Enable Interrupts */
741 l.mfspr r25,r0,SPR_SR
742 l.ori r25,r25,SPR_SR_IEE
743 l.mtspr r0,r25,SPR_SR
745 /* Unmask interrupts interrupts */
746 l.mfspr r25,r0,SPR_PICMR
748 l.mtspr r0,r25,SPR_PICMR
751 l.mfspr r25,r0,SPR_PMR
752 LOAD_SYMBOL_2_GPR(r3, SPR_PMR_DME)
754 l.mtspr r0,r25,SPR_PMR
756 /* Wakeup - Restore exception handler */
757 l.mtspr r0,r0,SPR_EVBAR
759 secondary_check_release:
761 * Check if we actually got the release signal, if not go-back to
764 l.mfspr r25,r0,SPR_COREID
765 LOAD_SYMBOL_2_GPR(r3, secondary_release)
771 /* fall through to secondary_init */
775 * set up initial ksp and current
777 LOAD_SYMBOL_2_GPR(r10, secondary_thread_info)
780 l.addi r1,r10,THREAD_SIZE
796 l.mfspr r30,r0,SPR_SR
797 l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME)
798 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
801 * This is a bit tricky, we need to switch over from physical addresses
802 * to virtual addresses on the fly.
803 * To do that, we first set up ESR with the IME and DME bits set.
804 * Then EPCR is set to secondary_start and then a l.rfe is issued to
807 l.mtspr r0,r30,SPR_ESR_BASE
808 LOAD_SYMBOL_2_GPR(r30, secondary_start)
809 l.mtspr r0,r30,SPR_EPCR_BASE
813 LOAD_SYMBOL_2_GPR(r30, secondary_start_kernel)
819 /* ========================================[ cache ]=== */
821 /* alignment here so we don't change memory offsets with
822 * memory controller defined
827 /* Check if IC present and skip enabling otherwise */
828 l.mfspr r24,r0,SPR_UPR
829 l.andi r26,r24,SPR_UPR_ICP
837 l.xori r5,r5,SPR_SR_ICE
841 /* Establish cache block size
844 r14 contain block size
846 l.mfspr r24,r0,SPR_ICCFGR
847 l.andi r26,r24,SPR_ICCFGR_CBS
852 /* Establish number of cache sets
853 r16 contains number of cache sets
854 r28 contains log(# of cache sets)
856 l.andi r26,r24,SPR_ICCFGR_NCS
866 // l.addi r5,r0,IC_SIZE
868 l.mtspr r0,r6,SPR_ICBIR
872 // l.addi r6,r6,IC_LINE
876 l.ori r6,r6,SPR_SR_ICE
893 /* Check if DC present and skip enabling otherwise */
894 l.mfspr r24,r0,SPR_UPR
895 l.andi r26,r24,SPR_UPR_DCP
903 l.xori r5,r5,SPR_SR_DCE
907 /* Establish cache block size
910 r14 contain block size
912 l.mfspr r24,r0,SPR_DCCFGR
913 l.andi r26,r24,SPR_DCCFGR_CBS
918 /* Establish number of cache sets
919 r16 contains number of cache sets
920 r28 contains log(# of cache sets)
922 l.andi r26,r24,SPR_DCCFGR_NCS
931 l.mtspr r0,r6,SPR_DCBIR
938 l.ori r6,r6,SPR_SR_DCE
944 /* ===============================================[ page table masks ]=== */
946 #define DTLB_UP_CONVERT_MASK 0x3fa
947 #define ITLB_UP_CONVERT_MASK 0x3a
949 /* for SMP we'd have (this is a bit subtle, CC must be always set
950 * for SMP, but since we have _PAGE_PRESENT bit always defined
951 * we can just modify the mask)
953 #define DTLB_SMP_CONVERT_MASK 0x3fb
954 #define ITLB_SMP_CONVERT_MASK 0x3b
956 /* ---[ boot dtlb miss handler ]----------------------------------------- */
958 boot_dtlb_miss_handler:
960 /* mask for DTLB_MR register: - (0) sets V (valid) bit,
961 * - (31-12) sets bits belonging to VPN (31-12)
963 #define DTLB_MR_MASK 0xfffff001
965 /* mask for DTLB_TR register: - (2) sets CI (cache inhibit) bit,
966 * - (4) sets A (access) bit,
967 * - (5) sets D (dirty) bit,
968 * - (8) sets SRE (superuser read) bit
969 * - (9) sets SWE (superuser write) bit
970 * - (31-12) sets bits belonging to VPN (31-12)
972 #define DTLB_TR_MASK 0xfffff332
974 /* These are for masking out the VPN/PPN value from the MR/TR registers...
975 * it's not the same as the PFN */
976 #define VPN_MASK 0xfffff000
977 #define PPN_MASK 0xfffff000
983 l.mfspr r6,r0,SPR_ESR_BASE //
984 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
985 l.sfeqi r6,0 // r6 == 0x1 --> SM
986 l.bf exit_with_no_dtranslation //
990 /* this could be optimized by moving storing of
991 * non r6 registers here, and jumping r6 restore
992 * if not in supervisor mode
1000 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
1002 immediate_translation:
1005 l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN size (4Kb)
1007 l.mfspr r6, r0, SPR_DMMUCFGR
1008 l.andi r6, r6, SPR_DMMUCFGR_NTS
1009 l.srli r6, r6, SPR_DMMUCFGR_NTS_OFF
1011 l.sll r5, r5, r6 // r5 = number DMMU sets
1012 l.addi r6, r5, -1 // r6 = nsets mask
1013 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
1015 l.or r6,r6,r4 // r6 <- r4
1016 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1017 l.movhi r5,hi(DTLB_MR_MASK) // r5 <- ffff:0000.x000
1018 l.ori r5,r5,lo(DTLB_MR_MASK) // r5 <- ffff:1111.x001 - apply DTLB_MR_MASK
1019 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have DTLBMR entry
1020 l.mtspr r2,r5,SPR_DTLBMR_BASE(0) // set DTLBMR
1022 /* set up DTLB with no translation for EA <= 0xbfffffff */
1023 LOAD_SYMBOL_2_GPR(r6,0xbfffffff)
1024 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xbfffffff >= EA)
1026 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
1028 tophys(r3,r4) // r3 <- PA
1030 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1031 l.movhi r5,hi(DTLB_TR_MASK) // r5 <- ffff:0000.x000
1032 l.ori r5,r5,lo(DTLB_TR_MASK) // r5 <- ffff:1111.x330 - apply DTLB_MR_MASK
1033 l.and r5,r5,r3 // r5 <- PPN :PPN .x330 - we have DTLBTR entry
1034 l.mtspr r2,r5,SPR_DTLBTR_BASE(0) // set DTLBTR
1042 l.rfe // SR <- ESR, PC <- EPC
1044 exit_with_no_dtranslation:
1045 /* EA out of memory or not in supervisor mode */
1048 l.j _dispatch_bus_fault
1050 /* ---[ boot itlb miss handler ]----------------------------------------- */
1052 boot_itlb_miss_handler:
1054 /* mask for ITLB_MR register: - sets V (valid) bit,
1055 * - sets bits belonging to VPN (15-12)
1057 #define ITLB_MR_MASK 0xfffff001
1059 /* mask for ITLB_TR register: - sets A (access) bit,
1060 * - sets SXE (superuser execute) bit
1061 * - sets bits belonging to VPN (15-12)
1063 #define ITLB_TR_MASK 0xfffff050
1066 #define VPN_MASK 0xffffe000
1067 #define PPN_MASK 0xffffe000
1072 EXCEPTION_STORE_GPR2
1073 EXCEPTION_STORE_GPR3
1074 EXCEPTION_STORE_GPR4
1075 EXCEPTION_STORE_GPR5
1076 EXCEPTION_STORE_GPR6
1079 l.mfspr r6,r0,SPR_ESR_BASE //
1080 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
1081 l.sfeqi r6,0 // r6 == 0x1 --> SM
1082 l.bf exit_with_no_itranslation
1087 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
1092 l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN size (4Kb)
1094 l.mfspr r6, r0, SPR_IMMUCFGR
1095 l.andi r6, r6, SPR_IMMUCFGR_NTS
1096 l.srli r6, r6, SPR_IMMUCFGR_NTS_OFF
1098 l.sll r5, r5, r6 // r5 = number IMMU sets from IMMUCFGR
1099 l.addi r6, r5, -1 // r6 = nsets mask
1100 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
1102 l.or r6,r6,r4 // r6 <- r4
1103 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1104 l.movhi r5,hi(ITLB_MR_MASK) // r5 <- ffff:0000.x000
1105 l.ori r5,r5,lo(ITLB_MR_MASK) // r5 <- ffff:1111.x001 - apply ITLB_MR_MASK
1106 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have ITLBMR entry
1107 l.mtspr r2,r5,SPR_ITLBMR_BASE(0) // set ITLBMR
1110 * set up ITLB with no translation for EA <= 0x0fffffff
1112 * we need this for head.S mapping (EA = PA). if we move all functions
1113 * which run with mmu enabled into entry.S, we might be able to eliminate this.
1116 LOAD_SYMBOL_2_GPR(r6,0x0fffffff)
1117 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xb0ffffff >= EA)
1119 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
1121 tophys(r3,r4) // r3 <- PA
1123 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1124 l.movhi r5,hi(ITLB_TR_MASK) // r5 <- ffff:0000.x000
1125 l.ori r5,r5,lo(ITLB_TR_MASK) // r5 <- ffff:1111.x050 - apply ITLB_MR_MASK
1126 l.and r5,r5,r3 // r5 <- PPN :PPN .x050 - we have ITLBTR entry
1127 l.mtspr r2,r5,SPR_ITLBTR_BASE(0) // set ITLBTR
1135 l.rfe // SR <- ESR, PC <- EPC
1137 exit_with_no_itranslation:
1140 l.j _dispatch_bus_fault
1143 /* ====================================================================== */
1145 * Stuff below here shouldn't go into .head section... maybe this stuff
1146 * can be moved to entry.S ???
1149 /* ==============================================[ DTLB miss handler ]=== */
1153 * Exception handlers are entered with MMU off so the following handler
1154 * needs to use physical addressing
1159 ENTRY(dtlb_miss_handler)
1160 EXCEPTION_STORE_GPR2
1161 EXCEPTION_STORE_GPR3
1162 EXCEPTION_STORE_GPR4
1164 * get EA of the miss
1166 l.mfspr r2,r0,SPR_EEAR_BASE
1168 * pmd = (pmd_t *)(current_pgd + pgd_index(daddr));
1170 GET_CURRENT_PGD(r3,r4) // r3 is current_pgd, r4 is temp
1171 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1172 l.slli r4,r4,0x2 // to get address << 2
1173 l.add r3,r4,r3 // r4 is pgd_index(daddr)
1175 * if (pmd_none(*pmd))
1179 l.lwz r3,0x0(r4) // get *pmd value
1182 l.addi r3,r0,0xffffe000 // PAGE_MASK
1186 * pte = *pte_offset(pmd, daddr);
1188 l.lwz r4,0x0(r4) // get **pmd value
1189 l.and r4,r4,r3 // & PAGE_MASK
1190 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1191 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1192 l.slli r3,r3,0x2 // to get address << 2
1194 l.lwz r3,0x0(r3) // this is pte at last
1196 * if (!pte_present(pte))
1199 l.sfne r4,r0 // is pte present
1200 l.bnf d_pte_not_present
1201 l.addi r4,r0,0xffffe3fa // PAGE_MASK | DTLB_UP_CONVERT_MASK
1203 * fill DTLB TR register
1205 l.and r4,r3,r4 // apply the mask
1206 // Determine number of DMMU sets
1207 l.mfspr r2, r0, SPR_DMMUCFGR
1208 l.andi r2, r2, SPR_DMMUCFGR_NTS
1209 l.srli r2, r2, SPR_DMMUCFGR_NTS_OFF
1211 l.sll r3, r3, r2 // r3 = number DMMU sets DMMUCFGR
1212 l.addi r2, r3, -1 // r2 = nsets mask
1213 l.mfspr r3, r0, SPR_EEAR_BASE
1214 l.srli r3, r3, 0xd // >> PAGE_SHIFT
1215 l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1)
1217 l.mtspr r2,r4,SPR_DTLBTR_BASE(0)
1219 * fill DTLB MR register
1221 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
1222 l.ori r4,r3,0x1 // set hardware valid bit: DTBL_MR entry
1223 l.mtspr r2,r4,SPR_DTLBMR_BASE(0)
1234 EXCEPTION_HANDLE(_dtlb_miss_page_fault_handler)
1236 /* ==============================================[ ITLB miss handler ]=== */
1237 ENTRY(itlb_miss_handler)
1238 EXCEPTION_STORE_GPR2
1239 EXCEPTION_STORE_GPR3
1240 EXCEPTION_STORE_GPR4
1242 * get EA of the miss
1244 l.mfspr r2,r0,SPR_EEAR_BASE
1247 * pmd = (pmd_t *)(current_pgd + pgd_index(daddr));
1250 GET_CURRENT_PGD(r3,r4) // r3 is current_pgd, r5 is temp
1251 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1252 l.slli r4,r4,0x2 // to get address << 2
1253 l.add r3,r4,r3 // r4 is pgd_index(daddr)
1255 * if (pmd_none(*pmd))
1259 l.lwz r3,0x0(r4) // get *pmd value
1262 l.addi r3,r0,0xffffe000 // PAGE_MASK
1266 * pte = *pte_offset(pmd, iaddr);
1269 l.lwz r4,0x0(r4) // get **pmd value
1270 l.and r4,r4,r3 // & PAGE_MASK
1271 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1272 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1273 l.slli r3,r3,0x2 // to get address << 2
1275 l.lwz r3,0x0(r3) // this is pte at last
1277 * if (!pte_present(pte))
1281 l.sfne r4,r0 // is pte present
1282 l.bnf i_pte_not_present
1283 l.addi r4,r0,0xffffe03a // PAGE_MASK | ITLB_UP_CONVERT_MASK
1285 * fill ITLB TR register
1287 l.and r4,r3,r4 // apply the mask
1288 l.andi r3,r3,0x7c0 // _PAGE_EXEC | _PAGE_SRE | _PAGE_SWE | _PAGE_URE | _PAGE_UWE
1290 l.bf itlb_tr_fill //_workaround
1291 // Determine number of IMMU sets
1292 l.mfspr r2, r0, SPR_IMMUCFGR
1293 l.andi r2, r2, SPR_IMMUCFGR_NTS
1294 l.srli r2, r2, SPR_IMMUCFGR_NTS_OFF
1296 l.sll r3, r3, r2 // r3 = number IMMU sets IMMUCFGR
1297 l.addi r2, r3, -1 // r2 = nsets mask
1298 l.mfspr r3, r0, SPR_EEAR_BASE
1299 l.srli r3, r3, 0xd // >> PAGE_SHIFT
1300 l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1)
1304 * we should not just blindly set executable flags,
1305 * but it does help with ping. the clean way would be to find out
1306 * (and fix it) why stack doesn't have execution permissions
1309 itlb_tr_fill_workaround:
1310 l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE)
1312 l.mtspr r2,r4,SPR_ITLBTR_BASE(0)
1314 * fill DTLB MR register
1316 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
1317 l.ori r4,r3,0x1 // set hardware valid bit: ITBL_MR entry
1318 l.mtspr r2,r4,SPR_ITLBMR_BASE(0)
1330 EXCEPTION_HANDLE(_itlb_miss_page_fault_handler)
1332 /* ==============================================[ boot tlb handlers ]=== */
1335 /* =================================================[ debugging aids ]=== */
1340 _immu_trampoline_top:
1342 #define TRAMP_SLOT_0 (0x0)
1343 #define TRAMP_SLOT_1 (0x4)
1344 #define TRAMP_SLOT_2 (0x8)
1345 #define TRAMP_SLOT_3 (0xc)
1346 #define TRAMP_SLOT_4 (0x10)
1347 #define TRAMP_SLOT_5 (0x14)
1348 #define TRAMP_FRAME_SIZE (0x18)
1350 ENTRY(_immu_trampoline_workaround)
1352 // r6 is physical EEA
1355 LOAD_SYMBOL_2_GPR(r5,_immu_trampoline)
1356 tophys (r3,r5) // r3 is trampoline (physical)
1358 LOAD_SYMBOL_2_GPR(r4,0x15000000)
1359 l.sw TRAMP_SLOT_0(r3),r4
1360 l.sw TRAMP_SLOT_1(r3),r4
1361 l.sw TRAMP_SLOT_4(r3),r4
1362 l.sw TRAMP_SLOT_5(r3),r4
1365 l.lwz r4,0x0(r6) // load op @ EEA + 0x0 (fc address)
1366 l.sw TRAMP_SLOT_3(r3),r4 // store it to _immu_trampoline_data
1367 l.lwz r4,-0x4(r6) // load op @ EEA - 0x4 (f8 address)
1368 l.sw TRAMP_SLOT_2(r3),r4 // store it to _immu_trampoline_data
1370 l.srli r5,r4,26 // check opcode for write access
1373 l.sfeqi r5,0x11 // l.jr
1375 l.sfeqi r5,1 // l.jal
1377 l.sfeqi r5,0x12 // l.jalr
1379 l.sfeqi r5,3 // l.bnf
1381 l.sfeqi r5,4 // l.bf
1385 l.j 99b // should never happen
1389 // r3 is trampoline address (physical)
1390 // r4 is instruction
1391 // r6 is physical(EEA)
1397 /* 19 20 aa aa l.movhi r9,0xaaaa
1398 * a9 29 bb bb l.ori r9,0xbbbb
1400 * where 0xaaaabbbb is EEA + 0x4 shifted right 2
1403 l.addi r6,r2,0x4 // this is 0xaaaabbbb
1405 // l.movhi r9,0xaaaa
1406 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1407 l.sh (TRAMP_SLOT_0+0x0)(r3),r5
1409 l.sh (TRAMP_SLOT_0+0x2)(r3),r5
1412 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1413 l.sh (TRAMP_SLOT_1+0x0)(r3),r5
1415 l.sh (TRAMP_SLOT_1+0x2)(r3),r5
1417 /* falthrough, need to set up new jump offset */
1421 l.slli r6,r4,6 // original offset shifted left 6 - 2
1422 // l.srli r6,r6,6 // original offset shifted right 2
1424 l.slli r4,r2,4 // old jump position: EEA shifted left 4
1425 // l.srli r4,r4,6 // old jump position: shifted right 2
1427 l.addi r5,r3,0xc // new jump position (physical)
1428 l.slli r5,r5,4 // new jump position: shifted left 4
1430 // calculate new jump offset
1431 // new_off = old_off + (old_jump - new_jump)
1433 l.sub r5,r4,r5 // old_jump - new_jump
1434 l.add r5,r6,r5 // orig_off + (old_jump - new_jump)
1435 l.srli r5,r5,6 // new offset shifted right 2
1437 // r5 is new jump offset
1438 // l.j has opcode 0x0...
1439 l.sw TRAMP_SLOT_2(r3),r5 // write it back
1444 /* ----------------------------- */
1448 /* 19 20 aa aa l.movhi r9,0xaaaa
1449 * a9 29 bb bb l.ori r9,0xbbbb
1451 * where 0xaaaabbbb is EEA + 0x4 shifted right 2
1454 l.addi r6,r2,0x4 // this is 0xaaaabbbb
1456 // l.movhi r9,0xaaaa
1457 l.ori r5,r0,0x1920 // 0x1920 == l.movhi r9
1458 l.sh (TRAMP_SLOT_0+0x0)(r3),r5
1460 l.sh (TRAMP_SLOT_0+0x2)(r3),r5
1463 l.ori r5,r0,0xa929 // 0xa929 == l.ori r9
1464 l.sh (TRAMP_SLOT_1+0x0)(r3),r5
1466 l.sh (TRAMP_SLOT_1+0x2)(r3),r5
1468 l.lhz r5,(TRAMP_SLOT_2+0x0)(r3) // load hi part of jump instruction
1469 l.andi r5,r5,0x3ff // clear out opcode part
1470 l.ori r5,r5,0x4400 // opcode changed from l.jalr -> l.jr
1471 l.sh (TRAMP_SLOT_2+0x0)(r3),r5 // write it back
1479 /* ----------------------------- */
1483 l.slli r6,r4,6 // original offset shifted left 6 - 2
1484 // l.srli r6,r6,6 // original offset shifted right 2
1486 l.slli r4,r2,4 // old jump position: EEA shifted left 4
1487 // l.srli r4,r4,6 // old jump position: shifted right 2
1489 l.addi r5,r3,0xc // new jump position (physical)
1490 l.slli r5,r5,4 // new jump position: shifted left 4
1492 // calculate new jump offset
1493 // new_off = old_off + (old_jump - new_jump)
1495 l.add r6,r6,r4 // (orig_off + old_jump)
1496 l.sub r6,r6,r5 // (orig_off + old_jump) - new_jump
1497 l.srli r6,r6,6 // new offset shifted right 2
1499 // r6 is new jump offset
1500 l.lwz r4,(TRAMP_SLOT_2+0x0)(r3) // load jump instruction
1502 l.andi r4,r4,0xfc00 // get opcode part
1504 l.or r6,r4,r6 // l.b(n)f new offset
1505 l.sw TRAMP_SLOT_2(r3),r6 // write it back
1507 /* we need to add l.j to EEA + 0x8 */
1508 tophys (r4,r2) // may not be needed (due to shifts down_
1509 l.addi r4,r4,(0x8 - 0x8) // jump target = r2 + 0x8 (compensate for 0x8)
1510 // jump position = r5 + 0x8 (0x8 compensated)
1511 l.sub r4,r4,r5 // jump offset = target - new_position + 0x8
1513 l.slli r4,r4,4 // the amount of info in imediate of jump
1514 l.srli r4,r4,6 // jump instruction with offset
1515 l.sw TRAMP_SLOT_4(r3),r4 // write it to 4th slot
1520 // set up new EPC to point to our trampoline code
1521 LOAD_SYMBOL_2_GPR(r5,_immu_trampoline)
1522 l.mtspr r0,r5,SPR_EPCR_BASE
1524 // immu_trampoline is (4x) CACHE_LINE aligned
1525 // and only 6 instructions long,
1526 // so we need to invalidate only 2 lines
1528 /* Establish cache block size
1531 r14 contain block size
1533 l.mfspr r21,r0,SPR_ICCFGR
1534 l.andi r21,r21,SPR_ICCFGR_CBS
1539 l.mtspr r0,r5,SPR_ICBIR
1541 l.mtspr r0,r5,SPR_ICBIR
1548 * DSCR: prints a string referenced by r3.
1550 * PRMS: r3 - address of the first character of null
1551 * terminated string to be printed
1553 * PREQ: UART at UART_BASE_ADD has to be initialized
1555 * POST: caller should be aware that r3, r9 are changed
1557 ENTRY(_emergency_print)
1558 EMERGENCY_PRINT_STORE_GPR4
1559 EMERGENCY_PRINT_STORE_GPR5
1560 EMERGENCY_PRINT_STORE_GPR6
1561 EMERGENCY_PRINT_STORE_GPR7
1569 l.movhi r4,hi(UART_BASE_ADD)
1587 /* next character */
1592 EMERGENCY_PRINT_LOAD_GPR7
1593 EMERGENCY_PRINT_LOAD_GPR6
1594 EMERGENCY_PRINT_LOAD_GPR5
1595 EMERGENCY_PRINT_LOAD_GPR4
1599 ENTRY(_emergency_print_nr)
1600 EMERGENCY_PRINT_STORE_GPR4
1601 EMERGENCY_PRINT_STORE_GPR5
1602 EMERGENCY_PRINT_STORE_GPR6
1603 EMERGENCY_PRINT_STORE_GPR7
1604 EMERGENCY_PRINT_STORE_GPR8
1606 l.addi r8,r0,32 // shift register
1608 1: /* remove leading zeros */
1613 /* don't skip the last zero if number == 0x0 */
1637 l.movhi r4,hi(UART_BASE_ADD)
1655 /* next character */
1660 EMERGENCY_PRINT_LOAD_GPR8
1661 EMERGENCY_PRINT_LOAD_GPR7
1662 EMERGENCY_PRINT_LOAD_GPR6
1663 EMERGENCY_PRINT_LOAD_GPR5
1664 EMERGENCY_PRINT_LOAD_GPR4
1670 * This should be used for debugging only.
1671 * It messes up the Linux early serial output
1672 * somehow, so use it sparingly and essentially
1673 * only if you need to debug something that goes wrong
1674 * before Linux gets the early serial going.
1676 * Furthermore, you'll have to make sure you set the
1677 * UART_DEVISOR correctly according to the system
1685 #define SYS_CLK 20000000
1686 //#define SYS_CLK 1843200
1687 #define OR32_CONSOLE_BAUD 115200
1688 #define UART_DIVISOR SYS_CLK/(16*OR32_CONSOLE_BAUD)
1690 ENTRY(_early_uart_init)
1691 l.movhi r3,hi(UART_BASE_ADD)
1705 l.addi r4,r0,((UART_DIVISOR>>8) & 0x000000ff)
1706 l.sb UART_DLM(r3),r4
1707 l.addi r4,r0,((UART_DIVISOR) & 0x000000ff)
1708 l.sb UART_DLL(r3),r4
1715 .global _secondary_evbar
1719 /* Just disable interrupts and Return */
1720 l.ori r3,r0,SPR_SR_SM
1721 l.mtspr r0,r3,SPR_ESR_BASE
1726 _string_unhandled_exception:
1727 .string "\n\rRunarunaround: Unhandled exception 0x\0"
1730 .string ": EPC=0x\0"
1736 /* ========================================[ page aligned structures ]=== */
1739 * .data section should be page aligned
1740 * (look into arch/openrisc/kernel/vmlinux.lds.S)
1744 .global empty_zero_page
1748 .global swapper_pg_dir
1752 .global _unhandled_stack
1755 _unhandled_stack_top:
1757 /* ============================================================[ EOF ]=== */