hda/patch_ca0132.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * HD audio interface patch for Creative CA0132 chip
   4  *
   5  * Copyright (c) 2011, Creative Technology Ltd.
   6  *
   7  * Based on patch_ca0110.c
   8  * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/delay.h>
  13 #include <linux/slab.h>
  14 #include <linux/mutex.h>
  15 #include <linux/module.h>
  16 #include <linux/firmware.h>
  17 #include <linux/kernel.h>
  18 #include <linux/types.h>
  19 #include <linux/io.h>
  20 #include <linux/pci.h>
  21 #include <asm/io.h>
  22 #include <sound/core.h>
  23 #include <sound/hda_codec.h>
  24 #include "hda_local.h"
  25 #include "hda_auto_parser.h"
  26 #include "hda_jack.h"
  27
  28 #include "ca0132_regs.h"
  29
  30 /* Enable this to see controls for tuning purpose. */
  31 /*#define ENABLE_TUNING_CONTROLS*/
  32
  33 #ifdef ENABLE_TUNING_CONTROLS
  34 #include <sound/tlv.h>
  35 #endif
  36
  37 #define FLOAT_ZERO      0x00000000
  38 #define FLOAT_ONE       0x3f800000
  39 #define FLOAT_TWO       0x40000000
  40 #define FLOAT_THREE     0x40400000
  41 #define FLOAT_FIVE      0x40a00000
  42 #define FLOAT_SIX       0x40c00000
  43 #define FLOAT_EIGHT     0x41000000
  44 #define FLOAT_MINUS_5   0xc0a00000
  45
  46 #define UNSOL_TAG_DSP   0x16
  47
  48 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
  49 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
  50
  51 #define DMA_TRANSFER_FRAME_SIZE_NWORDS          8
  52 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS      32
  53 #define DMA_OVERLAY_FRAME_SIZE_NWORDS           2
  54
  55 #define MASTERCONTROL                           0x80
  56 #define MASTERCONTROL_ALLOC_DMA_CHAN            10
  57 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS  60
  58
  59 #define WIDGET_CHIP_CTRL      0x15
  60 #define WIDGET_DSP_CTRL       0x16
  61
  62 #define MEM_CONNID_MICIN1     3
  63 #define MEM_CONNID_MICIN2     5
  64 #define MEM_CONNID_MICOUT1    12
  65 #define MEM_CONNID_MICOUT2    14
  66 #define MEM_CONNID_WUH        10
  67 #define MEM_CONNID_DSP        16
  68 #define MEM_CONNID_DMIC       100
  69
  70 #define SCP_SET    0
  71 #define SCP_GET    1
  72
  73 #define EFX_FILE   "/*(DEBLOBBED)*/"
  74 #define DESKTOP_EFX_FILE   "/*(DEBLOBBED)*/"
  75 #define R3DI_EFX_FILE  "/*(DEBLOBBED)*/"
  76
  77 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
  78 /*(DEBLOBBED)*/
  79 #endif
  80
  81 static const char *const dirstr[2] = { "Playback", "Capture" };
  82
  83 #define NUM_OF_OUTPUTS 2
  84 static const char *const out_type_str[2] = { "Speakers", "Headphone" };
  85 enum {
  86         SPEAKER_OUT,
  87         HEADPHONE_OUT,
  88 };
  89
  90 enum {
  91         DIGITAL_MIC,
  92         LINE_MIC_IN
  93 };
  94
  95 /* Strings for Input Source Enum Control */
  96 static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" };
  97 #define IN_SRC_NUM_OF_INPUTS 3
  98 enum {
  99         REAR_MIC,
 100         REAR_LINE_IN,
 101         FRONT_MIC,
 102 };
 103
 104 enum {
 105 #define VNODE_START_NID    0x80
 106         VNID_SPK = VNODE_START_NID,                     /* Speaker vnid */
 107         VNID_MIC,
 108         VNID_HP_SEL,
 109         VNID_AMIC1_SEL,
 110         VNID_HP_ASEL,
 111         VNID_AMIC1_ASEL,
 112         VNODE_END_NID,
 113 #define VNODES_COUNT  (VNODE_END_NID - VNODE_START_NID)
 114
 115 #define EFFECT_START_NID    0x90
 116 #define OUT_EFFECT_START_NID    EFFECT_START_NID
 117         SURROUND = OUT_EFFECT_START_NID,
 118         CRYSTALIZER,
 119         DIALOG_PLUS,
 120         SMART_VOLUME,
 121         X_BASS,
 122         EQUALIZER,
 123         OUT_EFFECT_END_NID,
 124 #define OUT_EFFECTS_COUNT  (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
 125
 126 #define IN_EFFECT_START_NID  OUT_EFFECT_END_NID
 127         ECHO_CANCELLATION = IN_EFFECT_START_NID,
 128         VOICE_FOCUS,
 129         MIC_SVM,
 130         NOISE_REDUCTION,
 131         IN_EFFECT_END_NID,
 132 #define IN_EFFECTS_COUNT  (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
 133
 134         VOICEFX = IN_EFFECT_END_NID,
 135         PLAY_ENHANCEMENT,
 136         CRYSTAL_VOICE,
 137         EFFECT_END_NID,
 138         OUTPUT_SOURCE_ENUM,
 139         INPUT_SOURCE_ENUM,
 140         XBASS_XOVER,
 141         EQ_PRESET_ENUM,
 142         SMART_VOLUME_ENUM,
 143         MIC_BOOST_ENUM,
 144         AE5_HEADPHONE_GAIN_ENUM,
 145         AE5_SOUND_FILTER_ENUM,
 146         ZXR_HEADPHONE_GAIN,
 147         SPEAKER_CHANNEL_CFG_ENUM,
 148         SPEAKER_FULL_RANGE_FRONT,
 149         SPEAKER_FULL_RANGE_REAR,
 150         BASS_REDIRECTION,
 151         BASS_REDIRECTION_XOVER,
 152 #define EFFECTS_COUNT  (EFFECT_END_NID - EFFECT_START_NID)
 153 };
 154
 155 /* Effects values size*/
 156 #define EFFECT_VALS_MAX_COUNT 12
 157
 158 /*
 159  * Default values for the effect slider controls, they are in order of their
 160  * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
 161  * X-bass.
 162  */
 163 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
 164 /* Amount of effect level sliders for ca0132_alt controls. */
 165 #define EFFECT_LEVEL_SLIDERS 5
 166
 167 /* Latency introduced by DSP blocks in milliseconds. */
 168 #define DSP_CAPTURE_INIT_LATENCY        0
 169 #define DSP_CRYSTAL_VOICE_LATENCY       124
 170 #define DSP_PLAYBACK_INIT_LATENCY       13
 171 #define DSP_PLAY_ENHANCEMENT_LATENCY    30
 172 #define DSP_SPEAKER_OUT_LATENCY         7
 173
 174 struct ct_effect {
 175         char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
 176         hda_nid_t nid;
 177         int mid; /*effect module ID*/
 178         int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
 179         int direct; /* 0:output; 1:input*/
 180         int params; /* number of default non-on/off params */
 181         /*effect default values, 1st is on/off. */
 182         unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
 183 };
 184
 185 #define EFX_DIR_OUT 0
 186 #define EFX_DIR_IN  1
 187
 188 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
 189         { .name = "Surround",
 190           .nid = SURROUND,
 191           .mid = 0x96,
 192           .reqs = {0, 1},
 193           .direct = EFX_DIR_OUT,
 194           .params = 1,
 195           .def_vals = {0x3F800000, 0x3F2B851F}
 196         },
 197         { .name = "Crystalizer",
 198           .nid = CRYSTALIZER,
 199           .mid = 0x96,
 200           .reqs = {7, 8},
 201           .direct = EFX_DIR_OUT,
 202           .params = 1,
 203           .def_vals = {0x3F800000, 0x3F266666}
 204         },
 205         { .name = "Dialog Plus",
 206           .nid = DIALOG_PLUS,
 207           .mid = 0x96,
 208           .reqs = {2, 3},
 209           .direct = EFX_DIR_OUT,
 210           .params = 1,
 211           .def_vals = {0x00000000, 0x3F000000}
 212         },
 213         { .name = "Smart Volume",
 214           .nid = SMART_VOLUME,
 215           .mid = 0x96,
 216           .reqs = {4, 5, 6},
 217           .direct = EFX_DIR_OUT,
 218           .params = 2,
 219           .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
 220         },
 221         { .name = "X-Bass",
 222           .nid = X_BASS,
 223           .mid = 0x96,
 224           .reqs = {24, 23, 25},
 225           .direct = EFX_DIR_OUT,
 226           .params = 2,
 227           .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
 228         },
 229         { .name = "Equalizer",
 230           .nid = EQUALIZER,
 231           .mid = 0x96,
 232           .reqs = {9, 10, 11, 12, 13, 14,
 233                         15, 16, 17, 18, 19, 20},
 234           .direct = EFX_DIR_OUT,
 235           .params = 11,
 236           .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
 237                        0x00000000, 0x00000000, 0x00000000, 0x00000000,
 238                        0x00000000, 0x00000000, 0x00000000, 0x00000000}
 239         },
 240         { .name = "Echo Cancellation",
 241           .nid = ECHO_CANCELLATION,
 242           .mid = 0x95,
 243           .reqs = {0, 1, 2, 3},
 244           .direct = EFX_DIR_IN,
 245           .params = 3,
 246           .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
 247         },
 248         { .name = "Voice Focus",
 249           .nid = VOICE_FOCUS,
 250           .mid = 0x95,
 251           .reqs = {6, 7, 8, 9},
 252           .direct = EFX_DIR_IN,
 253           .params = 3,
 254           .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
 255         },
 256         { .name = "Mic SVM",
 257           .nid = MIC_SVM,
 258           .mid = 0x95,
 259           .reqs = {44, 45},
 260           .direct = EFX_DIR_IN,
 261           .params = 1,
 262           .def_vals = {0x00000000, 0x3F3D70A4}
 263         },
 264         { .name = "Noise Reduction",
 265           .nid = NOISE_REDUCTION,
 266           .mid = 0x95,
 267           .reqs = {4, 5},
 268           .direct = EFX_DIR_IN,
 269           .params = 1,
 270           .def_vals = {0x3F800000, 0x3F000000}
 271         },
 272         { .name = "VoiceFX",
 273           .nid = VOICEFX,
 274           .mid = 0x95,
 275           .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
 276           .direct = EFX_DIR_IN,
 277           .params = 8,
 278           .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
 279                        0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
 280                        0x00000000}
 281         }
 282 };
 283
 284 /* Tuning controls */
 285 #ifdef ENABLE_TUNING_CONTROLS
 286
 287 enum {
 288 #define TUNING_CTL_START_NID  0xC0
 289         WEDGE_ANGLE = TUNING_CTL_START_NID,
 290         SVM_LEVEL,
 291         EQUALIZER_BAND_0,
 292         EQUALIZER_BAND_1,
 293         EQUALIZER_BAND_2,
 294         EQUALIZER_BAND_3,
 295         EQUALIZER_BAND_4,
 296         EQUALIZER_BAND_5,
 297         EQUALIZER_BAND_6,
 298         EQUALIZER_BAND_7,
 299         EQUALIZER_BAND_8,
 300         EQUALIZER_BAND_9,
 301         TUNING_CTL_END_NID
 302 #define TUNING_CTLS_COUNT  (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
 303 };
 304
 305 struct ct_tuning_ctl {
 306         char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
 307         hda_nid_t parent_nid;
 308         hda_nid_t nid;
 309         int mid; /*effect module ID*/
 310         int req; /*effect module request*/
 311         int direct; /* 0:output; 1:input*/
 312         unsigned int def_val;/*effect default values*/
 313 };
 314
 315 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
 316         { .name = "Wedge Angle",
 317           .parent_nid = VOICE_FOCUS,
 318           .nid = WEDGE_ANGLE,
 319           .mid = 0x95,
 320           .req = 8,
 321           .direct = EFX_DIR_IN,
 322           .def_val = 0x41F00000
 323         },
 324         { .name = "SVM Level",
 325           .parent_nid = MIC_SVM,
 326           .nid = SVM_LEVEL,
 327           .mid = 0x95,
 328           .req = 45,
 329           .direct = EFX_DIR_IN,
 330           .def_val = 0x3F3D70A4
 331         },
 332         { .name = "EQ Band0",
 333           .parent_nid = EQUALIZER,
 334           .nid = EQUALIZER_BAND_0,
 335           .mid = 0x96,
 336           .req = 11,
 337           .direct = EFX_DIR_OUT,
 338           .def_val = 0x00000000
 339         },
 340         { .name = "EQ Band1",
 341           .parent_nid = EQUALIZER,
 342           .nid = EQUALIZER_BAND_1,
 343           .mid = 0x96,
 344           .req = 12,
 345           .direct = EFX_DIR_OUT,
 346           .def_val = 0x00000000
 347         },
 348         { .name = "EQ Band2",
 349           .parent_nid = EQUALIZER,
 350           .nid = EQUALIZER_BAND_2,
 351           .mid = 0x96,
 352           .req = 13,
 353           .direct = EFX_DIR_OUT,
 354           .def_val = 0x00000000
 355         },
 356         { .name = "EQ Band3",
 357           .parent_nid = EQUALIZER,
 358           .nid = EQUALIZER_BAND_3,
 359           .mid = 0x96,
 360           .req = 14,
 361           .direct = EFX_DIR_OUT,
 362           .def_val = 0x00000000
 363         },
 364         { .name = "EQ Band4",
 365           .parent_nid = EQUALIZER,
 366           .nid = EQUALIZER_BAND_4,
 367           .mid = 0x96,
 368           .req = 15,
 369           .direct = EFX_DIR_OUT,
 370           .def_val = 0x00000000
 371         },
 372         { .name = "EQ Band5",
 373           .parent_nid = EQUALIZER,
 374           .nid = EQUALIZER_BAND_5,
 375           .mid = 0x96,
 376           .req = 16,
 377           .direct = EFX_DIR_OUT,
 378           .def_val = 0x00000000
 379         },
 380         { .name = "EQ Band6",
 381           .parent_nid = EQUALIZER,
 382           .nid = EQUALIZER_BAND_6,
 383           .mid = 0x96,
 384           .req = 17,
 385           .direct = EFX_DIR_OUT,
 386           .def_val = 0x00000000
 387         },
 388         { .name = "EQ Band7",
 389           .parent_nid = EQUALIZER,
 390           .nid = EQUALIZER_BAND_7,
 391           .mid = 0x96,
 392           .req = 18,
 393           .direct = EFX_DIR_OUT,
 394           .def_val = 0x00000000
 395         },
 396         { .name = "EQ Band8",
 397           .parent_nid = EQUALIZER,
 398           .nid = EQUALIZER_BAND_8,
 399           .mid = 0x96,
 400           .req = 19,
 401           .direct = EFX_DIR_OUT,
 402           .def_val = 0x00000000
 403         },
 404         { .name = "EQ Band9",
 405           .parent_nid = EQUALIZER,
 406           .nid = EQUALIZER_BAND_9,
 407           .mid = 0x96,
 408           .req = 20,
 409           .direct = EFX_DIR_OUT,
 410           .def_val = 0x00000000
 411         }
 412 };
 413 #endif
 414
 415 /* Voice FX Presets */
 416 #define VOICEFX_MAX_PARAM_COUNT 9
 417
 418 struct ct_voicefx {
 419         char *name;
 420         hda_nid_t nid;
 421         int mid;
 422         int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
 423 };
 424
 425 struct ct_voicefx_preset {
 426         char *name; /*preset name*/
 427         unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
 428 };
 429
 430 static const struct ct_voicefx ca0132_voicefx = {
 431         .name = "VoiceFX Capture Switch",
 432         .nid = VOICEFX,
 433         .mid = 0x95,
 434         .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
 435 };
 436
 437 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
 438         { .name = "Neutral",
 439           .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
 440                     0x44FA0000, 0x3F800000, 0x3F800000,
 441                     0x3F800000, 0x00000000, 0x00000000 }
 442         },
 443         { .name = "Female2Male",
 444           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 445                     0x44FA0000, 0x3F19999A, 0x3F866666,
 446                     0x3F800000, 0x00000000, 0x00000000 }
 447         },
 448         { .name = "Male2Female",
 449           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 450                     0x450AC000, 0x4017AE14, 0x3F6B851F,
 451                     0x3F800000, 0x00000000, 0x00000000 }
 452         },
 453         { .name = "ScrappyKid",
 454           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 455                     0x44FA0000, 0x40400000, 0x3F28F5C3,
 456                     0x3F800000, 0x00000000, 0x00000000 }
 457         },
 458         { .name = "Elderly",
 459           .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
 460                     0x44E10000, 0x3FB33333, 0x3FB9999A,
 461                     0x3F800000, 0x3E3A2E43, 0x00000000 }
 462         },
 463         { .name = "Orc",
 464           .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
 465                     0x45098000, 0x3F266666, 0x3FC00000,
 466                     0x3F800000, 0x00000000, 0x00000000 }
 467         },
 468         { .name = "Elf",
 469           .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
 470                     0x45193000, 0x3F8E147B, 0x3F75C28F,
 471                     0x3F800000, 0x00000000, 0x00000000 }
 472         },
 473         { .name = "Dwarf",
 474           .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
 475                     0x45007000, 0x3F451EB8, 0x3F7851EC,
 476                     0x3F800000, 0x00000000, 0x00000000 }
 477         },
 478         { .name = "AlienBrute",
 479           .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
 480                     0x451F6000, 0x3F266666, 0x3FA7D945,
 481                     0x3F800000, 0x3CF5C28F, 0x00000000 }
 482         },
 483         { .name = "Robot",
 484           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 485                     0x44FA0000, 0x3FB2718B, 0x3F800000,
 486                     0xBC07010E, 0x00000000, 0x00000000 }
 487         },
 488         { .name = "Marine",
 489           .vals = { 0x3F800000, 0x43C20000, 0x44906000,
 490                     0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
 491                     0x3F0A3D71, 0x00000000, 0x00000000 }
 492         },
 493         { .name = "Emo",
 494           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 495                     0x44FA0000, 0x3F800000, 0x3F800000,
 496                     0x3E4CCCCD, 0x00000000, 0x00000000 }
 497         },
 498         { .name = "DeepVoice",
 499           .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
 500                     0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
 501                     0x3F800000, 0x00000000, 0x00000000 }
 502         },
 503         { .name = "Munchkin",
 504           .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
 505                     0x44FA0000, 0x3F800000, 0x3F1A043C,
 506                     0x3F800000, 0x00000000, 0x00000000 }
 507         }
 508 };
 509
 510 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
 511
 512 #define EQ_PRESET_MAX_PARAM_COUNT 11
 513
 514 struct ct_eq {
 515         char *name;
 516         hda_nid_t nid;
 517         int mid;
 518         int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
 519 };
 520
 521 struct ct_eq_preset {
 522         char *name; /*preset name*/
 523         unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
 524 };
 525
 526 static const struct ct_eq ca0132_alt_eq_enum = {
 527         .name = "FX: Equalizer Preset Switch",
 528         .nid = EQ_PRESET_ENUM,
 529         .mid = 0x96,
 530         .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
 531 };
 532
 533
 534 static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
 535         { .name = "Flat",
 536          .vals = { 0x00000000, 0x00000000, 0x00000000,
 537                    0x00000000, 0x00000000, 0x00000000,
 538                    0x00000000, 0x00000000, 0x00000000,
 539                    0x00000000, 0x00000000            }
 540         },
 541         { .name = "Acoustic",
 542          .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
 543                    0x40000000, 0x00000000, 0x00000000,
 544                    0x00000000, 0x00000000, 0x40000000,
 545                    0x40000000, 0x40000000            }
 546         },
 547         { .name = "Classical",
 548          .vals = { 0x00000000, 0x00000000, 0x40C00000,
 549                    0x40C00000, 0x40466666, 0x00000000,
 550                    0x00000000, 0x00000000, 0x00000000,
 551                    0x40466666, 0x40466666            }
 552         },
 553         { .name = "Country",
 554          .vals = { 0x00000000, 0xBF99999A, 0x00000000,
 555                    0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
 556                    0x00000000, 0x00000000, 0x40000000,
 557                    0x40466666, 0x40800000            }
 558         },
 559         { .name = "Dance",
 560          .vals = { 0x00000000, 0xBF99999A, 0x40000000,
 561                    0x40466666, 0x40866666, 0xBF99999A,
 562                    0xBF99999A, 0x00000000, 0x00000000,
 563                    0x40800000, 0x40800000            }
 564         },
 565         { .name = "Jazz",
 566          .vals = { 0x00000000, 0x00000000, 0x00000000,
 567                    0x3F8CCCCD, 0x40800000, 0x40800000,
 568                    0x40800000, 0x00000000, 0x3F8CCCCD,
 569                    0x40466666, 0x40466666            }
 570         },
 571         { .name = "New Age",
 572          .vals = { 0x00000000, 0x00000000, 0x40000000,
 573                    0x40000000, 0x00000000, 0x00000000,
 574                    0x00000000, 0x3F8CCCCD, 0x40000000,
 575                    0x40000000, 0x40000000            }
 576         },
 577         { .name = "Pop",
 578          .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
 579                    0x40000000, 0x40000000, 0x00000000,
 580                    0xBF99999A, 0xBF99999A, 0x00000000,
 581                    0x40466666, 0x40C00000            }
 582         },
 583         { .name = "Rock",
 584          .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
 585                    0x3F8CCCCD, 0x40000000, 0xBF99999A,
 586                    0xBF99999A, 0x00000000, 0x00000000,
 587                    0x40800000, 0x40800000            }
 588         },
 589         { .name = "Vocal",
 590          .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
 591                    0xBF99999A, 0x00000000, 0x40466666,
 592                    0x40800000, 0x40466666, 0x00000000,
 593                    0x00000000, 0x3F8CCCCD            }
 594         }
 595 };
 596
 597 /*
 598  * DSP reqs for handling full-range speakers/bass redirection. If a speaker is
 599  * set as not being full range, and bass redirection is enabled, all
 600  * frequencies below the crossover frequency are redirected to the LFE
 601  * channel. If the surround configuration has no LFE channel, this can't be
 602  * enabled. X-Bass must be disabled when using these.
 603  */
 604 enum speaker_range_reqs {
 605         SPEAKER_BASS_REDIRECT            = 0x15,
 606         SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16,
 607         /* Between 0x16-0x1a are the X-Bass reqs. */
 608         SPEAKER_FULL_RANGE_FRONT_L_R     = 0x1a,
 609         SPEAKER_FULL_RANGE_CENTER_LFE    = 0x1b,
 610         SPEAKER_FULL_RANGE_REAR_L_R      = 0x1c,
 611         SPEAKER_FULL_RANGE_SURROUND_L_R  = 0x1d,
 612         SPEAKER_BASS_REDIRECT_SUB_GAIN   = 0x1e,
 613 };
 614
 615 /*
 616  * Definitions for the DSP req's to handle speaker tuning. These all belong to
 617  * module ID 0x96, the output effects module.
 618  */
 619 enum speaker_tuning_reqs {
 620         /*
 621          * Currently, this value is always set to 0.0f. However, on Windows,
 622          * when selecting certain headphone profiles on the new Sound Blaster
 623          * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is
 624          * sent. This gets the speaker EQ address area, which is then used to
 625          * send over (presumably) an equalizer profile for the specific
 626          * headphone setup. It is sent using the same method the DSP
 627          * firmware is uploaded with, which I believe is why the 'ctspeq.bin'
 628          * file exists in linux firmware tree but goes unused. It would also
 629          * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused.
 630          * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is
 631          * set to 1.0f.
 632          */
 633         SPEAKER_TUNING_USE_SPEAKER_EQ           = 0x1f,
 634         SPEAKER_TUNING_ENABLE_CENTER_EQ         = 0x20,
 635         SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL     = 0x21,
 636         SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL    = 0x22,
 637         SPEAKER_TUNING_CENTER_VOL_LEVEL         = 0x23,
 638         SPEAKER_TUNING_LFE_VOL_LEVEL            = 0x24,
 639         SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL      = 0x25,
 640         SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL     = 0x26,
 641         SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL  = 0x27,
 642         SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28,
 643         /*
 644          * Inversion is used when setting headphone virtualization to line
 645          * out. Not sure why this is, but it's the only place it's ever used.
 646          */
 647         SPEAKER_TUNING_FRONT_LEFT_INVERT        = 0x29,
 648         SPEAKER_TUNING_FRONT_RIGHT_INVERT       = 0x2a,
 649         SPEAKER_TUNING_CENTER_INVERT            = 0x2b,
 650         SPEAKER_TUNING_LFE_INVERT               = 0x2c,
 651         SPEAKER_TUNING_REAR_LEFT_INVERT         = 0x2d,
 652         SPEAKER_TUNING_REAR_RIGHT_INVERT        = 0x2e,
 653         SPEAKER_TUNING_SURROUND_LEFT_INVERT     = 0x2f,
 654         SPEAKER_TUNING_SURROUND_RIGHT_INVERT    = 0x30,
 655         /* Delay is used when setting surround speaker distance in Windows. */
 656         SPEAKER_TUNING_FRONT_LEFT_DELAY         = 0x31,
 657         SPEAKER_TUNING_FRONT_RIGHT_DELAY        = 0x32,
 658         SPEAKER_TUNING_CENTER_DELAY             = 0x33,
 659         SPEAKER_TUNING_LFE_DELAY                = 0x34,
 660         SPEAKER_TUNING_REAR_LEFT_DELAY          = 0x35,
 661         SPEAKER_TUNING_REAR_RIGHT_DELAY         = 0x36,
 662         SPEAKER_TUNING_SURROUND_LEFT_DELAY      = 0x37,
 663         SPEAKER_TUNING_SURROUND_RIGHT_DELAY     = 0x38,
 664         /* Of these two, only mute seems to ever be used. */
 665         SPEAKER_TUNING_MAIN_VOLUME              = 0x39,
 666         SPEAKER_TUNING_MUTE                     = 0x3a,
 667 };
 668
 669 /* Surround output channel count configuration structures. */
 670 #define SPEAKER_CHANNEL_CFG_COUNT 5
 671 enum {
 672         SPEAKER_CHANNELS_2_0,
 673         SPEAKER_CHANNELS_2_1,
 674         SPEAKER_CHANNELS_4_0,
 675         SPEAKER_CHANNELS_4_1,
 676         SPEAKER_CHANNELS_5_1,
 677 };
 678
 679 struct ca0132_alt_speaker_channel_cfg {
 680         char *name;
 681         unsigned int val;
 682 };
 683
 684 static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = {
 685         { .name = "2.0",
 686           .val = FLOAT_ONE
 687         },
 688         { .name = "2.1",
 689           .val = FLOAT_TWO
 690         },
 691         { .name = "4.0",
 692           .val = FLOAT_FIVE
 693         },
 694         { .name = "4.1",
 695           .val = FLOAT_SIX
 696         },
 697         { .name = "5.1",
 698           .val = FLOAT_EIGHT
 699         }
 700 };
 701
 702 /*
 703  * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
 704  * and I don't know what the third req is, but it's always zero. I assume it's
 705  * some sort of update or set command to tell the DSP there's new volume info.
 706  */
 707 #define DSP_VOL_OUT 0
 708 #define DSP_VOL_IN  1
 709
 710 struct ct_dsp_volume_ctl {
 711         hda_nid_t vnid;
 712         int mid; /* module ID*/
 713         unsigned int reqs[3]; /* scp req ID */
 714 };
 715
 716 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
 717         { .vnid = VNID_SPK,
 718           .mid = 0x32,
 719           .reqs = {3, 4, 2}
 720         },
 721         { .vnid = VNID_MIC,
 722           .mid = 0x37,
 723           .reqs = {2, 3, 1}
 724         }
 725 };
 726
 727 /* Values for ca0113_mmio_command_set for selecting output. */
 728 #define AE_CA0113_OUT_SET_COMMANDS 6
 729 struct ae_ca0113_output_set {
 730         unsigned int group[AE_CA0113_OUT_SET_COMMANDS];
 731         unsigned int target[AE_CA0113_OUT_SET_COMMANDS];
 732         unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS];
 733 };
 734
 735 static const struct ae_ca0113_output_set ae5_ca0113_output_presets = {
 736         .group =  { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
 737         .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
 738                     /* Speakers. */
 739         .vals =   { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
 740                     /* Headphones. */
 741                     { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } },
 742 };
 743
 744 static const struct ae_ca0113_output_set ae7_ca0113_output_presets = {
 745         .group  = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
 746         .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
 747                     /* Speakers. */
 748         .vals   = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
 749                     /* Headphones. */
 750                     { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } },
 751 };
 752
 753 /* ae5 ca0113 command sequences to set headphone gain levels. */
 754 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4
 755 struct ae5_headphone_gain_set {
 756         char *name;
 757         unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS];
 758 };
 759
 760 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = {
 761         { .name = "Low (16-31",
 762           .vals = { 0xff, 0x2c, 0xf5, 0x32 }
 763         },
 764         { .name = "Medium (32-149",
 765           .vals = { 0x38, 0xa8, 0x3e, 0x4c }
 766         },
 767         { .name = "High (150-600",
 768           .vals = { 0xff, 0xff, 0xff, 0x7f }
 769         }
 770 };
 771
 772 struct ae5_filter_set {
 773         char *name;
 774         unsigned int val;
 775 };
 776
 777 static const struct ae5_filter_set ae5_filter_presets[] = {
 778         { .name = "Slow Roll Off",
 779           .val = 0xa0
 780         },
 781         { .name = "Minimum Phase",
 782           .val = 0xc0
 783         },
 784         { .name = "Fast Roll Off",
 785           .val = 0x80
 786         }
 787 };
 788
 789 /*
 790  * Data structures for storing audio router remapping data. These are used to
 791  * remap a currently active streams ports.
 792  */
 793 struct chipio_stream_remap_data {
 794         unsigned int stream_id;
 795         unsigned int count;
 796
 797         unsigned int offset[16];
 798         unsigned int value[16];
 799 };
 800
 801 static const struct chipio_stream_remap_data stream_remap_data[] = {
 802         { .stream_id = 0x14,
 803           .count     = 0x04,
 804           .offset    = { 0x00, 0x04, 0x08, 0x0c },
 805           .value     = { 0x0001f8c0, 0x0001f9c1, 0x0001fac6, 0x0001fbc7 },
 806         },
 807         { .stream_id = 0x0c,
 808           .count     = 0x0c,
 809           .offset    = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x18, 0x1c,
 810                          0x20, 0x24, 0x28, 0x2c },
 811           .value     = { 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3,
 812                          0x0001e2c4, 0x0001e3c5, 0x0001e8c6, 0x0001e9c7,
 813                          0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb },
 814         },
 815         { .stream_id = 0x0c,
 816           .count     = 0x08,
 817           .offset    = { 0x08, 0x0c, 0x10, 0x14, 0x20, 0x24, 0x28, 0x2c },
 818           .value     = { 0x000140c2, 0x000141c3, 0x000150c4, 0x000151c5,
 819                          0x000142c8, 0x000143c9, 0x000152ca, 0x000153cb },
 820         }
 821 };
 822
 823 enum hda_cmd_vendor_io {
 824         /* for DspIO node */
 825         VENDOR_DSPIO_SCP_WRITE_DATA_LOW      = 0x000,
 826         VENDOR_DSPIO_SCP_WRITE_DATA_HIGH     = 0x100,
 827
 828         VENDOR_DSPIO_STATUS                  = 0xF01,
 829         VENDOR_DSPIO_SCP_POST_READ_DATA      = 0x702,
 830         VENDOR_DSPIO_SCP_READ_DATA           = 0xF02,
 831         VENDOR_DSPIO_DSP_INIT                = 0x703,
 832         VENDOR_DSPIO_SCP_POST_COUNT_QUERY    = 0x704,
 833         VENDOR_DSPIO_SCP_READ_COUNT          = 0xF04,
 834
 835         /* for ChipIO node */
 836         VENDOR_CHIPIO_ADDRESS_LOW            = 0x000,
 837         VENDOR_CHIPIO_ADDRESS_HIGH           = 0x100,
 838         VENDOR_CHIPIO_STREAM_FORMAT          = 0x200,
 839         VENDOR_CHIPIO_DATA_LOW               = 0x300,
 840         VENDOR_CHIPIO_DATA_HIGH              = 0x400,
 841
 842         VENDOR_CHIPIO_8051_WRITE_DIRECT      = 0x500,
 843         VENDOR_CHIPIO_8051_READ_DIRECT       = 0xD00,
 844
 845         VENDOR_CHIPIO_GET_PARAMETER          = 0xF00,
 846         VENDOR_CHIPIO_STATUS                 = 0xF01,
 847         VENDOR_CHIPIO_HIC_POST_READ          = 0x702,
 848         VENDOR_CHIPIO_HIC_READ_DATA          = 0xF03,
 849
 850         VENDOR_CHIPIO_8051_DATA_WRITE        = 0x707,
 851         VENDOR_CHIPIO_8051_DATA_READ         = 0xF07,
 852         VENDOR_CHIPIO_8051_PMEM_READ         = 0xF08,
 853         VENDOR_CHIPIO_8051_IRAM_WRITE        = 0x709,
 854         VENDOR_CHIPIO_8051_IRAM_READ         = 0xF09,
 855
 856         VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE   = 0x70A,
 857         VENDOR_CHIPIO_CT_EXTENSIONS_GET      = 0xF0A,
 858
 859         VENDOR_CHIPIO_PLL_PMU_WRITE          = 0x70C,
 860         VENDOR_CHIPIO_PLL_PMU_READ           = 0xF0C,
 861         VENDOR_CHIPIO_8051_ADDRESS_LOW       = 0x70D,
 862         VENDOR_CHIPIO_8051_ADDRESS_HIGH      = 0x70E,
 863         VENDOR_CHIPIO_FLAG_SET               = 0x70F,
 864         VENDOR_CHIPIO_FLAGS_GET              = 0xF0F,
 865         VENDOR_CHIPIO_PARAM_SET              = 0x710,
 866         VENDOR_CHIPIO_PARAM_GET              = 0xF10,
 867
 868         VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET  = 0x711,
 869         VENDOR_CHIPIO_PORT_ALLOC_SET         = 0x712,
 870         VENDOR_CHIPIO_PORT_ALLOC_GET         = 0xF12,
 871         VENDOR_CHIPIO_PORT_FREE_SET          = 0x713,
 872
 873         VENDOR_CHIPIO_PARAM_EX_ID_GET        = 0xF17,
 874         VENDOR_CHIPIO_PARAM_EX_ID_SET        = 0x717,
 875         VENDOR_CHIPIO_PARAM_EX_VALUE_GET     = 0xF18,
 876         VENDOR_CHIPIO_PARAM_EX_VALUE_SET     = 0x718,
 877
 878         VENDOR_CHIPIO_DMIC_CTL_SET           = 0x788,
 879         VENDOR_CHIPIO_DMIC_CTL_GET           = 0xF88,
 880         VENDOR_CHIPIO_DMIC_PIN_SET           = 0x789,
 881         VENDOR_CHIPIO_DMIC_PIN_GET           = 0xF89,
 882         VENDOR_CHIPIO_DMIC_MCLK_SET          = 0x78A,
 883         VENDOR_CHIPIO_DMIC_MCLK_GET          = 0xF8A,
 884
 885         VENDOR_CHIPIO_EAPD_SEL_SET           = 0x78D
 886 };
 887
 888 /*
 889  *  Control flag IDs
 890  */
 891 enum control_flag_id {
 892         /* Connection manager stream setup is bypassed/enabled */
 893         CONTROL_FLAG_C_MGR                  = 0,
 894         /* DSP DMA is bypassed/enabled */
 895         CONTROL_FLAG_DMA                    = 1,
 896         /* 8051 'idle' mode is disabled/enabled */
 897         CONTROL_FLAG_IDLE_ENABLE            = 2,
 898         /* Tracker for the SPDIF-in path is bypassed/enabled */
 899         CONTROL_FLAG_TRACKER                = 3,
 900         /* DigitalOut to Spdif2Out connection is disabled/enabled */
 901         CONTROL_FLAG_SPDIF2OUT              = 4,
 902         /* Digital Microphone is disabled/enabled */
 903         CONTROL_FLAG_DMIC                   = 5,
 904         /* ADC_B rate is 48 kHz/96 kHz */
 905         CONTROL_FLAG_ADC_B_96KHZ            = 6,
 906         /* ADC_C rate is 48 kHz/96 kHz */
 907         CONTROL_FLAG_ADC_C_96KHZ            = 7,
 908         /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
 909         CONTROL_FLAG_DAC_96KHZ              = 8,
 910         /* DSP rate is 48 kHz/96 kHz */
 911         CONTROL_FLAG_DSP_96KHZ              = 9,
 912         /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
 913         CONTROL_FLAG_SRC_CLOCK_196MHZ       = 10,
 914         /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
 915         CONTROL_FLAG_SRC_RATE_96KHZ         = 11,
 916         /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
 917         CONTROL_FLAG_DECODE_LOOP            = 12,
 918         /* De-emphasis filter on DAC-1 disabled/enabled */
 919         CONTROL_FLAG_DAC1_DEEMPHASIS        = 13,
 920         /* De-emphasis filter on DAC-2 disabled/enabled */
 921         CONTROL_FLAG_DAC2_DEEMPHASIS        = 14,
 922         /* De-emphasis filter on DAC-3 disabled/enabled */
 923         CONTROL_FLAG_DAC3_DEEMPHASIS        = 15,
 924         /* High-pass filter on ADC_B disabled/enabled */
 925         CONTROL_FLAG_ADC_B_HIGH_PASS        = 16,
 926         /* High-pass filter on ADC_C disabled/enabled */
 927         CONTROL_FLAG_ADC_C_HIGH_PASS        = 17,
 928         /* Common mode on Port_A disabled/enabled */
 929         CONTROL_FLAG_PORT_A_COMMON_MODE     = 18,
 930         /* Common mode on Port_D disabled/enabled */
 931         CONTROL_FLAG_PORT_D_COMMON_MODE     = 19,
 932         /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
 933         CONTROL_FLAG_PORT_A_10KOHM_LOAD     = 20,
 934         /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
 935         CONTROL_FLAG_PORT_D_10KOHM_LOAD     = 21,
 936         /* ASI rate is 48kHz/96kHz */
 937         CONTROL_FLAG_ASI_96KHZ              = 22,
 938         /* DAC power settings able to control attached ports no/yes */
 939         CONTROL_FLAG_DACS_CONTROL_PORTS     = 23,
 940         /* Clock Stop OK reporting is disabled/enabled */
 941         CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
 942         /* Number of control flags */
 943         CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
 944 };
 945
 946 /*
 947  * Control parameter IDs
 948  */
 949 enum control_param_id {
 950         /* 0: None, 1: Mic1In*/
 951         CONTROL_PARAM_VIP_SOURCE               = 1,
 952         /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
 953         CONTROL_PARAM_SPDIF1_SOURCE            = 2,
 954         /* Port A output stage gain setting to use when 16 Ohm output
 955          * impedance is selected*/
 956         CONTROL_PARAM_PORTA_160OHM_GAIN        = 8,
 957         /* Port D output stage gain setting to use when 16 Ohm output
 958          * impedance is selected*/
 959         CONTROL_PARAM_PORTD_160OHM_GAIN        = 10,
 960
 961         /*
 962          * This control param name was found in the 8051 memory, and makes
 963          * sense given the fact the AE-5 uses it and has the ASI flag set.
 964          */
 965         CONTROL_PARAM_ASI                      = 23,
 966
 967         /* Stream Control */
 968
 969         /* Select stream with the given ID */
 970         CONTROL_PARAM_STREAM_ID                = 24,
 971         /* Source connection point for the selected stream */
 972         CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
 973         /* Destination connection point for the selected stream */
 974         CONTROL_PARAM_STREAM_DEST_CONN_POINT   = 26,
 975         /* Number of audio channels in the selected stream */
 976         CONTROL_PARAM_STREAMS_CHANNELS         = 27,
 977         /*Enable control for the selected stream */
 978         CONTROL_PARAM_STREAM_CONTROL           = 28,
 979
 980         /* Connection Point Control */
 981
 982         /* Select connection point with the given ID */
 983         CONTROL_PARAM_CONN_POINT_ID            = 29,
 984         /* Connection point sample rate */
 985         CONTROL_PARAM_CONN_POINT_SAMPLE_RATE   = 30,
 986
 987         /* Node Control */
 988
 989         /* Select HDA node with the given ID */
 990         CONTROL_PARAM_NODE_ID                  = 31
 991 };
 992
 993 /*
 994  *  Dsp Io Status codes
 995  */
 996 enum hda_vendor_status_dspio {
 997         /* Success */
 998         VENDOR_STATUS_DSPIO_OK                       = 0x00,
 999         /* Busy, unable to accept new command, the host must retry */
1000         VENDOR_STATUS_DSPIO_BUSY                     = 0x01,
1001         /* SCP command queue is full */
1002         VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL   = 0x02,
1003         /* SCP response queue is empty */
1004         VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
1005 };
1006
1007 /*
1008  *  Chip Io Status codes
1009  */
1010 enum hda_vendor_status_chipio {
1011         /* Success */
1012         VENDOR_STATUS_CHIPIO_OK   = 0x00,
1013         /* Busy, unable to accept new command, the host must retry */
1014         VENDOR_STATUS_CHIPIO_BUSY = 0x01
1015 };
1016
1017 /*
1018  *  CA0132 sample rate
1019  */
1020 enum ca0132_sample_rate {
1021         SR_6_000        = 0x00,
1022         SR_8_000        = 0x01,
1023         SR_9_600        = 0x02,
1024         SR_11_025       = 0x03,
1025         SR_16_000       = 0x04,
1026         SR_22_050       = 0x05,
1027         SR_24_000       = 0x06,
1028         SR_32_000       = 0x07,
1029         SR_44_100       = 0x08,
1030         SR_48_000       = 0x09,
1031         SR_88_200       = 0x0A,
1032         SR_96_000       = 0x0B,
1033         SR_144_000      = 0x0C,
1034         SR_176_400      = 0x0D,
1035         SR_192_000      = 0x0E,
1036         SR_384_000      = 0x0F,
1037
1038         SR_COUNT        = 0x10,
1039
1040         SR_RATE_UNKNOWN = 0x1F
1041 };
1042
1043 enum dsp_download_state {
1044         DSP_DOWNLOAD_FAILED = -1,
1045         DSP_DOWNLOAD_INIT   = 0,
1046         DSP_DOWNLOADING     = 1,
1047         DSP_DOWNLOADED      = 2
1048 };
1049
1050 /* retrieve parameters from hda format */
1051 #define get_hdafmt_chs(fmt)     (fmt & 0xf)
1052 #define get_hdafmt_bits(fmt)    ((fmt >> 4) & 0x7)
1053 #define get_hdafmt_rate(fmt)    ((fmt >> 8) & 0x7f)
1054 #define get_hdafmt_type(fmt)    ((fmt >> 15) & 0x1)
1055
1056 /*
1057  * CA0132 specific
1058  */
1059
1060 struct ca0132_spec {
1061         const struct snd_kcontrol_new *mixers[5];
1062         unsigned int num_mixers;
1063         const struct hda_verb *base_init_verbs;
1064         const struct hda_verb *base_exit_verbs;
1065         const struct hda_verb *chip_init_verbs;
1066         const struct hda_verb *desktop_init_verbs;
1067         struct hda_verb *spec_init_verbs;
1068         struct auto_pin_cfg autocfg;
1069
1070         /* Nodes configurations */
1071         struct hda_multi_out multiout;
1072         hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
1073         hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
1074         unsigned int num_outputs;
1075         hda_nid_t input_pins[AUTO_PIN_LAST];
1076         hda_nid_t adcs[AUTO_PIN_LAST];
1077         hda_nid_t dig_out;
1078         hda_nid_t dig_in;
1079         unsigned int num_inputs;
1080         hda_nid_t shared_mic_nid;
1081         hda_nid_t shared_out_nid;
1082         hda_nid_t unsol_tag_hp;
1083         hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
1084         hda_nid_t unsol_tag_amic1;
1085
1086         /* chip access */
1087         struct mutex chipio_mutex; /* chip access mutex */
1088         u32 curr_chip_addx;
1089
1090         /* DSP download related */
1091         enum dsp_download_state dsp_state;
1092         unsigned int dsp_stream_id;
1093         unsigned int wait_scp;
1094         unsigned int wait_scp_header;
1095         unsigned int wait_num_data;
1096         unsigned int scp_resp_header;
1097         unsigned int scp_resp_data[4];
1098         unsigned int scp_resp_count;
1099         bool startup_check_entered;
1100         bool dsp_reload;
1101
1102         /* mixer and effects related */
1103         unsigned char dmic_ctl;
1104         int cur_out_type;
1105         int cur_mic_type;
1106         long vnode_lvol[VNODES_COUNT];
1107         long vnode_rvol[VNODES_COUNT];
1108         long vnode_lswitch[VNODES_COUNT];
1109         long vnode_rswitch[VNODES_COUNT];
1110         long effects_switch[EFFECTS_COUNT];
1111         long voicefx_val;
1112         long cur_mic_boost;
1113         /* ca0132_alt control related values */
1114         unsigned char in_enum_val;
1115         unsigned char out_enum_val;
1116         unsigned char channel_cfg_val;
1117         unsigned char speaker_range_val[2];
1118         unsigned char mic_boost_enum_val;
1119         unsigned char smart_volume_setting;
1120         unsigned char bass_redirection_val;
1121         long bass_redirect_xover_freq;
1122         long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
1123         long xbass_xover_freq;
1124         long eq_preset_val;
1125         unsigned int tlv[4];
1126         struct hda_vmaster_mute_hook vmaster_mute;
1127         /* AE-5 Control values */
1128         unsigned char ae5_headphone_gain_val;
1129         unsigned char ae5_filter_val;
1130         /* ZxR Control Values */
1131         unsigned char zxr_gain_set;
1132
1133         struct hda_codec *codec;
1134         struct delayed_work unsol_hp_work;
1135         int quirk;
1136
1137 #ifdef ENABLE_TUNING_CONTROLS
1138         long cur_ctl_vals[TUNING_CTLS_COUNT];
1139 #endif
1140         /*
1141          * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
1142          * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
1143          * things.
1144          */
1145         bool use_pci_mmio;
1146         void __iomem *mem_base;
1147
1148         /*
1149          * Whether or not to use the alt functions like alt_select_out,
1150          * alt_select_in, etc. Only used on desktop codecs for now, because of
1151          * surround sound support.
1152          */
1153         bool use_alt_functions;
1154
1155         /*
1156          * Whether or not to use alt controls:  volume effect sliders, EQ
1157          * presets, smart volume presets, and new control names with FX prefix.
1158          * Renames PlayEnhancement and CrystalVoice too.
1159          */
1160         bool use_alt_controls;
1161 };
1162
1163 /*
1164  * CA0132 quirks table
1165  */
1166 enum {
1167         QUIRK_NONE,
1168         QUIRK_ALIENWARE,
1169         QUIRK_ALIENWARE_M17XR4,
1170         QUIRK_SBZ,
1171         QUIRK_ZXR,
1172         QUIRK_ZXR_DBPRO,
1173         QUIRK_R3DI,
1174         QUIRK_R3D,
1175         QUIRK_AE5,
1176         QUIRK_AE7,
1177 };
1178
1179 #ifdef CONFIG_PCI
1180 #define ca0132_quirk(spec)              ((spec)->quirk)
1181 #define ca0132_use_pci_mmio(spec)       ((spec)->use_pci_mmio)
1182 #define ca0132_use_alt_functions(spec)  ((spec)->use_alt_functions)
1183 #define ca0132_use_alt_controls(spec)   ((spec)->use_alt_controls)
1184 #else
1185 #define ca0132_quirk(spec)              ({ (void)(spec); QUIRK_NONE; })
1186 #define ca0132_use_alt_functions(spec)  ({ (void)(spec); false; })
1187 #define ca0132_use_pci_mmio(spec)       ({ (void)(spec); false; })
1188 #define ca0132_use_alt_controls(spec)   ({ (void)(spec); false; })
1189 #endif
1190
1191 static const struct hda_pintbl alienware_pincfgs[] = {
1192         { 0x0b, 0x90170110 }, /* Builtin Speaker */
1193         { 0x0c, 0x411111f0 }, /* N/A */
1194         { 0x0d, 0x411111f0 }, /* N/A */
1195         { 0x0e, 0x411111f0 }, /* N/A */
1196         { 0x0f, 0x0321101f }, /* HP */
1197         { 0x10, 0x411111f0 }, /* Headset?  disabled for now */
1198         { 0x11, 0x03a11021 }, /* Mic */
1199         { 0x12, 0xd5a30140 }, /* Builtin Mic */
1200         { 0x13, 0x411111f0 }, /* N/A */
1201         { 0x18, 0x411111f0 }, /* N/A */
1202         {}
1203 };
1204
1205 /* Sound Blaster Z pin configs taken from Windows Driver */
1206 static const struct hda_pintbl sbz_pincfgs[] = {
1207         { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1208         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1209         { 0x0d, 0x014510f0 }, /* Digital Out */
1210         { 0x0e, 0x01c510f0 }, /* SPDIF In */
1211         { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1212         { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1213         { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1214         { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1215         { 0x13, 0x908700f0 }, /* What U Hear In*/
1216         { 0x18, 0x50d000f0 }, /* N/A */
1217         {}
1218 };
1219
1220 /* Sound Blaster ZxR pin configs taken from Windows Driver */
1221 static const struct hda_pintbl zxr_pincfgs[] = {
1222         { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
1223         { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
1224         { 0x0d, 0x014510f0 }, /* Digital Out */
1225         { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
1226         { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
1227         { 0x10, 0x01017111 }, /* Port D -- Center/LFE */
1228         { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
1229         { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
1230         { 0x13, 0x908700f0 }, /* What U Hear In*/
1231         { 0x18, 0x50d000f0 }, /* N/A */
1232         {}
1233 };
1234
1235 /* Recon3D pin configs taken from Windows Driver */
1236 static const struct hda_pintbl r3d_pincfgs[] = {
1237         { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1238         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1239         { 0x0d, 0x014510f0 }, /* Digital Out */
1240         { 0x0e, 0x01c520f0 }, /* SPDIF In */
1241         { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1242         { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1243         { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1244         { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1245         { 0x13, 0x908700f0 }, /* What U Hear In*/
1246         { 0x18, 0x50d000f0 }, /* N/A */
1247         {}
1248 };
1249
1250 /* Sound Blaster AE-5 pin configs taken from Windows Driver */
1251 static const struct hda_pintbl ae5_pincfgs[] = {
1252         { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1253         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1254         { 0x0d, 0x014510f0 }, /* Digital Out */
1255         { 0x0e, 0x01c510f0 }, /* SPDIF In */
1256         { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1257         { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1258         { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1259         { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1260         { 0x13, 0x908700f0 }, /* What U Hear In*/
1261         { 0x18, 0x50d000f0 }, /* N/A */
1262         {}
1263 };
1264
1265 /* Recon3D integrated pin configs taken from Windows Driver */
1266 static const struct hda_pintbl r3di_pincfgs[] = {
1267         { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1268         { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1269         { 0x0d, 0x014510f0 }, /* Digital Out */
1270         { 0x0e, 0x41c520f0 }, /* SPDIF In */
1271         { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1272         { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1273         { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1274         { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1275         { 0x13, 0x908700f0 }, /* What U Hear In*/
1276         { 0x18, 0x500000f0 }, /* N/A */
1277         {}
1278 };
1279
1280 static const struct hda_pintbl ae7_pincfgs[] = {
1281         { 0x0b, 0x01017010 },
1282         { 0x0c, 0x014510f0 },
1283         { 0x0d, 0x414510f0 },
1284         { 0x0e, 0x01c520f0 },
1285         { 0x0f, 0x01017114 },
1286         { 0x10, 0x01017011 },
1287         { 0x11, 0x018170ff },
1288         { 0x12, 0x01a170f0 },
1289         { 0x13, 0x908700f0 },
1290         { 0x18, 0x500000f0 },
1291         {}
1292 };
1293
1294 static const struct snd_pci_quirk ca0132_quirks[] = {
1295         SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1296         SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1297         SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
1298         SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1299         SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1300         SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1301         SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ),
1302         SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ),
1303         SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1304         SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1305         SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1306         SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),
1307         SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1308         SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D),
1309         SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
1310         SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5),
1311         SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7),
1312         {}
1313 };
1314
1315 /* Output selection quirk info structures. */
1316 #define MAX_QUIRK_MMIO_GPIO_SET_VALS 3
1317 #define MAX_QUIRK_SCP_SET_VALS 2
1318 struct ca0132_alt_out_set_info {
1319         unsigned int dac2port; /* ParamID 0x0d value. */
1320
1321         bool has_hda_gpio;
1322         char hda_gpio_pin;
1323         char hda_gpio_set;
1324
1325         unsigned int mmio_gpio_count;
1326         char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS];
1327         char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS];
1328
1329         unsigned int scp_cmds_count;
1330         unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS];
1331         unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS];
1332         unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS];
1333
1334         bool has_chipio_write;
1335         unsigned int chipio_write_addr;
1336         unsigned int chipio_write_data;
1337 };
1338
1339 struct ca0132_alt_out_set_quirk_data {
1340         int quirk_id;
1341
1342         bool has_headphone_gain;
1343         bool is_ae_series;
1344
1345         struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS];
1346 };
1347
1348 static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = {
1349         { .quirk_id = QUIRK_R3DI,
1350           .has_headphone_gain = false,
1351           .is_ae_series       = false,
1352           .out_set_info = {
1353                 /* Speakers. */
1354                 { .dac2port         = 0x24,
1355                   .has_hda_gpio     = true,
1356                   .hda_gpio_pin     = 2,
1357                   .hda_gpio_set     = 1,
1358                   .mmio_gpio_count  = 0,
1359                   .scp_cmds_count   = 0,
1360                   .has_chipio_write = false,
1361                 },
1362                 /* Headphones. */
1363                 { .dac2port         = 0x21,
1364                   .has_hda_gpio     = true,
1365                   .hda_gpio_pin     = 2,
1366                   .hda_gpio_set     = 0,
1367                   .mmio_gpio_count  = 0,
1368                   .scp_cmds_count   = 0,
1369                   .has_chipio_write = false,
1370                 } },
1371         },
1372         { .quirk_id = QUIRK_R3D,
1373           .has_headphone_gain = false,
1374           .is_ae_series       = false,
1375           .out_set_info = {
1376                 /* Speakers. */
1377                 { .dac2port         = 0x24,
1378                   .has_hda_gpio     = false,
1379                   .mmio_gpio_count  = 1,
1380                   .mmio_gpio_pin    = { 1 },
1381                   .mmio_gpio_set    = { 1 },
1382                   .scp_cmds_count   = 0,
1383                   .has_chipio_write = false,
1384                 },
1385                 /* Headphones. */
1386                 { .dac2port         = 0x21,
1387                   .has_hda_gpio     = false,
1388                   .mmio_gpio_count  = 1,
1389                   .mmio_gpio_pin    = { 1 },
1390                   .mmio_gpio_set    = { 0 },
1391                   .scp_cmds_count   = 0,
1392                   .has_chipio_write = false,
1393                 } },
1394         },
1395         { .quirk_id = QUIRK_SBZ,
1396           .has_headphone_gain = false,
1397           .is_ae_series       = false,
1398           .out_set_info = {
1399                 /* Speakers. */
1400                 { .dac2port         = 0x18,
1401                   .has_hda_gpio     = false,
1402                   .mmio_gpio_count  = 3,
1403                   .mmio_gpio_pin    = { 7, 4, 1 },
1404                   .mmio_gpio_set    = { 0, 1, 1 },
1405                   .scp_cmds_count   = 0,
1406                   .has_chipio_write = false, },
1407                 /* Headphones. */
1408                 { .dac2port         = 0x12,
1409                   .has_hda_gpio     = false,
1410                   .mmio_gpio_count  = 3,
1411                   .mmio_gpio_pin    = { 7, 4, 1 },
1412                   .mmio_gpio_set    = { 1, 1, 0 },
1413                   .scp_cmds_count   = 0,
1414                   .has_chipio_write = false,
1415                 } },
1416         },
1417         { .quirk_id = QUIRK_ZXR,
1418           .has_headphone_gain = true,
1419           .is_ae_series       = false,
1420           .out_set_info = {
1421                 /* Speakers. */
1422                 { .dac2port         = 0x24,
1423                   .has_hda_gpio     = false,
1424                   .mmio_gpio_count  = 3,
1425                   .mmio_gpio_pin    = { 2, 3, 5 },
1426                   .mmio_gpio_set    = { 1, 1, 0 },
1427                   .scp_cmds_count   = 0,
1428                   .has_chipio_write = false,
1429                 },
1430                 /* Headphones. */
1431                 { .dac2port         = 0x21,
1432                   .has_hda_gpio     = false,
1433                   .mmio_gpio_count  = 3,
1434                   .mmio_gpio_pin    = { 2, 3, 5 },
1435                   .mmio_gpio_set    = { 0, 1, 1 },
1436                   .scp_cmds_count   = 0,
1437                   .has_chipio_write = false,
1438                 } },
1439         },
1440         { .quirk_id = QUIRK_AE5,
1441           .has_headphone_gain = true,
1442           .is_ae_series       = true,
1443           .out_set_info = {
1444                 /* Speakers. */
1445                 { .dac2port          = 0xa4,
1446                   .has_hda_gpio      = false,
1447                   .mmio_gpio_count   = 0,
1448                   .scp_cmds_count    = 2,
1449                   .scp_cmd_mid       = { 0x96, 0x96 },
1450                   .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1451                                          SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1452                   .scp_cmd_val       = { FLOAT_ZERO, FLOAT_ZERO },
1453                   .has_chipio_write  = true,
1454                   .chipio_write_addr = 0x0018b03c,
1455                   .chipio_write_data = 0x00000012
1456                 },
1457                 /* Headphones. */
1458                 { .dac2port          = 0xa1,
1459                   .has_hda_gpio      = false,
1460                   .mmio_gpio_count   = 0,
1461                   .scp_cmds_count    = 2,
1462                   .scp_cmd_mid       = { 0x96, 0x96 },
1463                   .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1464                                          SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1465                   .scp_cmd_val       = { FLOAT_ONE, FLOAT_ONE },
1466                   .has_chipio_write  = true,
1467                   .chipio_write_addr = 0x0018b03c,
1468                   .chipio_write_data = 0x00000012
1469                 } },
1470         },
1471         { .quirk_id = QUIRK_AE7,
1472           .has_headphone_gain = true,
1473           .is_ae_series       = true,
1474           .out_set_info = {
1475                 /* Speakers. */
1476                 { .dac2port          = 0x58,
1477                   .has_hda_gpio      = false,
1478                   .mmio_gpio_count   = 1,
1479                   .mmio_gpio_pin     = { 0 },
1480                   .mmio_gpio_set     = { 1 },
1481                   .scp_cmds_count    = 2,
1482                   .scp_cmd_mid       = { 0x96, 0x96 },
1483                   .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1484                                          SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1485                   .scp_cmd_val       = { FLOAT_ZERO, FLOAT_ZERO },
1486                   .has_chipio_write  = true,
1487                   .chipio_write_addr = 0x0018b03c,
1488                   .chipio_write_data = 0x00000000
1489                 },
1490                 /* Headphones. */
1491                 { .dac2port          = 0x58,
1492                   .has_hda_gpio      = false,
1493                   .mmio_gpio_count   = 1,
1494                   .mmio_gpio_pin     = { 0 },
1495                   .mmio_gpio_set     = { 1 },
1496                   .scp_cmds_count    = 2,
1497                   .scp_cmd_mid       = { 0x96, 0x96 },
1498                   .scp_cmd_req       = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1499                                          SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1500                   .scp_cmd_val       = { FLOAT_ONE, FLOAT_ONE },
1501                   .has_chipio_write  = true,
1502                   .chipio_write_addr = 0x0018b03c,
1503                   .chipio_write_data = 0x00000010
1504                 } },
1505         }
1506 };
1507
1508 /*
1509  * CA0132 codec access
1510  */
1511 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
1512                 unsigned int verb, unsigned int parm, unsigned int *res)
1513 {
1514         unsigned int response;
1515         response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1516         *res = response;
1517
1518         return ((response == -1) ? -1 : 0);
1519 }
1520
1521 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1522                 unsigned short converter_format, unsigned int *res)
1523 {
1524         return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1525                                 converter_format & 0xffff, res);
1526 }
1527
1528 static int codec_set_converter_stream_channel(struct hda_codec *codec,
1529                                 hda_nid_t nid, unsigned char stream,
1530                                 unsigned char channel, unsigned int *res)
1531 {
1532         unsigned char converter_stream_channel = 0;
1533
1534         converter_stream_channel = (stream << 4) | (channel & 0x0f);
1535         return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1536                                 converter_stream_channel, res);
1537 }
1538
1539 /* Chip access helper function */
1540 static int chipio_send(struct hda_codec *codec,
1541                        unsigned int reg,
1542                        unsigned int data)
1543 {
1544         unsigned int res;
1545         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1546
1547         /* send bits of data specified by reg */
1548         do {
1549                 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1550                                          reg, data);
1551                 if (res == VENDOR_STATUS_CHIPIO_OK)
1552                         return 0;
1553                 msleep(20);
1554         } while (time_before(jiffies, timeout));
1555
1556         return -EIO;
1557 }
1558
1559 /*
1560  * Write chip address through the vendor widget -- NOT protected by the Mutex!
1561  */
1562 static int chipio_write_address(struct hda_codec *codec,
1563                                 unsigned int chip_addx)
1564 {
1565         struct ca0132_spec *spec = codec->spec;
1566         int res;
1567
1568         if (spec->curr_chip_addx == chip_addx)
1569                         return 0;
1570
1571         /* send low 16 bits of the address */
1572         res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1573                           chip_addx & 0xffff);
1574
1575         if (res != -EIO) {
1576                 /* send high 16 bits of the address */
1577                 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1578                                   chip_addx >> 16);
1579         }
1580
1581         spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1582
1583         return res;
1584 }
1585
1586 /*
1587  * Write data through the vendor widget -- NOT protected by the Mutex!
1588  */
1589 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1590 {
1591         struct ca0132_spec *spec = codec->spec;
1592         int res;
1593
1594         /* send low 16 bits of the data */
1595         res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1596
1597         if (res != -EIO) {
1598                 /* send high 16 bits of the data */
1599                 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1600                                   data >> 16);
1601         }
1602
1603         /*If no error encountered, automatically increment the address
1604         as per chip behaviour*/
1605         spec->curr_chip_addx = (res != -EIO) ?
1606                                         (spec->curr_chip_addx + 4) : ~0U;
1607         return res;
1608 }
1609
1610 /*
1611  * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1612  */
1613 static int chipio_write_data_multiple(struct hda_codec *codec,
1614                                       const u32 *data,
1615                                       unsigned int count)
1616 {
1617         int status = 0;
1618
1619         if (data == NULL) {
1620                 codec_dbg(codec, "chipio_write_data null ptr\n");
1621                 return -EINVAL;
1622         }
1623
1624         while ((count-- != 0) && (status == 0))
1625                 status = chipio_write_data(codec, *data++);
1626
1627         return status;
1628 }
1629
1630
1631 /*
1632  * Read data through the vendor widget -- NOT protected by the Mutex!
1633  */
1634 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1635 {
1636         struct ca0132_spec *spec = codec->spec;
1637         int res;
1638
1639         /* post read */
1640         res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1641
1642         if (res != -EIO) {
1643                 /* read status */
1644                 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1645         }
1646
1647         if (res != -EIO) {
1648                 /* read data */
1649                 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1650                                            VENDOR_CHIPIO_HIC_READ_DATA,
1651                                            0);
1652         }
1653
1654         /*If no error encountered, automatically increment the address
1655         as per chip behaviour*/
1656         spec->curr_chip_addx = (res != -EIO) ?
1657                                         (spec->curr_chip_addx + 4) : ~0U;
1658         return res;
1659 }
1660
1661 /*
1662  * Write given value to the given address through the chip I/O widget.
1663  * protected by the Mutex
1664  */
1665 static int chipio_write(struct hda_codec *codec,
1666                 unsigned int chip_addx, const unsigned int data)
1667 {
1668         struct ca0132_spec *spec = codec->spec;
1669         int err;
1670
1671         mutex_lock(&spec->chipio_mutex);
1672
1673         /* write the address, and if successful proceed to write data */
1674         err = chipio_write_address(codec, chip_addx);
1675         if (err < 0)
1676                 goto exit;
1677
1678         err = chipio_write_data(codec, data);
1679         if (err < 0)
1680                 goto exit;
1681
1682 exit:
1683         mutex_unlock(&spec->chipio_mutex);
1684         return err;
1685 }
1686
1687 /*
1688  * Write given value to the given address through the chip I/O widget.
1689  * not protected by the Mutex
1690  */
1691 static int chipio_write_no_mutex(struct hda_codec *codec,
1692                 unsigned int chip_addx, const unsigned int data)
1693 {
1694         int err;
1695
1696
1697         /* write the address, and if successful proceed to write data */
1698         err = chipio_write_address(codec, chip_addx);
1699         if (err < 0)
1700                 goto exit;
1701
1702         err = chipio_write_data(codec, data);
1703         if (err < 0)
1704                 goto exit;
1705
1706 exit:
1707         return err;
1708 }
1709
1710 /*
1711  * Write multiple values to the given address through the chip I/O widget.
1712  * protected by the Mutex
1713  */
1714 static int chipio_write_multiple(struct hda_codec *codec,
1715                                  u32 chip_addx,
1716                                  const u32 *data,
1717                                  unsigned int count)
1718 {
1719         struct ca0132_spec *spec = codec->spec;
1720         int status;
1721
1722         mutex_lock(&spec->chipio_mutex);
1723         status = chipio_write_address(codec, chip_addx);
1724         if (status < 0)
1725                 goto error;
1726
1727         status = chipio_write_data_multiple(codec, data, count);
1728 error:
1729         mutex_unlock(&spec->chipio_mutex);
1730
1731         return status;
1732 }
1733
1734 /*
1735  * Read the given address through the chip I/O widget
1736  * protected by the Mutex
1737  */
1738 static int chipio_read(struct hda_codec *codec,
1739                 unsigned int chip_addx, unsigned int *data)
1740 {
1741         struct ca0132_spec *spec = codec->spec;
1742         int err;
1743
1744         mutex_lock(&spec->chipio_mutex);
1745
1746         /* write the address, and if successful proceed to write data */
1747         err = chipio_write_address(codec, chip_addx);
1748         if (err < 0)
1749                 goto exit;
1750
1751         err = chipio_read_data(codec, data);
1752         if (err < 0)
1753                 goto exit;
1754
1755 exit:
1756         mutex_unlock(&spec->chipio_mutex);
1757         return err;
1758 }
1759
1760 /*
1761  * Set chip control flags through the chip I/O widget.
1762  */
1763 static void chipio_set_control_flag(struct hda_codec *codec,
1764                                     enum control_flag_id flag_id,
1765                                     bool flag_state)
1766 {
1767         unsigned int val;
1768         unsigned int flag_bit;
1769
1770         flag_bit = (flag_state ? 1 : 0);
1771         val = (flag_bit << 7) | (flag_id);
1772         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1773                             VENDOR_CHIPIO_FLAG_SET, val);
1774 }
1775
1776 /*
1777  * Set chip parameters through the chip I/O widget.
1778  */
1779 static void chipio_set_control_param(struct hda_codec *codec,
1780                 enum control_param_id param_id, int param_val)
1781 {
1782         struct ca0132_spec *spec = codec->spec;
1783         int val;
1784
1785         if ((param_id < 32) && (param_val < 8)) {
1786                 val = (param_val << 5) | (param_id);
1787                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1788                                     VENDOR_CHIPIO_PARAM_SET, val);
1789         } else {
1790                 mutex_lock(&spec->chipio_mutex);
1791                 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1792                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1793                                             VENDOR_CHIPIO_PARAM_EX_ID_SET,
1794                                             param_id);
1795                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1796                                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1797                                             param_val);
1798                 }
1799                 mutex_unlock(&spec->chipio_mutex);
1800         }
1801 }
1802
1803 /*
1804  * Set chip parameters through the chip I/O widget. NO MUTEX.
1805  */
1806 static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1807                 enum control_param_id param_id, int param_val)
1808 {
1809         int val;
1810
1811         if ((param_id < 32) && (param_val < 8)) {
1812                 val = (param_val << 5) | (param_id);
1813                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1814                                     VENDOR_CHIPIO_PARAM_SET, val);
1815         } else {
1816                 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1817                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1818                                             VENDOR_CHIPIO_PARAM_EX_ID_SET,
1819                                             param_id);
1820                         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1821                                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1822                                             param_val);
1823                 }
1824         }
1825 }
1826 /*
1827  * Connect stream to a source point, and then connect
1828  * that source point to a destination point.
1829  */
1830 static void chipio_set_stream_source_dest(struct hda_codec *codec,
1831                                 int streamid, int source_point, int dest_point)
1832 {
1833         chipio_set_control_param_no_mutex(codec,
1834                         CONTROL_PARAM_STREAM_ID, streamid);
1835         chipio_set_control_param_no_mutex(codec,
1836                         CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1837         chipio_set_control_param_no_mutex(codec,
1838                         CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1839 }
1840
1841 /*
1842  * Set number of channels in the selected stream.
1843  */
1844 static void chipio_set_stream_channels(struct hda_codec *codec,
1845                                 int streamid, unsigned int channels)
1846 {
1847         chipio_set_control_param_no_mutex(codec,
1848                         CONTROL_PARAM_STREAM_ID, streamid);
1849         chipio_set_control_param_no_mutex(codec,
1850                         CONTROL_PARAM_STREAMS_CHANNELS, channels);
1851 }
1852
1853 /*
1854  * Enable/Disable audio stream.
1855  */
1856 static void chipio_set_stream_control(struct hda_codec *codec,
1857                                 int streamid, int enable)
1858 {
1859         chipio_set_control_param_no_mutex(codec,
1860                         CONTROL_PARAM_STREAM_ID, streamid);
1861         chipio_set_control_param_no_mutex(codec,
1862                         CONTROL_PARAM_STREAM_CONTROL, enable);
1863 }
1864
1865 /*
1866  * Get ChipIO audio stream's status.
1867  */
1868 static void chipio_get_stream_control(struct hda_codec *codec,
1869                                 int streamid, unsigned int *enable)
1870 {
1871         chipio_set_control_param_no_mutex(codec,
1872                         CONTROL_PARAM_STREAM_ID, streamid);
1873         *enable = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1874                            VENDOR_CHIPIO_PARAM_GET,
1875                            CONTROL_PARAM_STREAM_CONTROL);
1876 }
1877
1878 /*
1879  * Set sampling rate of the connection point. NO MUTEX.
1880  */
1881 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1882                                 int connid, enum ca0132_sample_rate rate)
1883 {
1884         chipio_set_control_param_no_mutex(codec,
1885                         CONTROL_PARAM_CONN_POINT_ID, connid);
1886         chipio_set_control_param_no_mutex(codec,
1887                         CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1888 }
1889
1890 /*
1891  * Set sampling rate of the connection point.
1892  */
1893 static void chipio_set_conn_rate(struct hda_codec *codec,
1894                                 int connid, enum ca0132_sample_rate rate)
1895 {
1896         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1897         chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1898                                  rate);
1899 }
1900
1901 /*
1902  * Writes to the 8051's internal address space directly instead of indirectly,
1903  * giving access to the special function registers located at addresses
1904  * 0x80-0xFF.
1905  */
1906 static void chipio_8051_write_direct(struct hda_codec *codec,
1907                 unsigned int addr, unsigned int data)
1908 {
1909         unsigned int verb;
1910
1911         verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
1912         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1913 }
1914
1915 /*
1916  * Writes to the 8051's exram, which has 16-bits of address space.
1917  * Data at addresses 0x2000-0x7fff is mirrored to 0x8000-0xdfff.
1918  * Data at 0x8000-0xdfff can also be used as program memory for the 8051 by
1919  * setting the pmem bank selection SFR.
1920  * 0xe000-0xffff is always mapped as program memory, with only 0xf000-0xffff
1921  * being writable.
1922  */
1923 static void chipio_8051_set_address(struct hda_codec *codec, unsigned int addr)
1924 {
1925         unsigned int tmp;
1926
1927         /* Lower 8-bits. */
1928         tmp = addr & 0xff;
1929         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1930                             VENDOR_CHIPIO_8051_ADDRESS_LOW, tmp);
1931
1932         /* Upper 8-bits. */
1933         tmp = (addr >> 8) & 0xff;
1934         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1935                             VENDOR_CHIPIO_8051_ADDRESS_HIGH, tmp);
1936 }
1937
1938 static void chipio_8051_set_data(struct hda_codec *codec, unsigned int data)
1939 {
1940         /* 8-bits of data. */
1941         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1942                             VENDOR_CHIPIO_8051_DATA_WRITE, data & 0xff);
1943 }
1944
1945 static unsigned int chipio_8051_get_data(struct hda_codec *codec)
1946 {
1947         return snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1948                                    VENDOR_CHIPIO_8051_DATA_READ, 0);
1949 }
1950
1951 /* PLL_PMU writes share the lower address register of the 8051 exram writes. */
1952 static void chipio_8051_set_data_pll(struct hda_codec *codec, unsigned int data)
1953 {
1954         /* 8-bits of data. */
1955         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1956                             VENDOR_CHIPIO_PLL_PMU_WRITE, data & 0xff);
1957 }
1958
1959 static void chipio_8051_write_exram(struct hda_codec *codec,
1960                 unsigned int addr, unsigned int data)
1961 {
1962         struct ca0132_spec *spec = codec->spec;
1963
1964         mutex_lock(&spec->chipio_mutex);
1965
1966         chipio_8051_set_address(codec, addr);
1967         chipio_8051_set_data(codec, data);
1968
1969         mutex_unlock(&spec->chipio_mutex);
1970 }
1971
1972 static void chipio_8051_write_exram_no_mutex(struct hda_codec *codec,
1973                 unsigned int addr, unsigned int data)
1974 {
1975         chipio_8051_set_address(codec, addr);
1976         chipio_8051_set_data(codec, data);
1977 }
1978
1979 /* Readback data from the 8051's exram. No mutex. */
1980 static void chipio_8051_read_exram(struct hda_codec *codec,
1981                 unsigned int addr, unsigned int *data)
1982 {
1983         chipio_8051_set_address(codec, addr);
1984         *data = chipio_8051_get_data(codec);
1985 }
1986
1987 static void chipio_8051_write_pll_pmu(struct hda_codec *codec,
1988                 unsigned int addr, unsigned int data)
1989 {
1990         struct ca0132_spec *spec = codec->spec;
1991
1992         mutex_lock(&spec->chipio_mutex);
1993
1994         chipio_8051_set_address(codec, addr & 0xff);
1995         chipio_8051_set_data_pll(codec, data);
1996
1997         mutex_unlock(&spec->chipio_mutex);
1998 }
1999
2000 static void chipio_8051_write_pll_pmu_no_mutex(struct hda_codec *codec,
2001                 unsigned int addr, unsigned int data)
2002 {
2003         chipio_8051_set_address(codec, addr & 0xff);
2004         chipio_8051_set_data_pll(codec, data);
2005 }
2006
2007 /*
2008  * Enable clocks.
2009  */
2010 static void chipio_enable_clocks(struct hda_codec *codec)
2011 {
2012         struct ca0132_spec *spec = codec->spec;
2013
2014         mutex_lock(&spec->chipio_mutex);
2015
2016         chipio_8051_write_pll_pmu_no_mutex(codec, 0x00, 0xff);
2017         chipio_8051_write_pll_pmu_no_mutex(codec, 0x05, 0x0b);
2018         chipio_8051_write_pll_pmu_no_mutex(codec, 0x06, 0xff);
2019
2020         mutex_unlock(&spec->chipio_mutex);
2021 }
2022
2023 /*
2024  * CA0132 DSP IO stuffs
2025  */
2026 static int dspio_send(struct hda_codec *codec, unsigned int reg,
2027                       unsigned int data)
2028 {
2029         int res;
2030         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2031
2032         /* send bits of data specified by reg to dsp */
2033         do {
2034                 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
2035                 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
2036                         return res;
2037                 msleep(20);
2038         } while (time_before(jiffies, timeout));
2039
2040         return -EIO;
2041 }
2042
2043 /*
2044  * Wait for DSP to be ready for commands
2045  */
2046 static void dspio_write_wait(struct hda_codec *codec)
2047 {
2048         int status;
2049         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2050
2051         do {
2052                 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2053                                                 VENDOR_DSPIO_STATUS, 0);
2054                 if ((status == VENDOR_STATUS_DSPIO_OK) ||
2055                     (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
2056                         break;
2057                 msleep(1);
2058         } while (time_before(jiffies, timeout));
2059 }
2060
2061 /*
2062  * Write SCP data to DSP
2063  */
2064 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
2065 {
2066         struct ca0132_spec *spec = codec->spec;
2067         int status;
2068
2069         dspio_write_wait(codec);
2070
2071         mutex_lock(&spec->chipio_mutex);
2072         status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
2073                             scp_data & 0xffff);
2074         if (status < 0)
2075                 goto error;
2076
2077         status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
2078                                     scp_data >> 16);
2079         if (status < 0)
2080                 goto error;
2081
2082         /* OK, now check if the write itself has executed*/
2083         status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2084                                     VENDOR_DSPIO_STATUS, 0);
2085 error:
2086         mutex_unlock(&spec->chipio_mutex);
2087
2088         return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
2089                         -EIO : 0;
2090 }
2091
2092 /*
2093  * Write multiple SCP data to DSP
2094  */
2095 static int dspio_write_multiple(struct hda_codec *codec,
2096                                 unsigned int *buffer, unsigned int size)
2097 {
2098         int status = 0;
2099         unsigned int count;
2100
2101         if (buffer == NULL)
2102                 return -EINVAL;
2103
2104         count = 0;
2105         while (count < size) {
2106                 status = dspio_write(codec, *buffer++);
2107                 if (status != 0)
2108                         break;
2109                 count++;
2110         }
2111
2112         return status;
2113 }
2114
2115 static int dspio_read(struct hda_codec *codec, unsigned int *data)
2116 {
2117         int status;
2118
2119         status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
2120         if (status == -EIO)
2121                 return status;
2122
2123         status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
2124         if (status == -EIO ||
2125             status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
2126                 return -EIO;
2127
2128         *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2129                                    VENDOR_DSPIO_SCP_READ_DATA, 0);
2130
2131         return 0;
2132 }
2133
2134 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
2135                                unsigned int *buf_size, unsigned int size_count)
2136 {
2137         int status = 0;
2138         unsigned int size = *buf_size;
2139         unsigned int count;
2140         unsigned int skip_count;
2141         unsigned int dummy;
2142
2143         if (buffer == NULL)
2144                 return -1;
2145
2146         count = 0;
2147         while (count < size && count < size_count) {
2148                 status = dspio_read(codec, buffer++);
2149                 if (status != 0)
2150                         break;
2151                 count++;
2152         }
2153
2154         skip_count = count;
2155         if (status == 0) {
2156                 while (skip_count < size) {
2157                         status = dspio_read(codec, &dummy);
2158                         if (status != 0)
2159                                 break;
2160                         skip_count++;
2161                 }
2162         }
2163         *buf_size = count;
2164
2165         return status;
2166 }
2167
2168 /*
2169  * Construct the SCP header using corresponding fields
2170  */
2171 static inline unsigned int
2172 make_scp_header(unsigned int target_id, unsigned int source_id,
2173                 unsigned int get_flag, unsigned int req,
2174                 unsigned int device_flag, unsigned int resp_flag,
2175                 unsigned int error_flag, unsigned int data_size)
2176 {
2177         unsigned int header = 0;
2178
2179         header = (data_size & 0x1f) << 27;
2180         header |= (error_flag & 0x01) << 26;
2181         header |= (resp_flag & 0x01) << 25;
2182         header |= (device_flag & 0x01) << 24;
2183         header |= (req & 0x7f) << 17;
2184         header |= (get_flag & 0x01) << 16;
2185         header |= (source_id & 0xff) << 8;
2186         header |= target_id & 0xff;
2187
2188         return header;
2189 }
2190
2191 /*
2192  * Extract corresponding fields from SCP header
2193  */
2194 static inline void
2195 extract_scp_header(unsigned int header,
2196                    unsigned int *target_id, unsigned int *source_id,
2197                    unsigned int *get_flag, unsigned int *req,
2198                    unsigned int *device_flag, unsigned int *resp_flag,
2199                    unsigned int *error_flag, unsigned int *data_size)
2200 {
2201         if (data_size)
2202                 *data_size = (header >> 27) & 0x1f;
2203         if (error_flag)
2204                 *error_flag = (header >> 26) & 0x01;
2205         if (resp_flag)
2206                 *resp_flag = (header >> 25) & 0x01;
2207         if (device_flag)
2208                 *device_flag = (header >> 24) & 0x01;
2209         if (req)
2210                 *req = (header >> 17) & 0x7f;
2211         if (get_flag)
2212                 *get_flag = (header >> 16) & 0x01;
2213         if (source_id)
2214                 *source_id = (header >> 8) & 0xff;
2215         if (target_id)
2216                 *target_id = header & 0xff;
2217 }
2218
2219 #define SCP_MAX_DATA_WORDS  (16)
2220
2221 /* Structure to contain any SCP message */
2222 struct scp_msg {
2223         unsigned int hdr;
2224         unsigned int data[SCP_MAX_DATA_WORDS];
2225 };
2226
2227 static void dspio_clear_response_queue(struct hda_codec *codec)
2228 {
2229         unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2230         unsigned int dummy = 0;
2231         int status;
2232
2233         /* clear all from the response queue */
2234         do {
2235                 status = dspio_read(codec, &dummy);
2236         } while (status == 0 && time_before(jiffies, timeout));
2237 }
2238
2239 static int dspio_get_response_data(struct hda_codec *codec)
2240 {
2241         struct ca0132_spec *spec = codec->spec;
2242         unsigned int data = 0;
2243         unsigned int count;
2244
2245         if (dspio_read(codec, &data) < 0)
2246                 return -EIO;
2247
2248         if ((data & 0x00ffffff) == spec->wait_scp_header) {
2249                 spec->scp_resp_header = data;
2250                 spec->scp_resp_count = data >> 27;
2251                 count = spec->wait_num_data;
2252                 dspio_read_multiple(codec, spec->scp_resp_data,
2253                                     &spec->scp_resp_count, count);
2254                 return 0;
2255         }
2256
2257         return -EIO;
2258 }
2259
2260 /*
2261  * Send SCP message to DSP
2262  */
2263 static int dspio_send_scp_message(struct hda_codec *codec,
2264                                   unsigned char *send_buf,
2265                                   unsigned int send_buf_size,
2266                                   unsigned char *return_buf,
2267                                   unsigned int return_buf_size,
2268                                   unsigned int *bytes_returned)
2269 {
2270         struct ca0132_spec *spec = codec->spec;
2271         int status;
2272         unsigned int scp_send_size = 0;
2273         unsigned int total_size;
2274         bool waiting_for_resp = false;
2275         unsigned int header;
2276         struct scp_msg *ret_msg;
2277         unsigned int resp_src_id, resp_target_id;
2278         unsigned int data_size, src_id, target_id, get_flag, device_flag;
2279
2280         if (bytes_returned)
2281                 *bytes_returned = 0;
2282
2283         /* get scp header from buffer */
2284         header = *((unsigned int *)send_buf);
2285         extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
2286                            &device_flag, NULL, NULL, &data_size);
2287         scp_send_size = data_size + 1;
2288         total_size = (scp_send_size * 4);
2289
2290         if (send_buf_size < total_size)
2291                 return -EINVAL;
2292
2293         if (get_flag || device_flag) {
2294                 if (!return_buf || return_buf_size < 4 || !bytes_returned)
2295                         return -EINVAL;
2296
2297                 spec->wait_scp_header = *((unsigned int *)send_buf);
2298
2299                 /* swap source id with target id */
2300                 resp_target_id = src_id;
2301                 resp_src_id = target_id;
2302                 spec->wait_scp_header &= 0xffff0000;
2303                 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
2304                 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
2305                 spec->wait_scp = 1;
2306                 waiting_for_resp = true;
2307         }
2308
2309         status = dspio_write_multiple(codec, (unsigned int *)send_buf,
2310                                       scp_send_size);
2311         if (status < 0) {
2312                 spec->wait_scp = 0;
2313                 return status;
2314         }
2315
2316         if (waiting_for_resp) {
2317                 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2318                 memset(return_buf, 0, return_buf_size);
2319                 do {
2320                         msleep(20);
2321                 } while (spec->wait_scp && time_before(jiffies, timeout));
2322                 waiting_for_resp = false;
2323                 if (!spec->wait_scp) {
2324                         ret_msg = (struct scp_msg *)return_buf;
2325                         memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
2326                         memcpy(&ret_msg->data, spec->scp_resp_data,
2327                                spec->wait_num_data);
2328                         *bytes_returned = (spec->scp_resp_count + 1) * 4;
2329                         status = 0;
2330                 } else {
2331                         status = -EIO;
2332                 }
2333                 spec->wait_scp = 0;
2334         }
2335
2336         return status;
2337 }
2338
2339 /**
2340  * dspio_scp - Prepare and send the SCP message to DSP
2341  * @codec: the HDA codec
2342  * @mod_id: ID of the DSP module to send the command
2343  * @src_id: ID of the source
2344  * @req: ID of request to send to the DSP module
2345  * @dir: SET or GET
2346  * @data: pointer to the data to send with the request, request specific
2347  * @len: length of the data, in bytes
2348  * @reply: point to the buffer to hold data returned for a reply
2349  * @reply_len: length of the reply buffer returned from GET
2350  *
2351  * Returns zero or a negative error code.
2352  */
2353 static int dspio_scp(struct hda_codec *codec,
2354                 int mod_id, int src_id, int req, int dir, const void *data,
2355                 unsigned int len, void *reply, unsigned int *reply_len)
2356 {
2357         int status = 0;
2358         struct scp_msg scp_send, scp_reply;
2359         unsigned int ret_bytes, send_size, ret_size;
2360         unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
2361         unsigned int reply_data_size;
2362
2363         memset(&scp_send, 0, sizeof(scp_send));
2364         memset(&scp_reply, 0, sizeof(scp_reply));
2365
2366         if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
2367                 return -EINVAL;
2368
2369         if (dir == SCP_GET && reply == NULL) {
2370                 codec_dbg(codec, "dspio_scp get but has no buffer\n");
2371                 return -EINVAL;
2372         }
2373
2374         if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
2375                 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
2376                 return -EINVAL;
2377         }
2378
2379         scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
2380                                        0, 0, 0, len/sizeof(unsigned int));
2381         if (data != NULL && len > 0) {
2382                 len = min((unsigned int)(sizeof(scp_send.data)), len);
2383                 memcpy(scp_send.data, data, len);
2384         }
2385
2386         ret_bytes = 0;
2387         send_size = sizeof(unsigned int) + len;
2388         status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
2389                                         send_size, (unsigned char *)&scp_reply,
2390                                         sizeof(scp_reply), &ret_bytes);
2391
2392         if (status < 0) {
2393                 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
2394                 return status;
2395         }
2396
2397         /* extract send and reply headers members */
2398         extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
2399                            NULL, NULL, NULL, NULL, NULL);
2400         extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
2401                            &reply_resp_flag, &reply_error_flag,
2402                            &reply_data_size);
2403
2404         if (!send_get_flag)
2405                 return 0;
2406
2407         if (reply_resp_flag && !reply_error_flag) {
2408                 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
2409                                         / sizeof(unsigned int);
2410
2411                 if (*reply_len < ret_size*sizeof(unsigned int)) {
2412                         codec_dbg(codec, "reply too long for buf\n");
2413                         return -EINVAL;
2414                 } else if (ret_size != reply_data_size) {
2415                         codec_dbg(codec, "RetLen and HdrLen .NE.\n");
2416                         return -EINVAL;
2417                 } else if (!reply) {
2418                         codec_dbg(codec, "NULL reply\n");
2419                         return -EINVAL;
2420                 } else {
2421                         *reply_len = ret_size*sizeof(unsigned int);
2422                         memcpy(reply, scp_reply.data, *reply_len);
2423                 }
2424         } else {
2425                 codec_dbg(codec, "reply ill-formed or errflag set\n");
2426                 return -EIO;
2427         }
2428
2429         return status;
2430 }
2431
2432 /*
2433  * Set DSP parameters
2434  */
2435 static int dspio_set_param(struct hda_codec *codec, int mod_id,
2436                         int src_id, int req, const void *data, unsigned int len)
2437 {
2438         return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
2439                         NULL);
2440 }
2441
2442 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
2443                         int req, const unsigned int data)
2444 {
2445         return dspio_set_param(codec, mod_id, 0x20, req, &data,
2446                         sizeof(unsigned int));
2447 }
2448
2449 /*
2450  * Allocate a DSP DMA channel via an SCP message
2451  */
2452 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
2453 {
2454         int status = 0;
2455         unsigned int size = sizeof(dma_chan);
2456
2457         codec_dbg(codec, "     dspio_alloc_dma_chan() -- begin\n");
2458         status = dspio_scp(codec, MASTERCONTROL, 0x20,
2459                         MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
2460                         dma_chan, &size);
2461
2462         if (status < 0) {
2463                 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
2464                 return status;
2465         }
2466
2467         if ((*dma_chan + 1) == 0) {
2468                 codec_dbg(codec, "no free dma channels to allocate\n");
2469                 return -EBUSY;
2470         }
2471
2472         codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
2473         codec_dbg(codec, "     dspio_alloc_dma_chan() -- complete\n");
2474
2475         return status;
2476 }
2477
2478 /*
2479  * Free a DSP DMA via an SCP message
2480  */
2481 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
2482 {
2483         int status = 0;
2484         unsigned int dummy = 0;
2485
2486         codec_dbg(codec, "     dspio_free_dma_chan() -- begin\n");
2487         codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
2488
2489         status = dspio_scp(codec, MASTERCONTROL, 0x20,
2490                         MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
2491                         sizeof(dma_chan), NULL, &dummy);
2492
2493         if (status < 0) {
2494                 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
2495                 return status;
2496         }
2497
2498         codec_dbg(codec, "     dspio_free_dma_chan() -- complete\n");
2499
2500         return status;
2501 }
2502
2503 /*
2504  * (Re)start the DSP
2505  */
2506 static int dsp_set_run_state(struct hda_codec *codec)
2507 {
2508         unsigned int dbg_ctrl_reg;
2509         unsigned int halt_state;
2510         int err;
2511
2512         err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2513         if (err < 0)
2514                 return err;
2515
2516         halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
2517                       DSP_DBGCNTL_STATE_LOBIT;
2518
2519         if (halt_state != 0) {
2520                 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
2521                                   DSP_DBGCNTL_SS_MASK);
2522                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2523                                    dbg_ctrl_reg);
2524                 if (err < 0)
2525                         return err;
2526
2527                 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
2528                                 DSP_DBGCNTL_EXEC_MASK;
2529                 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2530                                    dbg_ctrl_reg);
2531                 if (err < 0)
2532                         return err;
2533         }
2534
2535         return 0;
2536 }
2537
2538 /*
2539  * Reset the DSP
2540  */
2541 static int dsp_reset(struct hda_codec *codec)
2542 {
2543         unsigned int res;
2544         int retry = 20;
2545
2546         codec_dbg(codec, "dsp_reset\n");
2547         do {
2548                 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2549                 retry--;
2550         } while (res == -EIO && retry);
2551
2552         if (!retry) {
2553                 codec_dbg(codec, "dsp_reset timeout\n");
2554                 return -EIO;
2555         }
2556
2557         return 0;
2558 }
2559
2560 /*
2561  * Convert chip address to DSP address
2562  */
2563 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2564                                         bool *code, bool *yram)
2565 {
2566         *code = *yram = false;
2567
2568         if (UC_RANGE(chip_addx, 1)) {
2569                 *code = true;
2570                 return UC_OFF(chip_addx);
2571         } else if (X_RANGE_ALL(chip_addx, 1)) {
2572                 return X_OFF(chip_addx);
2573         } else if (Y_RANGE_ALL(chip_addx, 1)) {
2574                 *yram = true;
2575                 return Y_OFF(chip_addx);
2576         }
2577
2578         return INVALID_CHIP_ADDRESS;
2579 }
2580
2581 /*
2582  * Check if the DSP DMA is active
2583  */
2584 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2585 {
2586         unsigned int dma_chnlstart_reg;
2587
2588         chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2589
2590         return ((dma_chnlstart_reg & (1 <<
2591                         (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2592 }
2593
2594 static int dsp_dma_setup_common(struct hda_codec *codec,
2595                                 unsigned int chip_addx,
2596                                 unsigned int dma_chan,
2597                                 unsigned int port_map_mask,
2598                                 bool ovly)
2599 {
2600         int status = 0;
2601         unsigned int chnl_prop;
2602         unsigned int dsp_addx;
2603         unsigned int active;
2604         bool code, yram;
2605
2606         codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
2607
2608         if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
2609                 codec_dbg(codec, "dma chan num invalid\n");
2610                 return -EINVAL;
2611         }
2612
2613         if (dsp_is_dma_active(codec, dma_chan)) {
2614                 codec_dbg(codec, "dma already active\n");
2615                 return -EBUSY;
2616         }
2617
2618         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2619
2620         if (dsp_addx == INVALID_CHIP_ADDRESS) {
2621                 codec_dbg(codec, "invalid chip addr\n");
2622                 return -ENXIO;
2623         }
2624
2625         chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2626         active = 0;
2627
2628         codec_dbg(codec, "   dsp_dma_setup_common()    start reg pgm\n");
2629
2630         if (ovly) {
2631                 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2632                                      &chnl_prop);
2633
2634                 if (status < 0) {
2635                         codec_dbg(codec, "read CHNLPROP Reg fail\n");
2636                         return status;
2637                 }
2638                 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
2639         }
2640
2641         if (!code)
2642                 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2643         else
2644                 chnl_prop |=  (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2645
2646         chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2647
2648         status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2649         if (status < 0) {
2650                 codec_dbg(codec, "write CHNLPROP Reg fail\n");
2651                 return status;
2652         }
2653         codec_dbg(codec, "   dsp_dma_setup_common()    Write CHNLPROP\n");
2654
2655         if (ovly) {
2656                 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2657                                      &active);
2658
2659                 if (status < 0) {
2660                         codec_dbg(codec, "read ACTIVE Reg fail\n");
2661                         return status;
2662                 }
2663                 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
2664         }
2665
2666         active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2667                 DSPDMAC_ACTIVE_AAR_MASK;
2668
2669         status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2670         if (status < 0) {
2671                 codec_dbg(codec, "write ACTIVE Reg fail\n");
2672                 return status;
2673         }
2674
2675         codec_dbg(codec, "   dsp_dma_setup_common()    Write ACTIVE\n");
2676
2677         status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2678                               port_map_mask);
2679         if (status < 0) {
2680                 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
2681                 return status;
2682         }
2683         codec_dbg(codec, "   dsp_dma_setup_common()    Write AUDCHSEL\n");
2684
2685         status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2686                         DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2687         if (status < 0) {
2688                 codec_dbg(codec, "write IRQCNT Reg fail\n");
2689                 return status;
2690         }
2691         codec_dbg(codec, "   dsp_dma_setup_common()    Write IRQCNT\n");
2692
2693         codec_dbg(codec,
2694                    "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2695                    "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2696                    chip_addx, dsp_addx, dma_chan,
2697                    port_map_mask, chnl_prop, active);
2698
2699         codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
2700
2701         return 0;
2702 }
2703
2704 /*
2705  * Setup the DSP DMA per-transfer-specific registers
2706  */
2707 static int dsp_dma_setup(struct hda_codec *codec,
2708                         unsigned int chip_addx,
2709                         unsigned int count,
2710                         unsigned int dma_chan)
2711 {
2712         int status = 0;
2713         bool code, yram;
2714         unsigned int dsp_addx;
2715         unsigned int addr_field;
2716         unsigned int incr_field;
2717         unsigned int base_cnt;
2718         unsigned int cur_cnt;
2719         unsigned int dma_cfg = 0;
2720         unsigned int adr_ofs = 0;
2721         unsigned int xfr_cnt = 0;
2722         const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2723                                                 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2724
2725         codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
2726
2727         if (count > max_dma_count) {
2728                 codec_dbg(codec, "count too big\n");
2729                 return -EINVAL;
2730         }
2731
2732         dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2733         if (dsp_addx == INVALID_CHIP_ADDRESS) {
2734                 codec_dbg(codec, "invalid chip addr\n");
2735                 return -ENXIO;
2736         }
2737
2738         codec_dbg(codec, "   dsp_dma_setup()    start reg pgm\n");
2739
2740         addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2741         incr_field   = 0;
2742
2743         if (!code) {
2744                 addr_field <<= 1;
2745                 if (yram)
2746                         addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2747
2748                 incr_field  = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2749         }
2750
2751         dma_cfg = addr_field + incr_field;
2752         status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2753                                 dma_cfg);
2754         if (status < 0) {
2755                 codec_dbg(codec, "write DMACFG Reg fail\n");
2756                 return status;
2757         }
2758         codec_dbg(codec, "   dsp_dma_setup()    Write DMACFG\n");
2759
2760         adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2761                                                         (code ? 0 : 1));
2762
2763         status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2764                                 adr_ofs);
2765         if (status < 0) {
2766                 codec_dbg(codec, "write DSPADROFS Reg fail\n");
2767                 return status;
2768         }
2769         codec_dbg(codec, "   dsp_dma_setup()    Write DSPADROFS\n");
2770
2771         base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2772
2773         cur_cnt  = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2774
2775         xfr_cnt = base_cnt | cur_cnt;
2776
2777         status = chipio_write(codec,
2778                                 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2779         if (status < 0) {
2780                 codec_dbg(codec, "write XFRCNT Reg fail\n");
2781                 return status;
2782         }
2783         codec_dbg(codec, "   dsp_dma_setup()    Write XFRCNT\n");
2784
2785         codec_dbg(codec,
2786                    "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2787                    "ADROFS=0x%x, XFRCNT=0x%x\n",
2788                    chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2789
2790         codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
2791
2792         return 0;
2793 }
2794
2795 /*
2796  * Start the DSP DMA
2797  */
2798 static int dsp_dma_start(struct hda_codec *codec,
2799                          unsigned int dma_chan, bool ovly)
2800 {
2801         unsigned int reg = 0;
2802         int status = 0;
2803
2804         codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
2805
2806         if (ovly) {
2807                 status = chipio_read(codec,
2808                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2809
2810                 if (status < 0) {
2811                         codec_dbg(codec, "read CHNLSTART reg fail\n");
2812                         return status;
2813                 }
2814                 codec_dbg(codec, "-- dsp_dma_start()    Read CHNLSTART\n");
2815
2816                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2817                                 DSPDMAC_CHNLSTART_DIS_MASK);
2818         }
2819
2820         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2821                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2822         if (status < 0) {
2823                 codec_dbg(codec, "write CHNLSTART reg fail\n");
2824                 return status;
2825         }
2826         codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
2827
2828         return status;
2829 }
2830
2831 /*
2832  * Stop the DSP DMA
2833  */
2834 static int dsp_dma_stop(struct hda_codec *codec,
2835                         unsigned int dma_chan, bool ovly)
2836 {
2837         unsigned int reg = 0;
2838         int status = 0;
2839
2840         codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
2841
2842         if (ovly) {
2843                 status = chipio_read(codec,
2844                                      DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2845
2846                 if (status < 0) {
2847                         codec_dbg(codec, "read CHNLSTART reg fail\n");
2848                         return status;
2849                 }
2850                 codec_dbg(codec, "-- dsp_dma_stop()    Read CHNLSTART\n");
2851                 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2852                                 DSPDMAC_CHNLSTART_DIS_MASK);
2853         }
2854
2855         status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2856                         reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2857         if (status < 0) {
2858                 codec_dbg(codec, "write CHNLSTART reg fail\n");
2859                 return status;
2860         }
2861         codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
2862
2863         return status;
2864 }
2865
2866 /**
2867  * dsp_allocate_router_ports - Allocate router ports
2868  *
2869  * @codec: the HDA codec
2870  * @num_chans: number of channels in the stream
2871  * @ports_per_channel: number of ports per channel
2872  * @start_device: start device
2873  * @port_map: pointer to the port list to hold the allocated ports
2874  *
2875  * Returns zero or a negative error code.
2876  */
2877 static int dsp_allocate_router_ports(struct hda_codec *codec,
2878                                      unsigned int num_chans,
2879                                      unsigned int ports_per_channel,
2880                                      unsigned int start_device,
2881                                      unsigned int *port_map)
2882 {
2883         int status = 0;
2884         int res;
2885         u8 val;
2886
2887         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2888         if (status < 0)
2889                 return status;
2890
2891         val = start_device << 6;
2892         val |= (ports_per_channel - 1) << 4;
2893         val |= num_chans - 1;
2894
2895         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2896                             VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2897                             val);
2898
2899         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2900                             VENDOR_CHIPIO_PORT_ALLOC_SET,
2901                             MEM_CONNID_DSP);
2902
2903         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2904         if (status < 0)
2905                 return status;
2906
2907         res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2908                                 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2909
2910         *port_map = res;
2911
2912         return (res < 0) ? res : 0;
2913 }
2914
2915 /*
2916  * Free router ports
2917  */
2918 static int dsp_free_router_ports(struct hda_codec *codec)
2919 {
2920         int status = 0;
2921
2922         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2923         if (status < 0)
2924                 return status;
2925
2926         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2927                             VENDOR_CHIPIO_PORT_FREE_SET,
2928                             MEM_CONNID_DSP);
2929
2930         status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2931
2932         return status;
2933 }
2934
2935 /*
2936  * Allocate DSP ports for the download stream
2937  */
2938 static int dsp_allocate_ports(struct hda_codec *codec,
2939                         unsigned int num_chans,
2940                         unsigned int rate_multi, unsigned int *port_map)
2941 {
2942         int status;
2943
2944         codec_dbg(codec, "     dsp_allocate_ports() -- begin\n");
2945
2946         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2947                 codec_dbg(codec, "bad rate multiple\n");
2948                 return -EINVAL;
2949         }
2950
2951         status = dsp_allocate_router_ports(codec, num_chans,
2952                                            rate_multi, 0, port_map);
2953
2954         codec_dbg(codec, "     dsp_allocate_ports() -- complete\n");
2955
2956         return status;
2957 }
2958
2959 static int dsp_allocate_ports_format(struct hda_codec *codec,
2960                         const unsigned short fmt,
2961                         unsigned int *port_map)
2962 {
2963         int status;
2964         unsigned int num_chans;
2965
2966         unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2967         unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2968         unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2969
2970         if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2971                 codec_dbg(codec, "bad rate multiple\n");
2972                 return -EINVAL;
2973         }
2974
2975         num_chans = get_hdafmt_chs(fmt) + 1;
2976
2977         status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2978
2979         return status;
2980 }
2981
2982 /*
2983  * free DSP ports
2984  */
2985 static int dsp_free_ports(struct hda_codec *codec)
2986 {
2987         int status;
2988
2989         codec_dbg(codec, "     dsp_free_ports() -- begin\n");
2990
2991         status = dsp_free_router_ports(codec);
2992         if (status < 0) {
2993                 codec_dbg(codec, "free router ports fail\n");
2994                 return status;
2995         }
2996         codec_dbg(codec, "     dsp_free_ports() -- complete\n");
2997
2998         return status;
2999 }
3000
3001 /*
3002  *  HDA DMA engine stuffs for DSP code download
3003  */
3004 struct dma_engine {
3005         struct hda_codec *codec;
3006         unsigned short m_converter_format;
3007         struct snd_dma_buffer *dmab;
3008         unsigned int buf_size;
3009 };
3010
3011
3012 enum dma_state {
3013         DMA_STATE_STOP  = 0,
3014         DMA_STATE_RUN   = 1
3015 };
3016
3017 static int dma_convert_to_hda_format(struct hda_codec *codec,
3018                 unsigned int sample_rate,
3019                 unsigned short channels,
3020                 unsigned short *hda_format)
3021 {
3022         unsigned int format_val;
3023
3024         format_val = snd_hdac_calc_stream_format(sample_rate,
3025                                 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
3026
3027         if (hda_format)
3028                 *hda_format = (unsigned short)format_val;
3029
3030         return 0;
3031 }
3032
3033 /*
3034  *  Reset DMA for DSP download
3035  */
3036 static int dma_reset(struct dma_engine *dma)
3037 {
3038         struct hda_codec *codec = dma->codec;
3039         struct ca0132_spec *spec = codec->spec;
3040         int status;
3041
3042         if (dma->dmab->area)
3043                 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
3044
3045         status = snd_hda_codec_load_dsp_prepare(codec,
3046                         dma->m_converter_format,
3047                         dma->buf_size,
3048                         dma->dmab);
3049         if (status < 0)
3050                 return status;
3051         spec->dsp_stream_id = status;
3052         return 0;
3053 }
3054
3055 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
3056 {
3057         bool cmd;
3058
3059         switch (state) {
3060         case DMA_STATE_STOP:
3061                 cmd = false;
3062                 break;
3063         case DMA_STATE_RUN:
3064                 cmd = true;
3065                 break;
3066         default:
3067                 return 0;
3068         }
3069
3070         snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
3071         return 0;
3072 }
3073
3074 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
3075 {
3076         return dma->dmab->bytes;
3077 }
3078
3079 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
3080 {
3081         return dma->dmab->area;
3082 }
3083
3084 static int dma_xfer(struct dma_engine *dma,
3085                 const unsigned int *data,
3086                 unsigned int count)
3087 {
3088         memcpy(dma->dmab->area, data, count);
3089         return 0;
3090 }
3091
3092 static void dma_get_converter_format(
3093                 struct dma_engine *dma,
3094                 unsigned short *format)
3095 {
3096         if (format)
3097                 *format = dma->m_converter_format;
3098 }
3099
3100 static unsigned int dma_get_stream_id(struct dma_engine *dma)
3101 {
3102         struct ca0132_spec *spec = dma->codec->spec;
3103
3104         return spec->dsp_stream_id;
3105 }
3106
3107 struct dsp_image_seg {
3108         u32 magic;
3109         u32 chip_addr;
3110         u32 count;
3111         u32 data[];
3112 };
3113
3114 static const u32 g_magic_value = 0x4c46584d;
3115 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
3116
3117 static bool is_valid(const struct dsp_image_seg *p)
3118 {
3119         return p->magic == g_magic_value;
3120 }
3121
3122 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
3123 {
3124         return g_chip_addr_magic_value == p->chip_addr;
3125 }
3126
3127 static bool is_last(const struct dsp_image_seg *p)
3128 {
3129         return p->count == 0;
3130 }
3131
3132 static size_t dsp_sizeof(const struct dsp_image_seg *p)
3133 {
3134         return struct_size(p, data, p->count);
3135 }
3136
3137 static const struct dsp_image_seg *get_next_seg_ptr(
3138                                 const struct dsp_image_seg *p)
3139 {
3140         return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
3141 }
3142
3143 /*
3144  * CA0132 chip DSP transfer stuffs.  For DSP download.
3145  */
3146 #define INVALID_DMA_CHANNEL (~0U)
3147
3148 /*
3149  * Program a list of address/data pairs via the ChipIO widget.
3150  * The segment data is in the format of successive pairs of words.
3151  * These are repeated as indicated by the segment's count field.
3152  */
3153 static int dspxfr_hci_write(struct hda_codec *codec,
3154                         const struct dsp_image_seg *fls)
3155 {
3156         int status;
3157         const u32 *data;
3158         unsigned int count;
3159
3160         if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
3161                 codec_dbg(codec, "hci_write invalid params\n");
3162                 return -EINVAL;
3163         }
3164
3165         count = fls->count;
3166         data = (u32 *)(fls->data);
3167         while (count >= 2) {
3168                 status = chipio_write(codec, data[0], data[1]);
3169                 if (status < 0) {
3170                         codec_dbg(codec, "hci_write chipio failed\n");
3171                         return status;
3172                 }
3173                 count -= 2;
3174                 data  += 2;
3175         }
3176         return 0;
3177 }
3178
3179 /**
3180  * dspxfr_one_seg - Write a block of data into DSP code or data RAM using pre-allocated DMA engine.
3181  *
3182  * @codec: the HDA codec
3183  * @fls: pointer to a fast load image
3184  * @reloc: Relocation address for loading single-segment overlays, or 0 for
3185  *         no relocation
3186  * @dma_engine: pointer to DMA engine to be used for DSP download
3187  * @dma_chan: The number of DMA channels used for DSP download
3188  * @port_map_mask: port mapping
3189  * @ovly: TRUE if overlay format is required
3190  *
3191  * Returns zero or a negative error code.
3192  */
3193 static int dspxfr_one_seg(struct hda_codec *codec,
3194                         const struct dsp_image_seg *fls,
3195                         unsigned int reloc,
3196                         struct dma_engine *dma_engine,
3197                         unsigned int dma_chan,
3198                         unsigned int port_map_mask,
3199                         bool ovly)
3200 {
3201         int status = 0;
3202         bool comm_dma_setup_done = false;
3203         const unsigned int *data;
3204         unsigned int chip_addx;
3205         unsigned int words_to_write;
3206         unsigned int buffer_size_words;
3207         unsigned char *buffer_addx;
3208         unsigned short hda_format;
3209         unsigned int sample_rate_div;
3210         unsigned int sample_rate_mul;
3211         unsigned int num_chans;
3212         unsigned int hda_frame_size_words;
3213         unsigned int remainder_words;
3214         const u32 *data_remainder;
3215         u32 chip_addx_remainder;
3216         unsigned int run_size_words;
3217         const struct dsp_image_seg *hci_write = NULL;
3218         unsigned long timeout;
3219         bool dma_active;
3220
3221         if (fls == NULL)
3222                 return -EINVAL;
3223         if (is_hci_prog_list_seg(fls)) {
3224                 hci_write = fls;
3225                 fls = get_next_seg_ptr(fls);
3226         }
3227
3228         if (hci_write && (!fls || is_last(fls))) {
3229                 codec_dbg(codec, "hci_write\n");
3230                 return dspxfr_hci_write(codec, hci_write);
3231         }
3232
3233         if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
3234                 codec_dbg(codec, "Invalid Params\n");
3235                 return -EINVAL;
3236         }
3237
3238         data = fls->data;
3239         chip_addx = fls->chip_addr;
3240         words_to_write = fls->count;
3241
3242         if (!words_to_write)
3243                 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
3244         if (reloc)
3245                 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
3246
3247         if (!UC_RANGE(chip_addx, words_to_write) &&
3248             !X_RANGE_ALL(chip_addx, words_to_write) &&
3249             !Y_RANGE_ALL(chip_addx, words_to_write)) {
3250                 codec_dbg(codec, "Invalid chip_addx Params\n");
3251                 return -EINVAL;
3252         }
3253
3254         buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
3255                                         sizeof(u32);
3256
3257         buffer_addx = dma_get_buffer_addr(dma_engine);
3258
3259         if (buffer_addx == NULL) {
3260                 codec_dbg(codec, "dma_engine buffer NULL\n");
3261                 return -EINVAL;
3262         }
3263
3264         dma_get_converter_format(dma_engine, &hda_format);
3265         sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
3266         sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
3267         num_chans = get_hdafmt_chs(hda_format) + 1;
3268
3269         hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
3270                         (num_chans * sample_rate_mul / sample_rate_div));
3271
3272         if (hda_frame_size_words == 0) {
3273                 codec_dbg(codec, "frmsz zero\n");
3274                 return -EINVAL;
3275         }
3276
3277         buffer_size_words = min(buffer_size_words,
3278                                 (unsigned int)(UC_RANGE(chip_addx, 1) ?
3279                                 65536 : 32768));
3280         buffer_size_words -= buffer_size_words % hda_frame_size_words;
3281         codec_dbg(codec,
3282                    "chpadr=0x%08x frmsz=%u nchan=%u "
3283                    "rate_mul=%u div=%u bufsz=%u\n",
3284                    chip_addx, hda_frame_size_words, num_chans,
3285                    sample_rate_mul, sample_rate_div, buffer_size_words);
3286
3287         if (buffer_size_words < hda_frame_size_words) {
3288                 codec_dbg(codec, "dspxfr_one_seg:failed\n");
3289                 return -EINVAL;
3290         }
3291
3292         remainder_words = words_to_write % hda_frame_size_words;
3293         data_remainder = data;
3294         chip_addx_remainder = chip_addx;
3295
3296         data += remainder_words;
3297         chip_addx += remainder_words*sizeof(u32);
3298         words_to_write -= remainder_words;
3299
3300         while (words_to_write != 0) {
3301                 run_size_words = min(buffer_size_words, words_to_write);
3302                 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
3303                             words_to_write, run_size_words, remainder_words);
3304                 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
3305                 if (!comm_dma_setup_done) {
3306                         status = dsp_dma_stop(codec, dma_chan, ovly);
3307                         if (status < 0)
3308                                 return status;
3309                         status = dsp_dma_setup_common(codec, chip_addx,
3310                                                 dma_chan, port_map_mask, ovly);
3311                         if (status < 0)
3312                                 return status;
3313                         comm_dma_setup_done = true;
3314                 }
3315
3316                 status = dsp_dma_setup(codec, chip_addx,
3317                                                 run_size_words, dma_chan);
3318                 if (status < 0)
3319                         return status;
3320                 status = dsp_dma_start(codec, dma_chan, ovly);
3321                 if (status < 0)
3322                         return status;
3323                 if (!dsp_is_dma_active(codec, dma_chan)) {
3324                         codec_dbg(codec, "dspxfr:DMA did not start\n");
3325                         return -EIO;
3326                 }
3327                 status = dma_set_state(dma_engine, DMA_STATE_RUN);
3328                 if (status < 0)
3329                         return status;
3330                 if (remainder_words != 0) {
3331                         status = chipio_write_multiple(codec,
3332                                                 chip_addx_remainder,
3333                                                 data_remainder,
3334                                                 remainder_words);
3335                         if (status < 0)
3336                                 return status;
3337                         remainder_words = 0;
3338                 }
3339                 if (hci_write) {
3340                         status = dspxfr_hci_write(codec, hci_write);
3341                         if (status < 0)
3342                                 return status;
3343                         hci_write = NULL;
3344                 }
3345
3346                 timeout = jiffies + msecs_to_jiffies(2000);
3347                 do {
3348                         dma_active = dsp_is_dma_active(codec, dma_chan);
3349                         if (!dma_active)
3350                                 break;
3351                         msleep(20);
3352                 } while (time_before(jiffies, timeout));
3353                 if (dma_active)
3354                         break;
3355
3356                 codec_dbg(codec, "+++++ DMA complete\n");
3357                 dma_set_state(dma_engine, DMA_STATE_STOP);
3358                 status = dma_reset(dma_engine);
3359
3360                 if (status < 0)
3361                         return status;
3362
3363                 data += run_size_words;
3364                 chip_addx += run_size_words*sizeof(u32);
3365                 words_to_write -= run_size_words;
3366         }
3367
3368         if (remainder_words != 0) {
3369                 status = chipio_write_multiple(codec, chip_addx_remainder,
3370                                         data_remainder, remainder_words);
3371         }
3372
3373         return status;
3374 }
3375
3376 /**
3377  * dspxfr_image - Write the entire DSP image of a DSP code/data overlay to DSP memories
3378  *
3379  * @codec: the HDA codec
3380  * @fls_data: pointer to a fast load image
3381  * @reloc: Relocation address for loading single-segment overlays, or 0 for
3382  *         no relocation
3383  * @sample_rate: sampling rate of the stream used for DSP download
3384  * @channels: channels of the stream used for DSP download
3385  * @ovly: TRUE if overlay format is required
3386  *
3387  * Returns zero or a negative error code.
3388  */
3389 static int dspxfr_image(struct hda_codec *codec,
3390                         const struct dsp_image_seg *fls_data,
3391                         unsigned int reloc,
3392                         unsigned int sample_rate,
3393                         unsigned short channels,
3394                         bool ovly)
3395 {
3396         struct ca0132_spec *spec = codec->spec;
3397         int status;
3398         unsigned short hda_format = 0;
3399         unsigned int response;
3400         unsigned char stream_id = 0;
3401         struct dma_engine *dma_engine;
3402         unsigned int dma_chan;
3403         unsigned int port_map_mask;
3404
3405         if (fls_data == NULL)
3406                 return -EINVAL;
3407
3408         dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
3409         if (!dma_engine)
3410                 return -ENOMEM;
3411
3412         dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
3413         if (!dma_engine->dmab) {
3414                 kfree(dma_engine);
3415                 return -ENOMEM;
3416         }
3417
3418         dma_engine->codec = codec;
3419         dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
3420         dma_engine->m_converter_format = hda_format;
3421         dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
3422                         DSP_DMA_WRITE_BUFLEN_INIT) * 2;
3423
3424         dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
3425
3426         status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
3427                                         hda_format, &response);
3428
3429         if (status < 0) {
3430                 codec_dbg(codec, "set converter format fail\n");
3431                 goto exit;
3432         }
3433
3434         status = snd_hda_codec_load_dsp_prepare(codec,
3435                                 dma_engine->m_converter_format,
3436                                 dma_engine->buf_size,
3437                                 dma_engine->dmab);
3438         if (status < 0)
3439                 goto exit;
3440         spec->dsp_stream_id = status;
3441
3442         if (ovly) {
3443                 status = dspio_alloc_dma_chan(codec, &dma_chan);
3444                 if (status < 0) {
3445                         codec_dbg(codec, "alloc dmachan fail\n");
3446                         dma_chan = INVALID_DMA_CHANNEL;
3447                         goto exit;
3448                 }
3449         }
3450
3451         port_map_mask = 0;
3452         status = dsp_allocate_ports_format(codec, hda_format,
3453                                         &port_map_mask);
3454         if (status < 0) {
3455                 codec_dbg(codec, "alloc ports fail\n");
3456                 goto exit;
3457         }
3458
3459         stream_id = dma_get_stream_id(dma_engine);
3460         status = codec_set_converter_stream_channel(codec,
3461                         WIDGET_CHIP_CTRL, stream_id, 0, &response);
3462         if (status < 0) {
3463                 codec_dbg(codec, "set stream chan fail\n");
3464                 goto exit;
3465         }
3466
3467         while ((fls_data != NULL) && !is_last(fls_data)) {
3468                 if (!is_valid(fls_data)) {
3469                         codec_dbg(codec, "FLS check fail\n");
3470                         status = -EINVAL;
3471                         goto exit;
3472                 }
3473                 status = dspxfr_one_seg(codec, fls_data, reloc,
3474                                         dma_engine, dma_chan,
3475                                         port_map_mask, ovly);
3476                 if (status < 0)
3477                         break;
3478
3479                 if (is_hci_prog_list_seg(fls_data))
3480                         fls_data = get_next_seg_ptr(fls_data);
3481
3482                 if ((fls_data != NULL) && !is_last(fls_data))
3483                         fls_data = get_next_seg_ptr(fls_data);
3484         }
3485
3486         if (port_map_mask != 0)
3487                 status = dsp_free_ports(codec);
3488
3489         if (status < 0)
3490                 goto exit;
3491
3492         status = codec_set_converter_stream_channel(codec,
3493                                 WIDGET_CHIP_CTRL, 0, 0, &response);
3494
3495 exit:
3496         if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
3497                 dspio_free_dma_chan(codec, dma_chan);
3498
3499         if (dma_engine->dmab->area)
3500                 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3501         kfree(dma_engine->dmab);
3502         kfree(dma_engine);
3503
3504         return status;
3505 }
3506
3507 /*
3508  * CA0132 DSP download stuffs.
3509  */
3510 static void dspload_post_setup(struct hda_codec *codec)
3511 {
3512         struct ca0132_spec *spec = codec->spec;
3513         codec_dbg(codec, "---- dspload_post_setup ------\n");
3514         if (!ca0132_use_alt_functions(spec)) {
3515                 /*set DSP speaker to 2.0 configuration*/
3516                 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3517                 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
3518
3519                 /*update write pointer*/
3520                 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3521         }
3522 }
3523
3524 /**
3525  * dspload_image - Download DSP from a DSP Image Fast Load structure.
3526  *
3527  * @codec: the HDA codec
3528  * @fls: pointer to a fast load image
3529  * @ovly: TRUE if overlay format is required
3530  * @reloc: Relocation address for loading single-segment overlays, or 0 for
3531  *         no relocation
3532  * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
3533  * @router_chans: number of audio router channels to be allocated (0 means use
3534  *                internal defaults; max is 32)
3535  *
3536  * Download DSP from a DSP Image Fast Load structure. This structure is a
3537  * linear, non-constant sized element array of structures, each of which
3538  * contain the count of the data to be loaded, the data itself, and the
3539  * corresponding starting chip address of the starting data location.
3540  * Returns zero or a negative error code.
3541  */
3542 static int dspload_image(struct hda_codec *codec,
3543                         const struct dsp_image_seg *fls,
3544                         bool ovly,
3545                         unsigned int reloc,
3546                         bool autostart,
3547                         int router_chans)
3548 {
3549         int status = 0;
3550         unsigned int sample_rate;
3551         unsigned short channels;
3552
3553         codec_dbg(codec, "---- dspload_image begin ------\n");
3554         if (router_chans == 0) {
3555                 if (!ovly)
3556                         router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3557                 else
3558                         router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3559         }
3560
3561         sample_rate = 48000;
3562         channels = (unsigned short)router_chans;
3563
3564         while (channels > 16) {
3565                 sample_rate *= 2;
3566                 channels /= 2;
3567         }
3568
3569         do {
3570                 codec_dbg(codec, "Ready to program DMA\n");
3571                 if (!ovly)
3572                         status = dsp_reset(codec);
3573
3574                 if (status < 0)
3575                         break;
3576
3577                 codec_dbg(codec, "dsp_reset() complete\n");
3578                 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3579                                       ovly);
3580
3581                 if (status < 0)
3582                         break;
3583
3584                 codec_dbg(codec, "dspxfr_image() complete\n");
3585                 if (autostart && !ovly) {
3586                         dspload_post_setup(codec);
3587                         status = dsp_set_run_state(codec);
3588                 }
3589
3590                 codec_dbg(codec, "LOAD FINISHED\n");
3591         } while (0);
3592
3593         return status;
3594 }
3595
3596 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
3597 static bool dspload_is_loaded(struct hda_codec *codec)
3598 {
3599         unsigned int data = 0;
3600         int status = 0;
3601
3602         status = chipio_read(codec, 0x40004, &data);
3603         if ((status < 0) || (data != 1))
3604                 return false;
3605
3606         return true;
3607 }
3608 #else
3609 #define dspload_is_loaded(codec)        false
3610 #endif
3611
3612 static bool dspload_wait_loaded(struct hda_codec *codec)
3613 {
3614         unsigned long timeout = jiffies + msecs_to_jiffies(2000);
3615
3616         do {
3617                 if (dspload_is_loaded(codec)) {
3618                         codec_info(codec, "ca0132 DSP downloaded and running\n");
3619                         return true;
3620                 }
3621                 msleep(20);
3622         } while (time_before(jiffies, timeout));
3623
3624         codec_err(codec, "ca0132 failed to download DSP\n");
3625         return false;
3626 }
3627
3628 /*
3629  * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3630  * based cards, and has a second mmio region, region2, that's used for special
3631  * commands.
3632  */
3633
3634 /*
3635  * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3636  * the mmio address 0x320 is used to set GPIO pins. The format for the data
3637  * The first eight bits are just the number of the pin. So far, I've only seen
3638  * this number go to 7.
3639  * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3640  * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3641  * then off to send that bit.
3642  */
3643 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3644                 bool enable)
3645 {
3646         struct ca0132_spec *spec = codec->spec;
3647         unsigned short gpio_data;
3648
3649         gpio_data = gpio_pin & 0xF;
3650         gpio_data |= ((enable << 8) & 0x100);
3651
3652         writew(gpio_data, spec->mem_base + 0x320);
3653 }
3654
3655 /*
3656  * Special pci region2 commands that are only used by the AE-5. They follow
3657  * a set format, and require reads at certain points to seemingly 'clear'
3658  * the response data. My first tests didn't do these reads, and would cause
3659  * the card to get locked up until the memory was read. These commands
3660  * seem to work with three distinct values that I've taken to calling group,
3661  * target-id, and value.
3662  */
3663 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3664                 unsigned int target, unsigned int value)
3665 {
3666         struct ca0132_spec *spec = codec->spec;
3667         unsigned int write_val;
3668
3669         writel(0x0000007e, spec->mem_base + 0x210);
3670         readl(spec->mem_base + 0x210);
3671         writel(0x0000005a, spec->mem_base + 0x210);
3672         readl(spec->mem_base + 0x210);
3673         readl(spec->mem_base + 0x210);
3674
3675         writel(0x00800005, spec->mem_base + 0x20c);
3676         writel(group, spec->mem_base + 0x804);
3677
3678         writel(0x00800005, spec->mem_base + 0x20c);
3679         write_val = (target & 0xff);
3680         write_val |= (value << 8);
3681
3682
3683         writel(write_val, spec->mem_base + 0x204);
3684         /*
3685          * Need delay here or else it goes too fast and works inconsistently.
3686          */
3687         msleep(20);
3688
3689         readl(spec->mem_base + 0x860);
3690         readl(spec->mem_base + 0x854);
3691         readl(spec->mem_base + 0x840);
3692
3693         writel(0x00800004, spec->mem_base + 0x20c);
3694         writel(0x00000000, spec->mem_base + 0x210);
3695         readl(spec->mem_base + 0x210);
3696         readl(spec->mem_base + 0x210);
3697 }
3698
3699 /*
3700  * This second type of command is used for setting the sound filter type.
3701  */
3702 static void ca0113_mmio_command_set_type2(struct hda_codec *codec,
3703                 unsigned int group, unsigned int target, unsigned int value)
3704 {
3705         struct ca0132_spec *spec = codec->spec;
3706         unsigned int write_val;
3707
3708         writel(0x0000007e, spec->mem_base + 0x210);
3709         readl(spec->mem_base + 0x210);
3710         writel(0x0000005a, spec->mem_base + 0x210);
3711         readl(spec->mem_base + 0x210);
3712         readl(spec->mem_base + 0x210);
3713
3714         writel(0x00800003, spec->mem_base + 0x20c);
3715         writel(group, spec->mem_base + 0x804);
3716
3717         writel(0x00800005, spec->mem_base + 0x20c);
3718         write_val = (target & 0xff);
3719         write_val |= (value << 8);
3720
3721
3722         writel(write_val, spec->mem_base + 0x204);
3723         msleep(20);
3724         readl(spec->mem_base + 0x860);
3725         readl(spec->mem_base + 0x854);
3726         readl(spec->mem_base + 0x840);
3727
3728         writel(0x00800004, spec->mem_base + 0x20c);
3729         writel(0x00000000, spec->mem_base + 0x210);
3730         readl(spec->mem_base + 0x210);
3731         readl(spec->mem_base + 0x210);
3732 }
3733
3734 /*
3735  * Setup GPIO for the other variants of Core3D.
3736  */
3737
3738 /*
3739  * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3740  * the card shows as having no GPIO pins.
3741  */
3742 static void ca0132_gpio_init(struct hda_codec *codec)
3743 {
3744         struct ca0132_spec *spec = codec->spec;
3745
3746         switch (ca0132_quirk(spec)) {
3747         case QUIRK_SBZ:
3748         case QUIRK_AE5:
3749         case QUIRK_AE7:
3750                 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3751                 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3752                 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3753                 break;
3754         case QUIRK_R3DI:
3755                 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3756                 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3757                 break;
3758         default:
3759                 break;
3760         }
3761
3762 }
3763
3764 /* Sets the GPIO for audio output. */
3765 static void ca0132_gpio_setup(struct hda_codec *codec)
3766 {
3767         struct ca0132_spec *spec = codec->spec;
3768
3769         switch (ca0132_quirk(spec)) {
3770         case QUIRK_SBZ:
3771                 snd_hda_codec_write(codec, 0x01, 0,
3772                                 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3773                 snd_hda_codec_write(codec, 0x01, 0,
3774                                 AC_VERB_SET_GPIO_MASK, 0x07);
3775                 snd_hda_codec_write(codec, 0x01, 0,
3776                                 AC_VERB_SET_GPIO_DATA, 0x04);
3777                 snd_hda_codec_write(codec, 0x01, 0,
3778                                 AC_VERB_SET_GPIO_DATA, 0x06);
3779                 break;
3780         case QUIRK_R3DI:
3781                 snd_hda_codec_write(codec, 0x01, 0,
3782                                 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3783                 snd_hda_codec_write(codec, 0x01, 0,
3784                                 AC_VERB_SET_GPIO_MASK, 0x1F);
3785                 snd_hda_codec_write(codec, 0x01, 0,
3786                                 AC_VERB_SET_GPIO_DATA, 0x0C);
3787                 break;
3788         default:
3789                 break;
3790         }
3791 }
3792
3793 /*
3794  * GPIO control functions for the Recon3D integrated.
3795  */
3796
3797 enum r3di_gpio_bit {
3798         /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3799         R3DI_MIC_SELECT_BIT = 1,
3800         /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3801         R3DI_OUT_SELECT_BIT = 2,
3802         /*
3803          * I dunno what this actually does, but it stays on until the dsp
3804          * is downloaded.
3805          */
3806         R3DI_GPIO_DSP_DOWNLOADING = 3,
3807         /*
3808          * Same as above, no clue what it does, but it comes on after the dsp
3809          * is downloaded.
3810          */
3811         R3DI_GPIO_DSP_DOWNLOADED = 4
3812 };
3813
3814 enum r3di_mic_select {
3815         /* Set GPIO bit 1 to 0 for rear mic */
3816         R3DI_REAR_MIC = 0,
3817         /* Set GPIO bit 1 to 1 for front microphone*/
3818         R3DI_FRONT_MIC = 1
3819 };
3820
3821 enum r3di_out_select {
3822         /* Set GPIO bit 2 to 0 for headphone */
3823         R3DI_HEADPHONE_OUT = 0,
3824         /* Set GPIO bit 2 to 1 for speaker */
3825         R3DI_LINE_OUT = 1
3826 };
3827 enum r3di_dsp_status {
3828         /* Set GPIO bit 3 to 1 until DSP is downloaded */
3829         R3DI_DSP_DOWNLOADING = 0,
3830         /* Set GPIO bit 4 to 1 once DSP is downloaded */
3831         R3DI_DSP_DOWNLOADED = 1
3832 };
3833
3834
3835 static void r3di_gpio_mic_set(struct hda_codec *codec,
3836                 enum r3di_mic_select cur_mic)
3837 {
3838         unsigned int cur_gpio;
3839
3840         /* Get the current GPIO Data setup */
3841         cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3842
3843         switch (cur_mic) {
3844         case R3DI_REAR_MIC:
3845                 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3846                 break;
3847         case R3DI_FRONT_MIC:
3848                 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3849                 break;
3850         }
3851         snd_hda_codec_write(codec, codec->core.afg, 0,
3852                             AC_VERB_SET_GPIO_DATA, cur_gpio);
3853 }
3854
3855 static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3856                 enum r3di_dsp_status dsp_status)
3857 {
3858         unsigned int cur_gpio;
3859
3860         /* Get the current GPIO Data setup */
3861         cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3862
3863         switch (dsp_status) {
3864         case R3DI_DSP_DOWNLOADING:
3865                 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3866                 snd_hda_codec_write(codec, codec->core.afg, 0,
3867                                 AC_VERB_SET_GPIO_DATA, cur_gpio);
3868                 break;
3869         case R3DI_DSP_DOWNLOADED:
3870                 /* Set DOWNLOADING bit to 0. */
3871                 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3872
3873                 snd_hda_codec_write(codec, codec->core.afg, 0,
3874                                 AC_VERB_SET_GPIO_DATA, cur_gpio);
3875
3876                 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3877                 break;
3878         }
3879
3880         snd_hda_codec_write(codec, codec->core.afg, 0,
3881                             AC_VERB_SET_GPIO_DATA, cur_gpio);
3882 }
3883
3884 /*
3885  * PCM callbacks
3886  */
3887 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3888                         struct hda_codec *codec,
3889                         unsigned int stream_tag,
3890                         unsigned int format,
3891                         struct snd_pcm_substream *substream)
3892 {
3893         struct ca0132_spec *spec = codec->spec;
3894
3895         snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3896
3897         return 0;
3898 }
3899
3900 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3901                         struct hda_codec *codec,
3902                         struct snd_pcm_substream *substream)
3903 {
3904         struct ca0132_spec *spec = codec->spec;
3905
3906         if (spec->dsp_state == DSP_DOWNLOADING)
3907                 return 0;
3908
3909         /*If Playback effects are on, allow stream some time to flush
3910          *effects tail*/
3911         if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3912                 msleep(50);
3913
3914         snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3915
3916         return 0;
3917 }
3918
3919 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3920                         struct hda_codec *codec,
3921                         struct snd_pcm_substream *substream)
3922 {
3923         struct ca0132_spec *spec = codec->spec;
3924         unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3925         struct snd_pcm_runtime *runtime = substream->runtime;
3926
3927         if (spec->dsp_state != DSP_DOWNLOADED)
3928                 return 0;
3929
3930         /* Add latency if playback enhancement and either effect is enabled. */
3931         if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3932                 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3933                     (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3934                         latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3935         }
3936
3937         /* Applying Speaker EQ adds latency as well. */
3938         if (spec->cur_out_type == SPEAKER_OUT)
3939                 latency += DSP_SPEAKER_OUT_LATENCY;
3940
3941         return (latency * runtime->rate) / 1000;
3942 }
3943
3944 /*
3945  * Digital out
3946  */
3947 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3948                                         struct hda_codec *codec,
3949                                         struct snd_pcm_substream *substream)
3950 {
3951         struct ca0132_spec *spec = codec->spec;
3952         return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3953 }
3954
3955 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3956                         struct hda_codec *codec,
3957                         unsigned int stream_tag,
3958                         unsigned int format,
3959                         struct snd_pcm_substream *substream)
3960 {
3961         struct ca0132_spec *spec = codec->spec;
3962         return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3963                                              stream_tag, format, substream);
3964 }
3965
3966 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3967                         struct hda_codec *codec,
3968                         struct snd_pcm_substream *substream)
3969 {
3970         struct ca0132_spec *spec = codec->spec;
3971         return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
3972 }
3973
3974 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3975                                          struct hda_codec *codec,
3976                                          struct snd_pcm_substream *substream)
3977 {
3978         struct ca0132_spec *spec = codec->spec;
3979         return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3980 }
3981
3982 /*
3983  * Analog capture
3984  */
3985 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3986                                         struct hda_codec *codec,
3987                                         unsigned int stream_tag,
3988                                         unsigned int format,
3989                                         struct snd_pcm_substream *substream)
3990 {
3991         snd_hda_codec_setup_stream(codec, hinfo->nid,
3992                                    stream_tag, 0, format);
3993
3994         return 0;
3995 }
3996
3997 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3998                         struct hda_codec *codec,
3999                         struct snd_pcm_substream *substream)
4000 {
4001         struct ca0132_spec *spec = codec->spec;
4002
4003         if (spec->dsp_state == DSP_DOWNLOADING)
4004                 return 0;
4005
4006         snd_hda_codec_cleanup_stream(codec, hinfo->nid);
4007         return 0;
4008 }
4009
4010 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
4011                         struct hda_codec *codec,
4012                         struct snd_pcm_substream *substream)
4013 {
4014         struct ca0132_spec *spec = codec->spec;
4015         unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
4016         struct snd_pcm_runtime *runtime = substream->runtime;
4017
4018         if (spec->dsp_state != DSP_DOWNLOADED)
4019                 return 0;
4020
4021         if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4022                 latency += DSP_CRYSTAL_VOICE_LATENCY;
4023
4024         return (latency * runtime->rate) / 1000;
4025 }
4026
4027 /*
4028  * Controls stuffs.
4029  */
4030
4031 /*
4032  * Mixer controls helpers.
4033  */
4034 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
4035         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4036           .name = xname, \
4037           .subdevice = HDA_SUBDEV_AMP_FLAG, \
4038           .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
4039                         SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
4040                         SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
4041           .info = ca0132_volume_info, \
4042           .get = ca0132_volume_get, \
4043           .put = ca0132_volume_put, \
4044           .tlv = { .c = ca0132_volume_tlv }, \
4045           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4046
4047 /*
4048  * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
4049  * volume put, which is used for setting the DSP volume. This was done because
4050  * the ca0132 functions were taking too much time and causing lag.
4051  */
4052 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
4053         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4054           .name = xname, \
4055           .subdevice = HDA_SUBDEV_AMP_FLAG, \
4056           .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
4057                         SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
4058                         SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
4059           .info = snd_hda_mixer_amp_volume_info, \
4060           .get = snd_hda_mixer_amp_volume_get, \
4061           .put = ca0132_alt_volume_put, \
4062           .tlv = { .c = snd_hda_mixer_amp_tlv }, \
4063           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4064
4065 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
4066         { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4067           .name = xname, \
4068           .subdevice = HDA_SUBDEV_AMP_FLAG, \
4069           .info = snd_hda_mixer_amp_switch_info, \
4070           .get = ca0132_switch_get, \
4071           .put = ca0132_switch_put, \
4072           .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
4073
4074 /* stereo */
4075 #define CA0132_CODEC_VOL(xname, nid, dir) \
4076         CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
4077 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
4078         CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
4079 #define CA0132_CODEC_MUTE(xname, nid, dir) \
4080         CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
4081
4082 /* lookup tables */
4083 /*
4084  * Lookup table with decibel values for the DSP. When volume is changed in
4085  * Windows, the DSP is also sent the dB value in floating point. In Windows,
4086  * these values have decimal points, probably because the Windows driver
4087  * actually uses floating point. We can't here, so I made a lookup table of
4088  * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
4089  * DAC's, and 9 is the maximum.
4090  */
4091 static const unsigned int float_vol_db_lookup[] = {
4092 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
4093 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
4094 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
4095 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
4096 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
4097 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
4098 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
4099 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
4100 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
4101 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
4102 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
4103 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
4104 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
4105 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
4106 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
4107 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
4108 0x40C00000, 0x40E00000, 0x41000000, 0x41100000
4109 };
4110
4111 /*
4112  * This table counts from float 0 to 1 in increments of .01, which is
4113  * useful for a few different sliders.
4114  */
4115 static const unsigned int float_zero_to_one_lookup[] = {
4116 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
4117 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
4118 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
4119 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4120 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4121 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4122 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4123 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4124 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4125 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4126 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4127 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4128 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4129 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4130 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4131 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4132 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4133 };
4134
4135 /*
4136  * This table counts from float 10 to 1000, which is the range of the x-bass
4137  * crossover slider in Windows.
4138  */
4139 static const unsigned int float_xbass_xover_lookup[] = {
4140 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
4141 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
4142 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
4143 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
4144 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
4145 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
4146 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
4147 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
4148 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
4149 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
4150 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
4151 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
4152 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
4153 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
4154 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
4155 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
4156 0x44728000, 0x44750000, 0x44778000, 0x447A0000
4157 };
4158
4159 /* The following are for tuning of products */
4160 #ifdef ENABLE_TUNING_CONTROLS
4161
4162 static const unsigned int voice_focus_vals_lookup[] = {
4163 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
4164 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
4165 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
4166 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
4167 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
4168 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
4169 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
4170 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
4171 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
4172 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
4173 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
4174 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
4175 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
4176 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
4177 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
4178 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
4179 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
4180 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
4181 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
4182 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
4183 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
4184 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
4185 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
4186 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
4187 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
4188 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
4189 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
4190 };
4191
4192 static const unsigned int mic_svm_vals_lookup[] = {
4193 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
4194 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
4195 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
4196 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4197 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4198 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4199 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4200 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4201 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4202 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4203 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4204 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4205 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4206 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4207 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4208 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4209 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4210 };
4211
4212 static const unsigned int equalizer_vals_lookup[] = {
4213 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
4214 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
4215 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
4216 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
4217 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
4218 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
4219 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
4220 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
4221 0x41C00000
4222 };
4223
4224 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4225                           const unsigned int *lookup, int idx)
4226 {
4227         int i = 0;
4228
4229         for (i = 0; i < TUNING_CTLS_COUNT; i++)
4230                 if (nid == ca0132_tuning_ctls[i].nid)
4231                         break;
4232
4233         snd_hda_power_up(codec);
4234         dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
4235                         ca0132_tuning_ctls[i].req,
4236                         &(lookup[idx]), sizeof(unsigned int));
4237         snd_hda_power_down(codec);
4238
4239         return 1;
4240 }
4241
4242 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
4243                           struct snd_ctl_elem_value *ucontrol)
4244 {
4245         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4246         struct ca0132_spec *spec = codec->spec;
4247         hda_nid_t nid = get_amp_nid(kcontrol);
4248         long *valp = ucontrol->value.integer.value;
4249         int idx = nid - TUNING_CTL_START_NID;
4250
4251         *valp = spec->cur_ctl_vals[idx];
4252         return 0;
4253 }
4254
4255 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
4256                               struct snd_ctl_elem_info *uinfo)
4257 {
4258         int chs = get_amp_channels(kcontrol);
4259         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4260         uinfo->count = chs == 3 ? 2 : 1;
4261         uinfo->value.integer.min = 20;
4262         uinfo->value.integer.max = 180;
4263         uinfo->value.integer.step = 1;
4264
4265         return 0;
4266 }
4267
4268 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
4269                                 struct snd_ctl_elem_value *ucontrol)
4270 {
4271         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4272         struct ca0132_spec *spec = codec->spec;
4273         hda_nid_t nid = get_amp_nid(kcontrol);
4274         long *valp = ucontrol->value.integer.value;
4275         int idx;
4276
4277         idx = nid - TUNING_CTL_START_NID;
4278         /* any change? */
4279         if (spec->cur_ctl_vals[idx] == *valp)
4280                 return 0;
4281
4282         spec->cur_ctl_vals[idx] = *valp;
4283
4284         idx = *valp - 20;
4285         tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
4286
4287         return 1;
4288 }
4289
4290 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
4291                               struct snd_ctl_elem_info *uinfo)
4292 {
4293         int chs = get_amp_channels(kcontrol);
4294         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4295         uinfo->count = chs == 3 ? 2 : 1;
4296         uinfo->value.integer.min = 0;
4297         uinfo->value.integer.max = 100;
4298         uinfo->value.integer.step = 1;
4299
4300         return 0;
4301 }
4302
4303 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
4304                                 struct snd_ctl_elem_value *ucontrol)
4305 {
4306         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4307         struct ca0132_spec *spec = codec->spec;
4308         hda_nid_t nid = get_amp_nid(kcontrol);
4309         long *valp = ucontrol->value.integer.value;
4310         int idx;
4311
4312         idx = nid - TUNING_CTL_START_NID;
4313         /* any change? */
4314         if (spec->cur_ctl_vals[idx] == *valp)
4315                 return 0;
4316
4317         spec->cur_ctl_vals[idx] = *valp;
4318
4319         idx = *valp;
4320         tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
4321
4322         return 0;
4323 }
4324
4325 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
4326                               struct snd_ctl_elem_info *uinfo)
4327 {
4328         int chs = get_amp_channels(kcontrol);
4329         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4330         uinfo->count = chs == 3 ? 2 : 1;
4331         uinfo->value.integer.min = 0;
4332         uinfo->value.integer.max = 48;
4333         uinfo->value.integer.step = 1;
4334
4335         return 0;
4336 }
4337
4338 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
4339                                 struct snd_ctl_elem_value *ucontrol)
4340 {
4341         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4342         struct ca0132_spec *spec = codec->spec;
4343         hda_nid_t nid = get_amp_nid(kcontrol);
4344         long *valp = ucontrol->value.integer.value;
4345         int idx;
4346
4347         idx = nid - TUNING_CTL_START_NID;
4348         /* any change? */
4349         if (spec->cur_ctl_vals[idx] == *valp)
4350                 return 0;
4351
4352         spec->cur_ctl_vals[idx] = *valp;
4353
4354         idx = *valp;
4355         tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
4356
4357         return 1;
4358 }
4359
4360 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
4361 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
4362
4363 static int add_tuning_control(struct hda_codec *codec,
4364                                 hda_nid_t pnid, hda_nid_t nid,
4365                                 const char *name, int dir)
4366 {
4367         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
4368         int type = dir ? HDA_INPUT : HDA_OUTPUT;
4369         struct snd_kcontrol_new knew =
4370                 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
4371
4372         knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
4373                         SNDRV_CTL_ELEM_ACCESS_TLV_READ;
4374         knew.tlv.c = 0;
4375         knew.tlv.p = 0;
4376         switch (pnid) {
4377         case VOICE_FOCUS:
4378                 knew.info = voice_focus_ctl_info;
4379                 knew.get = tuning_ctl_get;
4380                 knew.put = voice_focus_ctl_put;
4381                 knew.tlv.p = voice_focus_db_scale;
4382                 break;
4383         case MIC_SVM:
4384                 knew.info = mic_svm_ctl_info;
4385                 knew.get = tuning_ctl_get;
4386                 knew.put = mic_svm_ctl_put;
4387                 break;
4388         case EQUALIZER:
4389                 knew.info = equalizer_ctl_info;
4390                 knew.get = tuning_ctl_get;
4391                 knew.put = equalizer_ctl_put;
4392                 knew.tlv.p = eq_db_scale;
4393                 break;
4394         default:
4395                 return 0;
4396         }
4397         knew.private_value =
4398                 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
4399         sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
4400         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
4401 }
4402
4403 static int add_tuning_ctls(struct hda_codec *codec)
4404 {
4405         int i;
4406         int err;
4407
4408         for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4409                 err = add_tuning_control(codec,
4410                                         ca0132_tuning_ctls[i].parent_nid,
4411                                         ca0132_tuning_ctls[i].nid,
4412                                         ca0132_tuning_ctls[i].name,
4413                                         ca0132_tuning_ctls[i].direct);
4414                 if (err < 0)
4415                         return err;
4416         }
4417
4418         return 0;
4419 }
4420
4421 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
4422 {
4423         struct ca0132_spec *spec = codec->spec;
4424         int i;
4425
4426         /* Wedge Angle defaults to 30.  10 below is 30 - 20.  20 is min. */
4427         spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
4428         /* SVM level defaults to 0.74. */
4429         spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
4430
4431         /* EQ defaults to 0dB. */
4432         for (i = 2; i < TUNING_CTLS_COUNT; i++)
4433                 spec->cur_ctl_vals[i] = 24;
4434 }
4435 #endif /*ENABLE_TUNING_CONTROLS*/
4436
4437 /*
4438  * Select the active output.
4439  * If autodetect is enabled, output will be selected based on jack detection.
4440  * If jack inserted, headphone will be selected, else built-in speakers
4441  * If autodetect is disabled, output will be selected based on selection.
4442  */
4443 static int ca0132_select_out(struct hda_codec *codec)
4444 {
4445         struct ca0132_spec *spec = codec->spec;
4446         unsigned int pin_ctl;
4447         int jack_present;
4448         int auto_jack;
4449         unsigned int tmp;
4450         int err;
4451
4452         codec_dbg(codec, "ca0132_select_out\n");
4453
4454         snd_hda_power_up_pm(codec);
4455
4456         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4457
4458         if (auto_jack)
4459                 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
4460         else
4461                 jack_present =
4462                         spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
4463
4464         if (jack_present)
4465                 spec->cur_out_type = HEADPHONE_OUT;
4466         else
4467                 spec->cur_out_type = SPEAKER_OUT;
4468
4469         if (spec->cur_out_type == SPEAKER_OUT) {
4470                 codec_dbg(codec, "ca0132_select_out speaker\n");
4471                 /*speaker out config*/
4472                 tmp = FLOAT_ONE;
4473                 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4474                 if (err < 0)
4475                         goto exit;
4476                 /*enable speaker EQ*/
4477                 tmp = FLOAT_ONE;
4478                 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4479                 if (err < 0)
4480                         goto exit;
4481
4482                 /* Setup EAPD */
4483                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4484                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4485                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4486                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4487                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4488                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4489                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4490                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4491
4492                 /* disable headphone node */
4493                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4494                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4495                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4496                                     pin_ctl & ~PIN_HP);
4497                 /* enable speaker node */
4498                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4499                                 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4500                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4501                                     pin_ctl | PIN_OUT);
4502         } else {
4503                 codec_dbg(codec, "ca0132_select_out hp\n");
4504                 /*headphone out config*/
4505                 tmp = FLOAT_ZERO;
4506                 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4507                 if (err < 0)
4508                         goto exit;
4509                 /*disable speaker EQ*/
4510                 tmp = FLOAT_ZERO;
4511                 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4512                 if (err < 0)
4513                         goto exit;
4514
4515                 /* Setup EAPD */
4516                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4517                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4518                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4519                                     AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4520                 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4521                                     VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4522                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4523                                     AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4524
4525                 /* disable speaker*/
4526                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4527                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4528                 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4529                                     pin_ctl & ~PIN_HP);
4530                 /* enable headphone*/
4531                 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4532                                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4533                 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4534                                     pin_ctl | PIN_HP);
4535         }
4536
4537 exit:
4538         snd_hda_power_down_pm(codec);
4539
4540         return err < 0 ? err : 0;
4541 }
4542
4543 static int ae5_headphone_gain_set(struct hda_codec *codec, long val);
4544 static int zxr_headphone_gain_set(struct hda_codec *codec, long val);
4545 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
4546
4547 static void ae5_mmio_select_out(struct hda_codec *codec)
4548 {
4549         struct ca0132_spec *spec = codec->spec;
4550         const struct ae_ca0113_output_set *out_cmds;
4551         unsigned int i;
4552
4553         if (ca0132_quirk(spec) == QUIRK_AE5)
4554                 out_cmds = &ae5_ca0113_output_presets;
4555         else
4556                 out_cmds = &ae7_ca0113_output_presets;
4557
4558         for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++)
4559                 ca0113_mmio_command_set(codec, out_cmds->group[i],
4560                                 out_cmds->target[i],
4561                                 out_cmds->vals[spec->cur_out_type][i]);
4562 }
4563
4564 static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec)
4565 {
4566         struct ca0132_spec *spec = codec->spec;
4567         int quirk = ca0132_quirk(spec);
4568         unsigned int tmp;
4569         int err;
4570
4571         /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */
4572         if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0
4573                         || spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4574                 return 0;
4575
4576         /* Set front L/R full range. Zero for full-range, one for redirection. */
4577         tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE;
4578         err = dspio_set_uint_param(codec, 0x96,
4579                         SPEAKER_FULL_RANGE_FRONT_L_R, tmp);
4580         if (err < 0)
4581                 return err;
4582
4583         /* When setting full-range rear, both rear and center/lfe are set. */
4584         tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE;
4585         err = dspio_set_uint_param(codec, 0x96,
4586                         SPEAKER_FULL_RANGE_CENTER_LFE, tmp);
4587         if (err < 0)
4588                 return err;
4589
4590         err = dspio_set_uint_param(codec, 0x96,
4591                         SPEAKER_FULL_RANGE_REAR_L_R, tmp);
4592         if (err < 0)
4593                 return err;
4594
4595         /*
4596          * Only the AE series cards set this value when setting full-range,
4597          * and it's always 1.0f.
4598          */
4599         if (quirk == QUIRK_AE5 || quirk == QUIRK_AE7) {
4600                 err = dspio_set_uint_param(codec, 0x96,
4601                                 SPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE);
4602                 if (err < 0)
4603                         return err;
4604         }
4605
4606         return 0;
4607 }
4608
4609 static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec,
4610                 bool val)
4611 {
4612         struct ca0132_spec *spec = codec->spec;
4613         unsigned int tmp;
4614         int err;
4615
4616         if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 &&
4617                         spec->channel_cfg_val != SPEAKER_CHANNELS_2_0)
4618                 tmp = FLOAT_ONE;
4619         else
4620                 tmp = FLOAT_ZERO;
4621
4622         err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp);
4623         if (err < 0)
4624                 return err;
4625
4626         /* If it is enabled, make sure to set the crossover frequency. */
4627         if (tmp) {
4628                 tmp = float_xbass_xover_lookup[spec->xbass_xover_freq];
4629                 err = dspio_set_uint_param(codec, 0x96,
4630                                 SPEAKER_BASS_REDIRECT_XOVER_FREQ, tmp);
4631                 if (err < 0)
4632                         return err;
4633         }
4634
4635         return 0;
4636 }
4637
4638 /*
4639  * These are the commands needed to setup output on each of the different card
4640  * types.
4641  */
4642 static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec,
4643                 const struct ca0132_alt_out_set_quirk_data **quirk_data)
4644 {
4645         struct ca0132_spec *spec = codec->spec;
4646         int quirk = ca0132_quirk(spec);
4647         unsigned int i;
4648
4649         *quirk_data = NULL;
4650         for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) {
4651                 if (quirk_out_set_data[i].quirk_id == quirk) {
4652                         *quirk_data = &quirk_out_set_data[i];
4653                         return;
4654                 }
4655         }
4656 }
4657
4658 static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec)
4659 {
4660         const struct ca0132_alt_out_set_quirk_data *quirk_data;
4661         const struct ca0132_alt_out_set_info *out_info;
4662         struct ca0132_spec *spec = codec->spec;
4663         unsigned int i, gpio_data;
4664         int err;
4665
4666         ca0132_alt_select_out_get_quirk_data(codec, &quirk_data);
4667         if (!quirk_data)
4668                 return 0;
4669
4670         out_info = &quirk_data->out_set_info[spec->cur_out_type];
4671         if (quirk_data->is_ae_series)
4672                 ae5_mmio_select_out(codec);
4673
4674         if (out_info->has_hda_gpio) {
4675                 gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0,
4676                                 AC_VERB_GET_GPIO_DATA, 0);
4677
4678                 if (out_info->hda_gpio_set)
4679                         gpio_data |= (1 << out_info->hda_gpio_pin);
4680                 else
4681                         gpio_data &= ~(1 << out_info->hda_gpio_pin);
4682
4683                 snd_hda_codec_write(codec, codec->core.afg, 0,
4684                                     AC_VERB_SET_GPIO_DATA, gpio_data);
4685         }
4686
4687         if (out_info->mmio_gpio_count) {
4688                 for (i = 0; i < out_info->mmio_gpio_count; i++) {
4689                         ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i],
4690                                         out_info->mmio_gpio_set[i]);
4691                 }
4692         }
4693
4694         if (out_info->scp_cmds_count) {
4695                 for (i = 0; i < out_info->scp_cmds_count; i++) {
4696                         err = dspio_set_uint_param(codec,
4697                                         out_info->scp_cmd_mid[i],
4698                                         out_info->scp_cmd_req[i],
4699                                         out_info->scp_cmd_val[i]);
4700                         if (err < 0)
4701                                 return err;
4702                 }
4703         }
4704
4705         chipio_set_control_param(codec, 0x0d, out_info->dac2port);
4706
4707         if (out_info->has_chipio_write) {
4708                 chipio_write(codec, out_info->chipio_write_addr,
4709                                 out_info->chipio_write_data);
4710         }
4711
4712         if (quirk_data->has_headphone_gain) {
4713                 if (spec->cur_out_type != HEADPHONE_OUT) {
4714                         if (quirk_data->is_ae_series)
4715                                 ae5_headphone_gain_set(codec, 2);
4716                         else
4717                                 zxr_headphone_gain_set(codec, 0);
4718                 } else {
4719                         if (quirk_data->is_ae_series)
4720                                 ae5_headphone_gain_set(codec,
4721                                                 spec->ae5_headphone_gain_val);
4722                         else
4723                                 zxr_headphone_gain_set(codec,
4724                                                 spec->zxr_gain_set);
4725                 }
4726         }
4727
4728         return 0;
4729 }
4730
4731 static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid,
4732                 bool out_enable, bool hp_enable)
4733 {
4734         unsigned int pin_ctl;
4735
4736         pin_ctl = snd_hda_codec_read(codec, nid, 0,
4737                         AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4738
4739         pin_ctl = hp_enable ? pin_ctl | PIN_HP_AMP : pin_ctl & ~PIN_HP_AMP;
4740         pin_ctl = out_enable ? pin_ctl | PIN_OUT : pin_ctl & ~PIN_OUT;
4741         snd_hda_set_pin_ctl(codec, nid, pin_ctl);
4742 }
4743
4744 /*
4745  * This function behaves similarly to the ca0132_select_out funciton above,
4746  * except with a few differences. It adds the ability to select the current
4747  * output with an enumerated control "output source" if the auto detect
4748  * mute switch is set to off. If the auto detect mute switch is enabled, it
4749  * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
4750  * It also adds the ability to auto-detect the front headphone port.
4751  */
4752 static int ca0132_alt_select_out(struct hda_codec *codec)
4753 {
4754         struct ca0132_spec *spec = codec->spec;
4755         unsigned int tmp, outfx_set;
4756         int jack_present;
4757         int auto_jack;
4758         int err;
4759         /* Default Headphone is rear headphone */
4760         hda_nid_t headphone_nid = spec->out_pins[1];
4761
4762         codec_dbg(codec, "%s\n", __func__);
4763
4764         snd_hda_power_up_pm(codec);
4765
4766         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4767
4768         /*
4769          * If headphone rear or front is plugged in, set to headphone.
4770          * If neither is plugged in, set to rear line out. Only if
4771          * hp/speaker auto detect is enabled.
4772          */
4773         if (auto_jack) {
4774                 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
4775                            snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
4776
4777                 if (jack_present)
4778                         spec->cur_out_type = HEADPHONE_OUT;
4779                 else
4780                         spec->cur_out_type = SPEAKER_OUT;
4781         } else
4782                 spec->cur_out_type = spec->out_enum_val;
4783
4784         outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID];
4785
4786         /* Begin DSP output switch, mute DSP volume. */
4787         err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE);
4788         if (err < 0)
4789                 goto exit;
4790
4791         if (ca0132_alt_select_out_quirk_set(codec) < 0)
4792                 goto exit;
4793
4794         switch (spec->cur_out_type) {
4795         case SPEAKER_OUT:
4796                 codec_dbg(codec, "%s speaker\n", __func__);
4797
4798                 /* Enable EAPD */
4799                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4800                         AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4801
4802                 /* Disable headphone node. */
4803                 ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0);
4804                 /* Set front L-R to output. */
4805                 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0);
4806                 /* Set Center/LFE to output. */
4807                 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0);
4808                 /* Set rear surround to output. */
4809                 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0);
4810
4811                 /*
4812                  * Without PlayEnhancement being enabled, if we've got a 2.0
4813                  * setup, set it to floating point eight to disable any DSP
4814                  * processing effects.
4815                  */
4816                 if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4817                         tmp = FLOAT_EIGHT;
4818                 else
4819                         tmp = speaker_channel_cfgs[spec->channel_cfg_val].val;
4820
4821                 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4822                 if (err < 0)
4823                         goto exit;
4824
4825                 break;
4826         case HEADPHONE_OUT:
4827                 codec_dbg(codec, "%s hp\n", __func__);
4828                 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4829                         AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4830
4831                 /* Disable all speaker nodes. */
4832                 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0);
4833                 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0);
4834                 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0);
4835
4836                 /* enable headphone, either front or rear */
4837                 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4838                         headphone_nid = spec->out_pins[2];
4839                 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4840                         headphone_nid = spec->out_pins[1];
4841
4842                 ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1);
4843
4844                 if (outfx_set)
4845                         err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4846                 else
4847                         err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4848
4849                 if (err < 0)
4850                         goto exit;
4851                 break;
4852         }
4853         /*
4854          * If output effects are enabled, set the X-Bass effect value again to
4855          * make sure that it's properly enabled/disabled for speaker
4856          * configurations with an LFE channel.
4857          */
4858         if (outfx_set)
4859                 ca0132_effects_set(codec, X_BASS,
4860                         spec->effects_switch[X_BASS - EFFECT_START_NID]);
4861
4862         /* Set speaker EQ bypass attenuation to 0. */
4863         err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO);
4864         if (err < 0)
4865                 goto exit;
4866
4867         /*
4868          * Although unused on all cards but the AE series, this is always set
4869          * to zero when setting the output.
4870          */
4871         err = dspio_set_uint_param(codec, 0x96,
4872                         SPEAKER_TUNING_USE_SPEAKER_EQ, FLOAT_ZERO);
4873         if (err < 0)
4874                 goto exit;
4875
4876         if (spec->cur_out_type == SPEAKER_OUT)
4877                 err = ca0132_alt_surround_set_bass_redirection(codec,
4878                                 spec->bass_redirection_val);
4879         else
4880                 err = ca0132_alt_surround_set_bass_redirection(codec, 0);
4881
4882         /* Unmute DSP now that we're done with output selection. */
4883         err = dspio_set_uint_param(codec, 0x96,
4884                         SPEAKER_TUNING_MUTE, FLOAT_ZERO);
4885         if (err < 0)
4886                 goto exit;
4887
4888         if (spec->cur_out_type == SPEAKER_OUT) {
4889                 err = ca0132_alt_set_full_range_speaker(codec);
4890                 if (err < 0)
4891                         goto exit;
4892         }
4893
4894 exit:
4895         snd_hda_power_down_pm(codec);
4896
4897         return err < 0 ? err : 0;
4898 }
4899
4900 static void ca0132_unsol_hp_delayed(struct work_struct *work)
4901 {
4902         struct ca0132_spec *spec = container_of(
4903                 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
4904         struct hda_jack_tbl *jack;
4905
4906         if (ca0132_use_alt_functions(spec))
4907                 ca0132_alt_select_out(spec->codec);
4908         else
4909                 ca0132_select_out(spec->codec);
4910
4911         jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
4912         if (jack) {
4913                 jack->block_report = 0;
4914                 snd_hda_jack_report_sync(spec->codec);
4915         }
4916 }
4917
4918 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4919 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4920 static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4921 static int stop_mic1(struct hda_codec *codec);
4922 static int ca0132_cvoice_switch_set(struct hda_codec *codec);
4923 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
4924
4925 /*
4926  * Select the active VIP source
4927  */
4928 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4929 {
4930         struct ca0132_spec *spec = codec->spec;
4931         unsigned int tmp;
4932
4933         if (spec->dsp_state != DSP_DOWNLOADED)
4934                 return 0;
4935
4936         /* if CrystalVoice if off, vipsource should be 0 */
4937         if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4938             (val == 0)) {
4939                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4940                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4941                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4942                 if (spec->cur_mic_type == DIGITAL_MIC)
4943                         tmp = FLOAT_TWO;
4944                 else
4945                         tmp = FLOAT_ONE;
4946                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4947                 tmp = FLOAT_ZERO;
4948                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4949         } else {
4950                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4951                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4952                 if (spec->cur_mic_type == DIGITAL_MIC)
4953                         tmp = FLOAT_TWO;
4954                 else
4955                         tmp = FLOAT_ONE;
4956                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4957                 tmp = FLOAT_ONE;
4958                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4959                 msleep(20);
4960                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4961         }
4962
4963         return 1;
4964 }
4965
4966 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4967 {
4968         struct ca0132_spec *spec = codec->spec;
4969         unsigned int tmp;
4970
4971         if (spec->dsp_state != DSP_DOWNLOADED)
4972                 return 0;
4973
4974         codec_dbg(codec, "%s\n", __func__);
4975
4976         chipio_set_stream_control(codec, 0x03, 0);
4977         chipio_set_stream_control(codec, 0x04, 0);
4978
4979         /* if CrystalVoice is off, vipsource should be 0 */
4980         if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4981             (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4982                 codec_dbg(codec, "%s: off.", __func__);
4983                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4984
4985                 tmp = FLOAT_ZERO;
4986                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4987
4988                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4989                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4990                 if (ca0132_quirk(spec) == QUIRK_R3DI)
4991                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4992
4993
4994                 if (spec->in_enum_val == REAR_LINE_IN)
4995                         tmp = FLOAT_ZERO;
4996                 else {
4997                         if (ca0132_quirk(spec) == QUIRK_SBZ)
4998                                 tmp = FLOAT_THREE;
4999                         else
5000                                 tmp = FLOAT_ONE;
5001                 }
5002
5003                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5004
5005         } else {
5006                 codec_dbg(codec, "%s: on.", __func__);
5007                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
5008                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
5009                 if (ca0132_quirk(spec) == QUIRK_R3DI)
5010                         chipio_set_conn_rate(codec, 0x0F, SR_16_000);
5011
5012                 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
5013                         tmp = FLOAT_TWO;
5014                 else
5015                         tmp = FLOAT_ONE;
5016                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5017
5018                 tmp = FLOAT_ONE;
5019                 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
5020
5021                 msleep(20);
5022                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
5023         }
5024
5025         chipio_set_stream_control(codec, 0x03, 1);
5026         chipio_set_stream_control(codec, 0x04, 1);
5027
5028         return 1;
5029 }
5030
5031 /*
5032  * Select the active microphone.
5033  * If autodetect is enabled, mic will be selected based on jack detection.
5034  * If jack inserted, ext.mic will be selected, else built-in mic
5035  * If autodetect is disabled, mic will be selected based on selection.
5036  */
5037 static int ca0132_select_mic(struct hda_codec *codec)
5038 {
5039         struct ca0132_spec *spec = codec->spec;
5040         int jack_present;
5041         int auto_jack;
5042
5043         codec_dbg(codec, "ca0132_select_mic\n");
5044
5045         snd_hda_power_up_pm(codec);
5046
5047         auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5048
5049         if (auto_jack)
5050                 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
5051         else
5052                 jack_present =
5053                         spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
5054
5055         if (jack_present)
5056                 spec->cur_mic_type = LINE_MIC_IN;
5057         else
5058                 spec->cur_mic_type = DIGITAL_MIC;
5059
5060         if (spec->cur_mic_type == DIGITAL_MIC) {
5061                 /* enable digital Mic */
5062                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
5063                 ca0132_set_dmic(codec, 1);
5064                 ca0132_mic_boost_set(codec, 0);
5065                 /* set voice focus */
5066                 ca0132_effects_set(codec, VOICE_FOCUS,
5067                                    spec->effects_switch
5068                                    [VOICE_FOCUS - EFFECT_START_NID]);
5069         } else {
5070                 /* disable digital Mic */
5071                 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
5072                 ca0132_set_dmic(codec, 0);
5073                 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
5074                 /* disable voice focus */
5075                 ca0132_effects_set(codec, VOICE_FOCUS, 0);
5076         }
5077
5078         snd_hda_power_down_pm(codec);
5079
5080         return 0;
5081 }
5082
5083 /*
5084  * Select the active input.
5085  * Mic detection isn't used, because it's kind of pointless on the SBZ.
5086  * The front mic has no jack-detection, so the only way to switch to it
5087  * is to do it manually in alsamixer.
5088  */
5089 static int ca0132_alt_select_in(struct hda_codec *codec)
5090 {
5091         struct ca0132_spec *spec = codec->spec;
5092         unsigned int tmp;
5093
5094         codec_dbg(codec, "%s\n", __func__);
5095
5096         snd_hda_power_up_pm(codec);
5097
5098         chipio_set_stream_control(codec, 0x03, 0);
5099         chipio_set_stream_control(codec, 0x04, 0);
5100
5101         spec->cur_mic_type = spec->in_enum_val;
5102
5103         switch (spec->cur_mic_type) {
5104         case REAR_MIC:
5105                 switch (ca0132_quirk(spec)) {
5106                 case QUIRK_SBZ:
5107                 case QUIRK_R3D:
5108                         ca0113_mmio_gpio_set(codec, 0, false);
5109                         tmp = FLOAT_THREE;
5110                         break;
5111                 case QUIRK_ZXR:
5112                         tmp = FLOAT_THREE;
5113                         break;
5114                 case QUIRK_R3DI:
5115                         r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
5116                         tmp = FLOAT_ONE;
5117                         break;
5118                 case QUIRK_AE5:
5119                         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5120                         tmp = FLOAT_THREE;
5121                         break;
5122                 case QUIRK_AE7:
5123                         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5124                         tmp = FLOAT_THREE;
5125                         chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5126                                         SR_96_000);
5127                         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5128                                         SR_96_000);
5129                         dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5130                         break;
5131                 default:
5132                         tmp = FLOAT_ONE;
5133                         break;
5134                 }
5135
5136                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5137                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5138                 if (ca0132_quirk(spec) == QUIRK_R3DI)
5139                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5140
5141                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5142
5143                 chipio_set_stream_control(codec, 0x03, 1);
5144                 chipio_set_stream_control(codec, 0x04, 1);
5145                 switch (ca0132_quirk(spec)) {
5146                 case QUIRK_SBZ:
5147                         chipio_write(codec, 0x18B098, 0x0000000C);
5148                         chipio_write(codec, 0x18B09C, 0x0000000C);
5149                         break;
5150                 case QUIRK_ZXR:
5151                         chipio_write(codec, 0x18B098, 0x0000000C);
5152                         chipio_write(codec, 0x18B09C, 0x000000CC);
5153                         break;
5154                 case QUIRK_AE5:
5155                         chipio_write(codec, 0x18B098, 0x0000000C);
5156                         chipio_write(codec, 0x18B09C, 0x0000004C);
5157                         break;
5158                 default:
5159                         break;
5160                 }
5161                 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5162                 break;
5163         case REAR_LINE_IN:
5164                 ca0132_mic_boost_set(codec, 0);
5165                 switch (ca0132_quirk(spec)) {
5166                 case QUIRK_SBZ:
5167                 case QUIRK_R3D:
5168                         ca0113_mmio_gpio_set(codec, 0, false);
5169                         break;
5170                 case QUIRK_R3DI:
5171                         r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
5172                         break;
5173                 case QUIRK_AE5:
5174                         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5175                         break;
5176                 case QUIRK_AE7:
5177                         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5178                         chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5179                                         SR_96_000);
5180                         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5181                                         SR_96_000);
5182                         dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5183                         break;
5184                 default:
5185                         break;
5186                 }
5187
5188                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5189                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5190                 if (ca0132_quirk(spec) == QUIRK_R3DI)
5191                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5192
5193                 if (ca0132_quirk(spec) == QUIRK_AE7)
5194                         tmp = FLOAT_THREE;
5195                 else
5196                         tmp = FLOAT_ZERO;
5197                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5198
5199                 switch (ca0132_quirk(spec)) {
5200                 case QUIRK_SBZ:
5201                 case QUIRK_AE5:
5202                         chipio_write(codec, 0x18B098, 0x00000000);
5203                         chipio_write(codec, 0x18B09C, 0x00000000);
5204                         break;
5205                 default:
5206                         break;
5207                 }
5208                 chipio_set_stream_control(codec, 0x03, 1);
5209                 chipio_set_stream_control(codec, 0x04, 1);
5210                 break;
5211         case FRONT_MIC:
5212                 switch (ca0132_quirk(spec)) {
5213                 case QUIRK_SBZ:
5214                 case QUIRK_R3D:
5215                         ca0113_mmio_gpio_set(codec, 0, true);
5216                         ca0113_mmio_gpio_set(codec, 5, false);
5217                         tmp = FLOAT_THREE;
5218                         break;
5219                 case QUIRK_R3DI:
5220                         r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
5221                         tmp = FLOAT_ONE;
5222                         break;
5223                 case QUIRK_AE5:
5224                         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5225                         tmp = FLOAT_THREE;
5226                         break;
5227                 default:
5228                         tmp = FLOAT_ONE;
5229                         break;
5230                 }
5231
5232                 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5233                 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5234                 if (ca0132_quirk(spec) == QUIRK_R3DI)
5235                         chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5236
5237                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5238
5239                 chipio_set_stream_control(codec, 0x03, 1);
5240                 chipio_set_stream_control(codec, 0x04, 1);
5241
5242                 switch (ca0132_quirk(spec)) {
5243                 case QUIRK_SBZ:
5244                         chipio_write(codec, 0x18B098, 0x0000000C);
5245                         chipio_write(codec, 0x18B09C, 0x000000CC);
5246                         break;
5247                 case QUIRK_AE5:
5248                         chipio_write(codec, 0x18B098, 0x0000000C);
5249                         chipio_write(codec, 0x18B09C, 0x0000004C);
5250                         break;
5251                 default:
5252                         break;
5253                 }
5254                 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5255                 break;
5256         }
5257         ca0132_cvoice_switch_set(codec);
5258
5259         snd_hda_power_down_pm(codec);
5260         return 0;
5261 }
5262
5263 /*
5264  * Check if VNODE settings take effect immediately.
5265  */
5266 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
5267                                      hda_nid_t vnid,
5268                                      hda_nid_t *shared_nid)
5269 {
5270         struct ca0132_spec *spec = codec->spec;
5271         hda_nid_t nid;
5272
5273         switch (vnid) {
5274         case VNID_SPK:
5275                 nid = spec->shared_out_nid;
5276                 break;
5277         case VNID_MIC:
5278                 nid = spec->shared_mic_nid;
5279                 break;
5280         default:
5281                 return false;
5282         }
5283
5284         if (shared_nid)
5285                 *shared_nid = nid;
5286
5287         return true;
5288 }
5289
5290 /*
5291 * The following functions are control change helpers.
5292 * They return 0 if no changed.  Return 1 if changed.
5293 */
5294 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
5295 {
5296         struct ca0132_spec *spec = codec->spec;
5297         unsigned int tmp;
5298
5299         /* based on CrystalVoice state to enable VoiceFX. */
5300         if (enable) {
5301                 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
5302                         FLOAT_ONE : FLOAT_ZERO;
5303         } else {
5304                 tmp = FLOAT_ZERO;
5305         }
5306
5307         dspio_set_uint_param(codec, ca0132_voicefx.mid,
5308                              ca0132_voicefx.reqs[0], tmp);
5309
5310         return 1;
5311 }
5312
5313 /*
5314  * Set the effects parameters
5315  */
5316 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
5317 {
5318         struct ca0132_spec *spec = codec->spec;
5319         unsigned int on, tmp, channel_cfg;
5320         int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
5321         int err = 0;
5322         int idx = nid - EFFECT_START_NID;
5323
5324         if ((idx < 0) || (idx >= num_fx))
5325                 return 0; /* no changed */
5326
5327         /* for out effect, qualify with PE */
5328         if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
5329                 /* if PE if off, turn off out effects. */
5330                 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
5331                         val = 0;
5332                 if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) {
5333                         channel_cfg = spec->channel_cfg_val;
5334                         if (channel_cfg != SPEAKER_CHANNELS_2_0 &&
5335                                         channel_cfg != SPEAKER_CHANNELS_4_0)
5336                                 val = 0;
5337                 }
5338         }
5339
5340         /* for in effect, qualify with CrystalVoice */
5341         if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
5342                 /* if CrystalVoice if off, turn off in effects. */
5343                 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
5344                         val = 0;
5345
5346                 /* Voice Focus applies to 2-ch Mic, Digital Mic */
5347                 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
5348                         val = 0;
5349
5350                 /* If Voice Focus on SBZ, set to two channel. */
5351                 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec)
5352                                 && (spec->cur_mic_type != REAR_LINE_IN)) {
5353                         if (spec->effects_switch[CRYSTAL_VOICE -
5354                                                  EFFECT_START_NID]) {
5355
5356                                 if (spec->effects_switch[VOICE_FOCUS -
5357                                                          EFFECT_START_NID]) {
5358                                         tmp = FLOAT_TWO;
5359                                         val = 1;
5360                                 } else
5361                                         tmp = FLOAT_ONE;
5362
5363                                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5364                         }
5365                 }
5366                 /*
5367                  * For SBZ noise reduction, there's an extra command
5368                  * to module ID 0x47. No clue why.
5369                  */
5370                 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec)
5371                                 && (spec->cur_mic_type != REAR_LINE_IN)) {
5372                         if (spec->effects_switch[CRYSTAL_VOICE -
5373                                                  EFFECT_START_NID]) {
5374                                 if (spec->effects_switch[NOISE_REDUCTION -
5375                                                          EFFECT_START_NID])
5376                                         tmp = FLOAT_ONE;
5377                                 else
5378                                         tmp = FLOAT_ZERO;
5379                         } else
5380                                 tmp = FLOAT_ZERO;
5381
5382                         dspio_set_uint_param(codec, 0x47, 0x00, tmp);
5383                 }
5384
5385                 /* If rear line in disable effects. */
5386                 if (ca0132_use_alt_functions(spec) &&
5387                                 spec->in_enum_val == REAR_LINE_IN)
5388                         val = 0;
5389         }
5390
5391         codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5392                     nid, val);
5393
5394         on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
5395         err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5396                                    ca0132_effects[idx].reqs[0], on);
5397
5398         if (err < 0)
5399                 return 0; /* no changed */
5400
5401         return 1;
5402 }
5403
5404 /*
5405  * Turn on/off Playback Enhancements
5406  */
5407 static int ca0132_pe_switch_set(struct hda_codec *codec)
5408 {
5409         struct ca0132_spec *spec = codec->spec;
5410         hda_nid_t nid;
5411         int i, ret = 0;
5412
5413         codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
5414                     spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
5415
5416         if (ca0132_use_alt_functions(spec))
5417                 ca0132_alt_select_out(codec);
5418
5419         i = OUT_EFFECT_START_NID - EFFECT_START_NID;
5420         nid = OUT_EFFECT_START_NID;
5421         /* PE affects all out effects */
5422         for (; nid < OUT_EFFECT_END_NID; nid++, i++)
5423                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5424
5425         return ret;
5426 }
5427
5428 /* Check if Mic1 is streaming, if so, stop streaming */
5429 static int stop_mic1(struct hda_codec *codec)
5430 {
5431         struct ca0132_spec *spec = codec->spec;
5432         unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
5433                                                  AC_VERB_GET_CONV, 0);
5434         if (oldval != 0)
5435                 snd_hda_codec_write(codec, spec->adcs[0], 0,
5436                                     AC_VERB_SET_CHANNEL_STREAMID,
5437                                     0);
5438         return oldval;
5439 }
5440
5441 /* Resume Mic1 streaming if it was stopped. */
5442 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
5443 {
5444         struct ca0132_spec *spec = codec->spec;
5445         /* Restore the previous stream and channel */
5446         if (oldval != 0)
5447                 snd_hda_codec_write(codec, spec->adcs[0], 0,
5448                                     AC_VERB_SET_CHANNEL_STREAMID,
5449                                     oldval);
5450 }
5451
5452 /*
5453  * Turn on/off CrystalVoice
5454  */
5455 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
5456 {
5457         struct ca0132_spec *spec = codec->spec;
5458         hda_nid_t nid;
5459         int i, ret = 0;
5460         unsigned int oldval;
5461
5462         codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
5463                     spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
5464
5465         i = IN_EFFECT_START_NID - EFFECT_START_NID;
5466         nid = IN_EFFECT_START_NID;
5467         /* CrystalVoice affects all in effects */
5468         for (; nid < IN_EFFECT_END_NID; nid++, i++)
5469                 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5470
5471         /* including VoiceFX */
5472         ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
5473
5474         /* set correct vipsource */
5475         oldval = stop_mic1(codec);
5476         if (ca0132_use_alt_functions(spec))
5477                 ret |= ca0132_alt_set_vipsource(codec, 1);
5478         else
5479                 ret |= ca0132_set_vipsource(codec, 1);
5480         resume_mic1(codec, oldval);
5481         return ret;
5482 }
5483
5484 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
5485 {
5486         struct ca0132_spec *spec = codec->spec;
5487         int ret = 0;
5488
5489         if (val) /* on */
5490                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5491                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
5492         else /* off */
5493                 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5494                                         HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
5495
5496         return ret;
5497 }
5498
5499 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
5500 {
5501         struct ca0132_spec *spec = codec->spec;
5502         int ret = 0;
5503
5504         ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5505                                 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
5506         return ret;
5507 }
5508
5509 static int ae5_headphone_gain_set(struct hda_codec *codec, long val)
5510 {
5511         unsigned int i;
5512
5513         for (i = 0; i < 4; i++)
5514                 ca0113_mmio_command_set(codec, 0x48, 0x11 + i,
5515                                 ae5_headphone_gain_presets[val].vals[i]);
5516         return 0;
5517 }
5518
5519 /*
5520  * gpio pin 1 is a relay that switches on/off, apparently setting the headphone
5521  * amplifier to handle a 600 ohm load.
5522  */
5523 static int zxr_headphone_gain_set(struct hda_codec *codec, long val)
5524 {
5525         ca0113_mmio_gpio_set(codec, 1, val);
5526
5527         return 0;
5528 }
5529
5530 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
5531                                 struct snd_ctl_elem_value *ucontrol)
5532 {
5533         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5534         hda_nid_t nid = get_amp_nid(kcontrol);
5535         hda_nid_t shared_nid = 0;
5536         bool effective;
5537         int ret = 0;
5538         struct ca0132_spec *spec = codec->spec;
5539         int auto_jack;
5540
5541         if (nid == VNID_HP_SEL) {
5542                 auto_jack =
5543                         spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5544                 if (!auto_jack) {
5545                         if (ca0132_use_alt_functions(spec))
5546                                 ca0132_alt_select_out(codec);
5547                         else
5548                                 ca0132_select_out(codec);
5549                 }
5550                 return 1;
5551         }
5552
5553         if (nid == VNID_AMIC1_SEL) {
5554                 auto_jack =
5555                         spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5556                 if (!auto_jack)
5557                         ca0132_select_mic(codec);
5558                 return 1;
5559         }
5560
5561         if (nid == VNID_HP_ASEL) {
5562                 if (ca0132_use_alt_functions(spec))
5563                         ca0132_alt_select_out(codec);
5564                 else
5565                         ca0132_select_out(codec);
5566                 return 1;
5567         }
5568
5569         if (nid == VNID_AMIC1_ASEL) {
5570                 ca0132_select_mic(codec);
5571                 return 1;
5572         }
5573
5574         /* if effective conditions, then update hw immediately. */
5575         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5576         if (effective) {
5577                 int dir = get_amp_direction(kcontrol);
5578                 int ch = get_amp_channels(kcontrol);
5579                 unsigned long pval;
5580
5581                 mutex_lock(&codec->control_mutex);
5582                 pval = kcontrol->private_value;
5583                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5584                                                                 0, dir);
5585                 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
5586                 kcontrol->private_value = pval;
5587                 mutex_unlock(&codec->control_mutex);
5588         }
5589
5590         return ret;
5591 }
5592 /* End of control change helpers. */
5593
5594 static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec,
5595                 long idx)
5596 {
5597         snd_hda_power_up(codec);
5598
5599         dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ,
5600                         &(float_xbass_xover_lookup[idx]), sizeof(unsigned int));
5601
5602         snd_hda_power_down(codec);
5603 }
5604
5605 /*
5606  * Below I've added controls to mess with the effect levels, I've only enabled
5607  * them on the Sound Blaster Z, but they would probably also work on the
5608  * Chromebook. I figured they were probably tuned specifically for it, and left
5609  * out for a reason.
5610  */
5611
5612 /* Sets DSP effect level from the sliders above the controls */
5613
5614 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
5615                           const unsigned int *lookup, int idx)
5616 {
5617         int i = 0;
5618         unsigned int y;
5619         /*
5620          * For X_BASS, req 2 is actually crossover freq instead of
5621          * effect level
5622          */
5623         if (nid == X_BASS)
5624                 y = 2;
5625         else
5626                 y = 1;
5627
5628         snd_hda_power_up(codec);
5629         if (nid == XBASS_XOVER) {
5630                 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5631                         if (ca0132_effects[i].nid == X_BASS)
5632                                 break;
5633
5634                 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5635                                 ca0132_effects[i].reqs[1],
5636                                 &(lookup[idx - 1]), sizeof(unsigned int));
5637         } else {
5638                 /* Find the actual effect structure */
5639                 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5640                         if (nid == ca0132_effects[i].nid)
5641                                 break;
5642
5643                 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5644                                 ca0132_effects[i].reqs[y],
5645                                 &(lookup[idx]), sizeof(unsigned int));
5646         }
5647
5648         snd_hda_power_down(codec);
5649
5650         return 0;
5651 }
5652
5653 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
5654                           struct snd_ctl_elem_value *ucontrol)
5655 {
5656         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5657         struct ca0132_spec *spec = codec->spec;
5658         long *valp = ucontrol->value.integer.value;
5659         hda_nid_t nid = get_amp_nid(kcontrol);
5660
5661         if (nid == BASS_REDIRECTION_XOVER)
5662                 *valp = spec->bass_redirect_xover_freq;
5663         else
5664                 *valp = spec->xbass_xover_freq;
5665
5666         return 0;
5667 }
5668
5669 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
5670                           struct snd_ctl_elem_value *ucontrol)
5671 {
5672         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5673         struct ca0132_spec *spec = codec->spec;
5674         hda_nid_t nid = get_amp_nid(kcontrol);
5675         long *valp = ucontrol->value.integer.value;
5676         int idx = nid - OUT_EFFECT_START_NID;
5677
5678         *valp = spec->fx_ctl_val[idx];
5679         return 0;
5680 }
5681
5682 /*
5683  * The X-bass crossover starts at 10hz, so the min is 1. The
5684  * frequency is set in multiples of 10.
5685  */
5686 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
5687                 struct snd_ctl_elem_info *uinfo)
5688 {
5689         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5690         uinfo->count = 1;
5691         uinfo->value.integer.min = 1;
5692         uinfo->value.integer.max = 100;
5693         uinfo->value.integer.step = 1;
5694
5695         return 0;
5696 }
5697
5698 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
5699                 struct snd_ctl_elem_info *uinfo)
5700 {
5701         int chs = get_amp_channels(kcontrol);
5702
5703         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5704         uinfo->count = chs == 3 ? 2 : 1;
5705         uinfo->value.integer.min = 0;
5706         uinfo->value.integer.max = 100;
5707         uinfo->value.integer.step = 1;
5708
5709         return 0;
5710 }
5711
5712 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
5713                                 struct snd_ctl_elem_value *ucontrol)
5714 {
5715         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5716         struct ca0132_spec *spec = codec->spec;
5717         hda_nid_t nid = get_amp_nid(kcontrol);
5718         long *valp = ucontrol->value.integer.value;
5719         long *cur_val;
5720         int idx;
5721
5722         if (nid == BASS_REDIRECTION_XOVER)
5723                 cur_val = &spec->bass_redirect_xover_freq;
5724         else
5725                 cur_val = &spec->xbass_xover_freq;
5726
5727         /* any change? */
5728         if (*cur_val == *valp)
5729                 return 0;
5730
5731         *cur_val = *valp;
5732
5733         idx = *valp;
5734         if (nid == BASS_REDIRECTION_XOVER)
5735                 ca0132_alt_bass_redirection_xover_set(codec, *cur_val);
5736         else
5737                 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
5738
5739         return 0;
5740 }
5741
5742 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
5743                                 struct snd_ctl_elem_value *ucontrol)
5744 {
5745         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5746         struct ca0132_spec *spec = codec->spec;
5747         hda_nid_t nid = get_amp_nid(kcontrol);
5748         long *valp = ucontrol->value.integer.value;
5749         int idx;
5750
5751         idx = nid - EFFECT_START_NID;
5752         /* any change? */
5753         if (spec->fx_ctl_val[idx] == *valp)
5754                 return 0;
5755
5756         spec->fx_ctl_val[idx] = *valp;
5757
5758         idx = *valp;
5759         ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
5760
5761         return 0;
5762 }
5763
5764
5765 /*
5766  * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
5767  * only has off or full 30 dB, and didn't like making a volume slider that has
5768  * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5769  */
5770 #define MIC_BOOST_NUM_OF_STEPS 4
5771 #define MIC_BOOST_ENUM_MAX_STRLEN 10
5772
5773 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
5774                                  struct snd_ctl_elem_info *uinfo)
5775 {
5776         char *sfx = "dB";
5777         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5778
5779         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5780         uinfo->count = 1;
5781         uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
5782         if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
5783                 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
5784         sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
5785         strcpy(uinfo->value.enumerated.name, namestr);
5786         return 0;
5787 }
5788
5789 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
5790                                 struct snd_ctl_elem_value *ucontrol)
5791 {
5792         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5793         struct ca0132_spec *spec = codec->spec;
5794
5795         ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5796         return 0;
5797 }
5798
5799 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
5800                                 struct snd_ctl_elem_value *ucontrol)
5801 {
5802         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5803         struct ca0132_spec *spec = codec->spec;
5804         int sel = ucontrol->value.enumerated.item[0];
5805         unsigned int items = MIC_BOOST_NUM_OF_STEPS;
5806
5807         if (sel >= items)
5808                 return 0;
5809
5810         codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
5811                     sel);
5812
5813         spec->mic_boost_enum_val = sel;
5814
5815         if (spec->in_enum_val != REAR_LINE_IN)
5816                 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5817
5818         return 1;
5819 }
5820
5821 /*
5822  * Sound BlasterX AE-5 Headphone Gain Controls.
5823  */
5824 #define AE5_HEADPHONE_GAIN_MAX 3
5825 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol,
5826                                  struct snd_ctl_elem_info *uinfo)
5827 {
5828         char *sfx = " Ohms)";
5829         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5830
5831         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5832         uinfo->count = 1;
5833         uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX;
5834         if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX)
5835                 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1;
5836         sprintf(namestr, "%s %s",
5837                 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name,
5838                 sfx);
5839         strcpy(uinfo->value.enumerated.name, namestr);
5840         return 0;
5841 }
5842
5843 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol,
5844                                 struct snd_ctl_elem_value *ucontrol)
5845 {
5846         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5847         struct ca0132_spec *spec = codec->spec;
5848
5849         ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val;
5850         return 0;
5851 }
5852
5853 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol,
5854                                 struct snd_ctl_elem_value *ucontrol)
5855 {
5856         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5857         struct ca0132_spec *spec = codec->spec;
5858         int sel = ucontrol->value.enumerated.item[0];
5859         unsigned int items = AE5_HEADPHONE_GAIN_MAX;
5860
5861         if (sel >= items)
5862                 return 0;
5863
5864         codec_dbg(codec, "ae5_headphone_gain: boost=%d\n",
5865                     sel);
5866
5867         spec->ae5_headphone_gain_val = sel;
5868
5869         if (spec->out_enum_val == HEADPHONE_OUT)
5870                 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val);
5871
5872         return 1;
5873 }
5874
5875 /*
5876  * Sound BlasterX AE-5 sound filter enumerated control.
5877  */
5878 #define AE5_SOUND_FILTER_MAX 3
5879
5880 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol,
5881                                  struct snd_ctl_elem_info *uinfo)
5882 {
5883         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5884
5885         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5886         uinfo->count = 1;
5887         uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX;
5888         if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX)
5889                 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1;
5890         sprintf(namestr, "%s",
5891                         ae5_filter_presets[uinfo->value.enumerated.item].name);
5892         strcpy(uinfo->value.enumerated.name, namestr);
5893         return 0;
5894 }
5895
5896 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol,
5897                                 struct snd_ctl_elem_value *ucontrol)
5898 {
5899         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5900         struct ca0132_spec *spec = codec->spec;
5901
5902         ucontrol->value.enumerated.item[0] = spec->ae5_filter_val;
5903         return 0;
5904 }
5905
5906 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol,
5907                                 struct snd_ctl_elem_value *ucontrol)
5908 {
5909         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5910         struct ca0132_spec *spec = codec->spec;
5911         int sel = ucontrol->value.enumerated.item[0];
5912         unsigned int items = AE5_SOUND_FILTER_MAX;
5913
5914         if (sel >= items)
5915                 return 0;
5916
5917         codec_dbg(codec, "ae5_sound_filter: %s\n",
5918                         ae5_filter_presets[sel].name);
5919
5920         spec->ae5_filter_val = sel;
5921
5922         ca0113_mmio_command_set_type2(codec, 0x48, 0x07,
5923                         ae5_filter_presets[sel].val);
5924
5925         return 1;
5926 }
5927
5928 /*
5929  * Input Select Control for alternative ca0132 codecs. This exists because
5930  * front microphone has no auto-detect, and we need a way to set the rear
5931  * as line-in
5932  */
5933 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
5934                                  struct snd_ctl_elem_info *uinfo)
5935 {
5936         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5937         uinfo->count = 1;
5938         uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
5939         if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
5940                 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
5941         strcpy(uinfo->value.enumerated.name,
5942                         in_src_str[uinfo->value.enumerated.item]);
5943         return 0;
5944 }
5945
5946 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
5947                                 struct snd_ctl_elem_value *ucontrol)
5948 {
5949         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5950         struct ca0132_spec *spec = codec->spec;
5951
5952         ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5953         return 0;
5954 }
5955
5956 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
5957                                 struct snd_ctl_elem_value *ucontrol)
5958 {
5959         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5960         struct ca0132_spec *spec = codec->spec;
5961         int sel = ucontrol->value.enumerated.item[0];
5962         unsigned int items = IN_SRC_NUM_OF_INPUTS;
5963
5964         /*
5965          * The AE-7 has no front microphone, so limit items to 2: rear mic and
5966          * line-in.
5967          */
5968         if (ca0132_quirk(spec) == QUIRK_AE7)
5969                 items = 2;
5970
5971         if (sel >= items)
5972                 return 0;
5973
5974         codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
5975                     sel, in_src_str[sel]);
5976
5977         spec->in_enum_val = sel;
5978
5979         ca0132_alt_select_in(codec);
5980
5981         return 1;
5982 }
5983
5984 /* Sound Blaster Z Output Select Control */
5985 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
5986                                  struct snd_ctl_elem_info *uinfo)
5987 {
5988         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5989         uinfo->count = 1;
5990         uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5991         if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5992                 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5993         strcpy(uinfo->value.enumerated.name,
5994                         out_type_str[uinfo->value.enumerated.item]);
5995         return 0;
5996 }
5997
5998 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
5999                                 struct snd_ctl_elem_value *ucontrol)
6000 {
6001         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6002         struct ca0132_spec *spec = codec->spec;
6003
6004         ucontrol->value.enumerated.item[0] = spec->out_enum_val;
6005         return 0;
6006 }
6007
6008 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
6009                                 struct snd_ctl_elem_value *ucontrol)
6010 {
6011         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6012         struct ca0132_spec *spec = codec->spec;
6013         int sel = ucontrol->value.enumerated.item[0];
6014         unsigned int items = NUM_OF_OUTPUTS;
6015         unsigned int auto_jack;
6016
6017         if (sel >= items)
6018                 return 0;
6019
6020         codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
6021                     sel, out_type_str[sel]);
6022
6023         spec->out_enum_val = sel;
6024
6025         auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
6026
6027         if (!auto_jack)
6028                 ca0132_alt_select_out(codec);
6029
6030         return 1;
6031 }
6032
6033 /* Select surround output type: 2.1, 4.0, 4.1, or 5.1. */
6034 static int ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol *kcontrol,
6035                                  struct snd_ctl_elem_info *uinfo)
6036 {
6037         unsigned int items = SPEAKER_CHANNEL_CFG_COUNT;
6038
6039         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6040         uinfo->count = 1;
6041         uinfo->value.enumerated.items = items;
6042         if (uinfo->value.enumerated.item >= items)
6043                 uinfo->value.enumerated.item = items - 1;
6044         strcpy(uinfo->value.enumerated.name,
6045                         speaker_channel_cfgs[uinfo->value.enumerated.item].name);
6046         return 0;
6047 }
6048
6049 static int ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol *kcontrol,
6050                                 struct snd_ctl_elem_value *ucontrol)
6051 {
6052         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6053         struct ca0132_spec *spec = codec->spec;
6054
6055         ucontrol->value.enumerated.item[0] = spec->channel_cfg_val;
6056         return 0;
6057 }
6058
6059 static int ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol *kcontrol,
6060                                 struct snd_ctl_elem_value *ucontrol)
6061 {
6062         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6063         struct ca0132_spec *spec = codec->spec;
6064         int sel = ucontrol->value.enumerated.item[0];
6065         unsigned int items = SPEAKER_CHANNEL_CFG_COUNT;
6066
6067         if (sel >= items)
6068                 return 0;
6069
6070         codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n",
6071                     sel, speaker_channel_cfgs[sel].name);
6072
6073         spec->channel_cfg_val = sel;
6074
6075         if (spec->out_enum_val == SPEAKER_OUT)
6076                 ca0132_alt_select_out(codec);
6077
6078         return 1;
6079 }
6080
6081 /*
6082  * Smart Volume output setting control. Three different settings, Normal,
6083  * which takes the value from the smart volume slider. The two others, loud
6084  * and night, disregard the slider value and have uneditable values.
6085  */
6086 #define NUM_OF_SVM_SETTINGS 3
6087 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
6088
6089 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
6090                                  struct snd_ctl_elem_info *uinfo)
6091 {
6092         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6093         uinfo->count = 1;
6094         uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
6095         if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
6096                 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
6097         strcpy(uinfo->value.enumerated.name,
6098                         out_svm_set_enum_str[uinfo->value.enumerated.item]);
6099         return 0;
6100 }
6101
6102 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
6103                                 struct snd_ctl_elem_value *ucontrol)
6104 {
6105         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6106         struct ca0132_spec *spec = codec->spec;
6107
6108         ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
6109         return 0;
6110 }
6111
6112 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
6113                                 struct snd_ctl_elem_value *ucontrol)
6114 {
6115         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6116         struct ca0132_spec *spec = codec->spec;
6117         int sel = ucontrol->value.enumerated.item[0];
6118         unsigned int items = NUM_OF_SVM_SETTINGS;
6119         unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
6120         unsigned int tmp;
6121
6122         if (sel >= items)
6123                 return 0;
6124
6125         codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
6126                     sel, out_svm_set_enum_str[sel]);
6127
6128         spec->smart_volume_setting = sel;
6129
6130         switch (sel) {
6131         case 0:
6132                 tmp = FLOAT_ZERO;
6133                 break;
6134         case 1:
6135                 tmp = FLOAT_ONE;
6136                 break;
6137         case 2:
6138                 tmp = FLOAT_TWO;
6139                 break;
6140         default:
6141                 tmp = FLOAT_ZERO;
6142                 break;
6143         }
6144         /* Req 2 is the Smart Volume Setting req. */
6145         dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6146                         ca0132_effects[idx].reqs[2], tmp);
6147         return 1;
6148 }
6149
6150 /* Sound Blaster Z EQ preset controls */
6151 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
6152                                  struct snd_ctl_elem_info *uinfo)
6153 {
6154         unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
6155
6156         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6157         uinfo->count = 1;
6158         uinfo->value.enumerated.items = items;
6159         if (uinfo->value.enumerated.item >= items)
6160                 uinfo->value.enumerated.item = items - 1;
6161         strcpy(uinfo->value.enumerated.name,
6162                 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
6163         return 0;
6164 }
6165
6166 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
6167                                 struct snd_ctl_elem_value *ucontrol)
6168 {
6169         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6170         struct ca0132_spec *spec = codec->spec;
6171
6172         ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
6173         return 0;
6174 }
6175
6176 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
6177                                 struct snd_ctl_elem_value *ucontrol)
6178 {
6179         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6180         struct ca0132_spec *spec = codec->spec;
6181         int i, err = 0;
6182         int sel = ucontrol->value.enumerated.item[0];
6183         unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
6184
6185         if (sel >= items)
6186                 return 0;
6187
6188         codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
6189                         ca0132_alt_eq_presets[sel].name);
6190         /*
6191          * Idx 0 is default.
6192          * Default needs to qualify with CrystalVoice state.
6193          */
6194         for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
6195                 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
6196                                 ca0132_alt_eq_enum.reqs[i],
6197                                 ca0132_alt_eq_presets[sel].vals[i]);
6198                 if (err < 0)
6199                         break;
6200         }
6201
6202         if (err >= 0)
6203                 spec->eq_preset_val = sel;
6204
6205         return 1;
6206 }
6207
6208 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
6209                                  struct snd_ctl_elem_info *uinfo)
6210 {
6211         unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
6212
6213         uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6214         uinfo->count = 1;
6215         uinfo->value.enumerated.items = items;
6216         if (uinfo->value.enumerated.item >= items)
6217                 uinfo->value.enumerated.item = items - 1;
6218         strcpy(uinfo->value.enumerated.name,
6219                ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
6220         return 0;
6221 }
6222
6223 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
6224                                 struct snd_ctl_elem_value *ucontrol)
6225 {
6226         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6227         struct ca0132_spec *spec = codec->spec;
6228
6229         ucontrol->value.enumerated.item[0] = spec->voicefx_val;
6230         return 0;
6231 }
6232
6233 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
6234                                 struct snd_ctl_elem_value *ucontrol)
6235 {
6236         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6237         struct ca0132_spec *spec = codec->spec;
6238         int i, err = 0;
6239         int sel = ucontrol->value.enumerated.item[0];
6240
6241         if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
6242                 return 0;
6243
6244         codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
6245                     sel, ca0132_voicefx_presets[sel].name);
6246
6247         /*
6248          * Idx 0 is default.
6249          * Default needs to qualify with CrystalVoice state.
6250          */
6251         for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
6252                 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
6253                                 ca0132_voicefx.reqs[i],
6254                                 ca0132_voicefx_presets[sel].vals[i]);
6255                 if (err < 0)
6256                         break;
6257         }
6258
6259         if (err >= 0) {
6260                 spec->voicefx_val = sel;
6261                 /* enable voice fx */
6262                 ca0132_voicefx_set(codec, (sel ? 1 : 0));
6263         }
6264
6265         return 1;
6266 }
6267
6268 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
6269                                 struct snd_ctl_elem_value *ucontrol)
6270 {
6271         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6272         struct ca0132_spec *spec = codec->spec;
6273         hda_nid_t nid = get_amp_nid(kcontrol);
6274         int ch = get_amp_channels(kcontrol);
6275         long *valp = ucontrol->value.integer.value;
6276
6277         /* vnode */
6278         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
6279                 if (ch & 1) {
6280                         *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
6281                         valp++;
6282                 }
6283                 if (ch & 2) {
6284                         *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
6285                         valp++;
6286                 }
6287                 return 0;
6288         }
6289
6290         /* effects, include PE and CrystalVoice */
6291         if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
6292                 *valp = spec->effects_switch[nid - EFFECT_START_NID];
6293                 return 0;
6294         }
6295
6296         /* mic boost */
6297         if (nid == spec->input_pins[0]) {
6298                 *valp = spec->cur_mic_boost;
6299                 return 0;
6300         }
6301
6302         if (nid == ZXR_HEADPHONE_GAIN) {
6303                 *valp = spec->zxr_gain_set;
6304                 return 0;
6305         }
6306
6307         if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) {
6308                 *valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT];
6309                 return 0;
6310         }
6311
6312         if (nid == BASS_REDIRECTION) {
6313                 *valp = spec->bass_redirection_val;
6314                 return 0;
6315         }
6316
6317         return 0;
6318 }
6319
6320 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
6321                              struct snd_ctl_elem_value *ucontrol)
6322 {
6323         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6324         struct ca0132_spec *spec = codec->spec;
6325         hda_nid_t nid = get_amp_nid(kcontrol);
6326         int ch = get_amp_channels(kcontrol);
6327         long *valp = ucontrol->value.integer.value;
6328         int changed = 1;
6329
6330         codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
6331                     nid, *valp);
6332
6333         snd_hda_power_up(codec);
6334         /* vnode */
6335         if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
6336                 if (ch & 1) {
6337                         spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
6338                         valp++;
6339                 }
6340                 if (ch & 2) {
6341                         spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
6342                         valp++;
6343                 }
6344                 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
6345                 goto exit;
6346         }
6347
6348         /* PE */
6349         if (nid == PLAY_ENHANCEMENT) {
6350                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6351                 changed = ca0132_pe_switch_set(codec);
6352                 goto exit;
6353         }
6354
6355         /* CrystalVoice */
6356         if (nid == CRYSTAL_VOICE) {
6357                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6358                 changed = ca0132_cvoice_switch_set(codec);
6359                 goto exit;
6360         }
6361
6362         /* out and in effects */
6363         if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
6364             ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
6365                 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6366                 changed = ca0132_effects_set(codec, nid, *valp);
6367                 goto exit;
6368         }
6369
6370         /* mic boost */
6371         if (nid == spec->input_pins[0]) {
6372                 spec->cur_mic_boost = *valp;
6373                 if (ca0132_use_alt_functions(spec)) {
6374                         if (spec->in_enum_val != REAR_LINE_IN)
6375                                 changed = ca0132_mic_boost_set(codec, *valp);
6376                 } else {
6377                         /* Mic boost does not apply to Digital Mic */
6378                         if (spec->cur_mic_type != DIGITAL_MIC)
6379                                 changed = ca0132_mic_boost_set(codec, *valp);
6380                 }
6381
6382                 goto exit;
6383         }
6384
6385         if (nid == ZXR_HEADPHONE_GAIN) {
6386                 spec->zxr_gain_set = *valp;
6387                 if (spec->cur_out_type == HEADPHONE_OUT)
6388                         changed = zxr_headphone_gain_set(codec, *valp);
6389                 else
6390                         changed = 0;
6391
6392                 goto exit;
6393         }
6394
6395         if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) {
6396                 spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp;
6397                 if (spec->cur_out_type == SPEAKER_OUT)
6398                         ca0132_alt_set_full_range_speaker(codec);
6399
6400                 changed = 0;
6401         }
6402
6403         if (nid == BASS_REDIRECTION) {
6404                 spec->bass_redirection_val = *valp;
6405                 if (spec->cur_out_type == SPEAKER_OUT)
6406                         ca0132_alt_surround_set_bass_redirection(codec, *valp);
6407
6408                 changed = 0;
6409         }
6410
6411 exit:
6412         snd_hda_power_down(codec);
6413         return changed;
6414 }
6415
6416 /*
6417  * Volume related
6418  */
6419 /*
6420  * Sets the internal DSP decibel level to match the DAC for output, and the
6421  * ADC for input. Currently only the SBZ sets dsp capture volume level, and
6422  * all alternative codecs set DSP playback volume.
6423  */
6424 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
6425 {
6426         struct ca0132_spec *spec = codec->spec;
6427         unsigned int dsp_dir;
6428         unsigned int lookup_val;
6429
6430         if (nid == VNID_SPK)
6431                 dsp_dir = DSP_VOL_OUT;
6432         else
6433                 dsp_dir = DSP_VOL_IN;
6434
6435         lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
6436
6437         dspio_set_uint_param(codec,
6438                 ca0132_alt_vol_ctls[dsp_dir].mid,
6439                 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
6440                 float_vol_db_lookup[lookup_val]);
6441
6442         lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
6443
6444         dspio_set_uint_param(codec,
6445                 ca0132_alt_vol_ctls[dsp_dir].mid,
6446                 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
6447                 float_vol_db_lookup[lookup_val]);
6448
6449         dspio_set_uint_param(codec,
6450                 ca0132_alt_vol_ctls[dsp_dir].mid,
6451                 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
6452 }
6453
6454 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
6455                               struct snd_ctl_elem_info *uinfo)
6456 {
6457         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6458         struct ca0132_spec *spec = codec->spec;
6459         hda_nid_t nid = get_amp_nid(kcontrol);
6460         int ch = get_amp_channels(kcontrol);
6461         int dir = get_amp_direction(kcontrol);
6462         unsigned long pval;
6463         int err;
6464
6465         switch (nid) {
6466         case VNID_SPK:
6467                 /* follow shared_out info */
6468                 nid = spec->shared_out_nid;
6469                 mutex_lock(&codec->control_mutex);
6470                 pval = kcontrol->private_value;
6471                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6472                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6473                 kcontrol->private_value = pval;
6474                 mutex_unlock(&codec->control_mutex);
6475                 break;
6476         case VNID_MIC:
6477                 /* follow shared_mic info */
6478                 nid = spec->shared_mic_nid;
6479                 mutex_lock(&codec->control_mutex);
6480                 pval = kcontrol->private_value;
6481                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6482                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6483                 kcontrol->private_value = pval;
6484                 mutex_unlock(&codec->control_mutex);
6485                 break;
6486         default:
6487                 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6488         }
6489         return err;
6490 }
6491
6492 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
6493                                 struct snd_ctl_elem_value *ucontrol)
6494 {
6495         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6496         struct ca0132_spec *spec = codec->spec;
6497         hda_nid_t nid = get_amp_nid(kcontrol);
6498         int ch = get_amp_channels(kcontrol);
6499         long *valp = ucontrol->value.integer.value;
6500
6501         /* store the left and right volume */
6502         if (ch & 1) {
6503                 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
6504                 valp++;
6505         }
6506         if (ch & 2) {
6507                 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
6508                 valp++;
6509         }
6510         return 0;
6511 }
6512
6513 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
6514                                 struct snd_ctl_elem_value *ucontrol)
6515 {
6516         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6517         struct ca0132_spec *spec = codec->spec;
6518         hda_nid_t nid = get_amp_nid(kcontrol);
6519         int ch = get_amp_channels(kcontrol);
6520         long *valp = ucontrol->value.integer.value;
6521         hda_nid_t shared_nid = 0;
6522         bool effective;
6523         int changed = 1;
6524
6525         /* store the left and right volume */
6526         if (ch & 1) {
6527                 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
6528                 valp++;
6529         }
6530         if (ch & 2) {
6531                 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
6532                 valp++;
6533         }
6534
6535         /* if effective conditions, then update hw immediately. */
6536         effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
6537         if (effective) {
6538                 int dir = get_amp_direction(kcontrol);
6539                 unsigned long pval;
6540
6541                 snd_hda_power_up(codec);
6542                 mutex_lock(&codec->control_mutex);
6543                 pval = kcontrol->private_value;
6544                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
6545                                                                 0, dir);
6546                 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6547                 kcontrol->private_value = pval;
6548                 mutex_unlock(&codec->control_mutex);
6549                 snd_hda_power_down(codec);
6550         }
6551
6552         return changed;
6553 }
6554
6555 /*
6556  * This function is the same as the one above, because using an if statement
6557  * inside of the above volume control for the DSP volume would cause too much
6558  * lag. This is a lot more smooth.
6559  */
6560 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
6561                                 struct snd_ctl_elem_value *ucontrol)
6562 {
6563         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6564         struct ca0132_spec *spec = codec->spec;
6565         hda_nid_t nid = get_amp_nid(kcontrol);
6566         int ch = get_amp_channels(kcontrol);
6567         long *valp = ucontrol->value.integer.value;
6568         hda_nid_t vnid = 0;
6569         int changed;
6570
6571         switch (nid) {
6572         case 0x02:
6573                 vnid = VNID_SPK;
6574                 break;
6575         case 0x07:
6576                 vnid = VNID_MIC;
6577                 break;
6578         }
6579
6580         /* store the left and right volume */
6581         if (ch & 1) {
6582                 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
6583                 valp++;
6584         }
6585         if (ch & 2) {
6586                 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
6587                 valp++;
6588         }
6589
6590         snd_hda_power_up(codec);
6591         ca0132_alt_dsp_volume_put(codec, vnid);
6592         mutex_lock(&codec->control_mutex);
6593         changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6594         mutex_unlock(&codec->control_mutex);
6595         snd_hda_power_down(codec);
6596
6597         return changed;
6598 }
6599
6600 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
6601                              unsigned int size, unsigned int __user *tlv)
6602 {
6603         struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6604         struct ca0132_spec *spec = codec->spec;
6605         hda_nid_t nid = get_amp_nid(kcontrol);
6606         int ch = get_amp_channels(kcontrol);
6607         int dir = get_amp_direction(kcontrol);
6608         unsigned long pval;
6609         int err;
6610
6611         switch (nid) {
6612         case VNID_SPK:
6613                 /* follow shared_out tlv */
6614                 nid = spec->shared_out_nid;
6615                 mutex_lock(&codec->control_mutex);
6616                 pval = kcontrol->private_value;
6617                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6618                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6619                 kcontrol->private_value = pval;
6620                 mutex_unlock(&codec->control_mutex);
6621                 break;
6622         case VNID_MIC:
6623                 /* follow shared_mic tlv */
6624                 nid = spec->shared_mic_nid;
6625                 mutex_lock(&codec->control_mutex);
6626                 pval = kcontrol->private_value;
6627                 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6628                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6629                 kcontrol->private_value = pval;
6630                 mutex_unlock(&codec->control_mutex);
6631                 break;
6632         default:
6633                 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6634         }
6635         return err;
6636 }
6637
6638 /* Add volume slider control for effect level */
6639 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
6640                                         const char *pfx, int dir)
6641 {
6642         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6643         int type = dir ? HDA_INPUT : HDA_OUTPUT;
6644         struct snd_kcontrol_new knew =
6645                 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
6646
6647         sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
6648
6649         knew.tlv.c = NULL;
6650
6651         switch (nid) {
6652         case XBASS_XOVER:
6653                 knew.info = ca0132_alt_xbass_xover_slider_info;
6654                 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6655                 knew.put = ca0132_alt_xbass_xover_slider_put;
6656                 break;
6657         default:
6658                 knew.info = ca0132_alt_effect_slider_info;
6659                 knew.get = ca0132_alt_slider_ctl_get;
6660                 knew.put = ca0132_alt_effect_slider_put;
6661                 knew.private_value =
6662                         HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
6663                 break;
6664         }
6665
6666         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6667 }
6668
6669 /*
6670  * Added FX: prefix for the alternative codecs, because otherwise the surround
6671  * effect would conflict with the Surround sound volume control. Also seems more
6672  * clear as to what the switches do. Left alone for others.
6673  */
6674 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
6675                          const char *pfx, int dir)
6676 {
6677         struct ca0132_spec *spec = codec->spec;
6678         char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6679         int type = dir ? HDA_INPUT : HDA_OUTPUT;
6680         struct snd_kcontrol_new knew =
6681                 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
6682         /* If using alt_controls, add FX: prefix. But, don't add FX:
6683          * prefix to OutFX or InFX enable controls.
6684          */
6685         if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID))
6686                 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
6687         else
6688                 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
6689
6690         return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6691 }
6692
6693 static int add_voicefx(struct hda_codec *codec)
6694 {
6695         struct snd_kcontrol_new knew =
6696                 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
6697                                     VOICEFX, 1, 0, HDA_INPUT);
6698         knew.info = ca0132_voicefx_info;
6699         knew.get = ca0132_voicefx_get;
6700         knew.put = ca0132_voicefx_put;
6701         return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
6702 }
6703
6704 /* Create the EQ Preset control */
6705 static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
6706 {
6707         struct snd_kcontrol_new knew =
6708                 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
6709                                     EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
6710         knew.info = ca0132_alt_eq_preset_info;
6711         knew.get = ca0132_alt_eq_preset_get;
6712         knew.put = ca0132_alt_eq_preset_put;
6713         return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
6714                                 snd_ctl_new1(&knew, codec));
6715 }
6716
6717 /*
6718  * Add enumerated control for the three different settings of the smart volume
6719  * output effect. Normal just uses the slider value, and loud and night are
6720  * their own things that ignore that value.
6721  */
6722 static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
6723 {
6724         struct snd_kcontrol_new knew =
6725                 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
6726                                     SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
6727         knew.info = ca0132_alt_svm_setting_info;
6728         knew.get = ca0132_alt_svm_setting_get;
6729         knew.put = ca0132_alt_svm_setting_put;
6730         return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
6731                                 snd_ctl_new1(&knew, codec));
6732
6733 }
6734
6735 /*
6736  * Create an Output Select enumerated control for codecs with surround
6737  * out capabilities.
6738  */
6739 static int ca0132_alt_add_output_enum(struct hda_codec *codec)
6740 {
6741         struct snd_kcontrol_new knew =
6742                 HDA_CODEC_MUTE_MONO("Output Select",
6743                                     OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
6744         knew.info = ca0132_alt_output_select_get_info;
6745         knew.get = ca0132_alt_output_select_get;
6746         knew.put = ca0132_alt_output_select_put;
6747         return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
6748                                 snd_ctl_new1(&knew, codec));
6749 }
6750
6751 /*
6752  * Add a control for selecting channel count on speaker output. Setting this
6753  * allows the DSP to do bass redirection and channel upmixing on surround
6754  * configurations.
6755  */
6756 static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec)
6757 {
6758         struct snd_kcontrol_new knew =
6759                 HDA_CODEC_MUTE_MONO("Surround Channel Config",
6760                                     SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT);
6761         knew.info = ca0132_alt_speaker_channel_cfg_get_info;
6762         knew.get = ca0132_alt_speaker_channel_cfg_get;
6763         knew.put = ca0132_alt_speaker_channel_cfg_put;
6764         return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM,
6765                                 snd_ctl_new1(&knew, codec));
6766 }
6767
6768 /*
6769  * Full range front stereo and rear surround switches. When these are set to
6770  * full range, the lower frequencies from these channels are no longer
6771  * redirected to the LFE channel.
6772  */
6773 static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec)
6774 {
6775         struct snd_kcontrol_new knew =
6776                 CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers",
6777                                     SPEAKER_FULL_RANGE_FRONT, 1, HDA_OUTPUT);
6778
6779         return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT,
6780                                 snd_ctl_new1(&knew, codec));
6781 }
6782
6783 static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec)
6784 {
6785         struct snd_kcontrol_new knew =
6786                 CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers",
6787                                     SPEAKER_FULL_RANGE_REAR, 1, HDA_OUTPUT);
6788
6789         return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR,
6790                                 snd_ctl_new1(&knew, codec));
6791 }
6792
6793 /*
6794  * Bass redirection redirects audio below the crossover frequency to the LFE
6795  * channel on speakers that are set as not being full-range. On configurations
6796  * without an LFE channel, it does nothing. Bass redirection seems to be the
6797  * replacement for X-Bass on configurations with an LFE channel.
6798  */
6799 static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec)
6800 {
6801         const char *namestr = "Bass Redirection Crossover";
6802         struct snd_kcontrol_new knew =
6803                 HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0,
6804                                 HDA_OUTPUT);
6805
6806         knew.tlv.c = NULL;
6807         knew.info = ca0132_alt_xbass_xover_slider_info;
6808         knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6809         knew.put = ca0132_alt_xbass_xover_slider_put;
6810
6811         return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER,
6812                         snd_ctl_new1(&knew, codec));
6813 }
6814
6815 static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec)
6816 {
6817         const char *namestr = "Bass Redirection";
6818         struct snd_kcontrol_new knew =
6819                 CA0132_CODEC_MUTE_MONO(namestr, BASS_REDIRECTION, 1,
6820                                 HDA_OUTPUT);
6821
6822         return snd_hda_ctl_add(codec, BASS_REDIRECTION,
6823                         snd_ctl_new1(&knew, codec));
6824 }
6825
6826 /*
6827  * Create an Input Source enumerated control for the alternate ca0132 codecs
6828  * because the front microphone has no auto-detect, and Line-in has to be set
6829  * somehow.
6830  */
6831 static int ca0132_alt_add_input_enum(struct hda_codec *codec)
6832 {
6833         struct snd_kcontrol_new knew =
6834                 HDA_CODEC_MUTE_MONO("Input Source",
6835                                     INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
6836         knew.info = ca0132_alt_input_source_info;
6837         knew.get = ca0132_alt_input_source_get;
6838         knew.put = ca0132_alt_input_source_put;
6839         return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
6840                                 snd_ctl_new1(&knew, codec));
6841 }
6842
6843 /*
6844  * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
6845  * more control than the original mic boost, which is either full 30dB or off.
6846  */
6847 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
6848 {
6849         struct snd_kcontrol_new knew =
6850                 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
6851                                     MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
6852         knew.info = ca0132_alt_mic_boost_info;
6853         knew.get = ca0132_alt_mic_boost_get;
6854         knew.put = ca0132_alt_mic_boost_put;
6855         return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
6856                                 snd_ctl_new1(&knew, codec));
6857
6858 }
6859
6860 /*
6861  * Add headphone gain enumerated control for the AE-5. This switches between
6862  * three modes, low, medium, and high. When non-headphone outputs are selected,
6863  * it is automatically set to high. This is the same behavior as Windows.
6864  */
6865 static int ae5_add_headphone_gain_enum(struct hda_codec *codec)
6866 {
6867         struct snd_kcontrol_new knew =
6868                 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain",
6869                                     AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT);
6870         knew.info = ae5_headphone_gain_info;
6871         knew.get = ae5_headphone_gain_get;
6872         knew.put = ae5_headphone_gain_put;
6873         return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM,
6874                                 snd_ctl_new1(&knew, codec));
6875 }
6876
6877 /*
6878  * Add sound filter enumerated control for the AE-5. This adds three different
6879  * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've
6880  * read into it, it changes the DAC's interpolation filter.
6881  */
6882 static int ae5_add_sound_filter_enum(struct hda_codec *codec)
6883 {
6884         struct snd_kcontrol_new knew =
6885                 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter",
6886                                     AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT);
6887         knew.info = ae5_sound_filter_info;
6888         knew.get = ae5_sound_filter_get;
6889         knew.put = ae5_sound_filter_put;
6890         return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM,
6891                                 snd_ctl_new1(&knew, codec));
6892 }
6893
6894 static int zxr_add_headphone_gain_switch(struct hda_codec *codec)
6895 {
6896         struct snd_kcontrol_new knew =
6897                 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain",
6898                                     ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT);
6899
6900         return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN,
6901                                 snd_ctl_new1(&knew, codec));
6902 }
6903
6904 /*
6905  * Need to create follower controls for the alternate codecs that have surround
6906  * capabilities.
6907  */
6908 static const char * const ca0132_alt_follower_pfxs[] = {
6909         "Front", "Surround", "Center", "LFE", NULL,
6910 };
6911
6912 /*
6913  * Also need special channel map, because the default one is incorrect.
6914  * I think this has to do with the pin for rear surround being 0x11,
6915  * and the center/lfe being 0x10. Usually the pin order is the opposite.
6916  */
6917 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
6918         { .channels = 2,
6919           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
6920         { .channels = 4,
6921           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6922                    SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6923         { .channels = 6,
6924           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6925                    SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
6926                    SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6927         { }
6928 };
6929
6930 /* Add the correct chmap for streams with 6 channels. */
6931 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
6932 {
6933         int err = 0;
6934         struct hda_pcm *pcm;
6935
6936         list_for_each_entry(pcm, &codec->pcm_list_head, list) {
6937                 struct hda_pcm_stream *hinfo =
6938                         &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
6939                 struct snd_pcm_chmap *chmap;
6940                 const struct snd_pcm_chmap_elem *elem;
6941
6942                 elem = ca0132_alt_chmaps;
6943                 if (hinfo->channels_max == 6) {
6944                         err = snd_pcm_add_chmap_ctls(pcm->pcm,
6945                                         SNDRV_PCM_STREAM_PLAYBACK,
6946                                         elem, hinfo->channels_max, 0, &chmap);
6947                         if (err < 0)
6948                                 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
6949                 }
6950         }
6951 }
6952
6953 /*
6954  * When changing Node IDs for Mixer Controls below, make sure to update
6955  * Node IDs in ca0132_config() as well.
6956  */
6957 static const struct snd_kcontrol_new ca0132_mixer[] = {
6958         CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
6959         CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
6960         CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6961         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6962         HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
6963         HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
6964         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6965         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6966         CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
6967                                0x12, 1, HDA_INPUT),
6968         CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
6969                                VNID_HP_SEL, 1, HDA_OUTPUT),
6970         CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
6971                                VNID_AMIC1_SEL, 1, HDA_INPUT),
6972         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6973                                VNID_HP_ASEL, 1, HDA_OUTPUT),
6974         CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
6975                                VNID_AMIC1_ASEL, 1, HDA_INPUT),
6976         { } /* end */
6977 };
6978
6979 /*
6980  * Desktop specific control mixer. Removes auto-detect for mic, and adds
6981  * surround controls. Also sets both the Front Playback and Capture Volume
6982  * controls to alt so they set the DSP's decibel level.
6983  */
6984 static const struct snd_kcontrol_new desktop_mixer[] = {
6985         CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6986         CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
6987         HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6988         HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6989         HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6990         HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6991         HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6992         HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
6993         CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
6994         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6995         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6996         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6997         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6998                                 VNID_HP_ASEL, 1, HDA_OUTPUT),
6999         { } /* end */
7000 };
7001
7002 /*
7003  * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
7004  * because it doesn't set decibel levels for the DSP for capture.
7005  */
7006 static const struct snd_kcontrol_new r3di_mixer[] = {
7007         CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
7008         CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
7009         HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
7010         HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
7011         HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
7012         HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
7013         HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
7014         HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
7015         CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
7016         CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
7017         HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
7018         HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
7019         CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
7020                                 VNID_HP_ASEL, 1, HDA_OUTPUT),
7021         { } /* end */
7022 };
7023
7024 static int ca0132_build_controls(struct hda_codec *codec)
7025 {
7026         struct ca0132_spec *spec = codec->spec;
7027         int i, num_fx, num_sliders;
7028         int err = 0;
7029
7030         /* Add Mixer controls */
7031         for (i = 0; i < spec->num_mixers; i++) {
7032                 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
7033                 if (err < 0)
7034                         return err;
7035         }
7036         /* Setup vmaster with surround followers for desktop ca0132 devices */
7037         if (ca0132_use_alt_functions(spec)) {
7038                 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
7039                                         spec->tlv);
7040                 snd_hda_add_vmaster(codec, "Master Playback Volume",
7041                                         spec->tlv, ca0132_alt_follower_pfxs,
7042                                         "Playback Volume", 0);
7043                 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
7044                                             NULL, ca0132_alt_follower_pfxs,
7045                                             "Playback Switch",
7046                                             true, 0, &spec->vmaster_mute.sw_kctl);
7047                 if (err < 0)
7048                         return err;
7049         }
7050
7051         /* Add in and out effects controls.
7052          * VoiceFX, PE and CrystalVoice are added separately.
7053          */
7054         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
7055         for (i = 0; i < num_fx; i++) {
7056                 /* Desktop cards break if Echo Cancellation is used. */
7057                 if (ca0132_use_pci_mmio(spec)) {
7058                         if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
7059                                                 OUT_EFFECTS_COUNT))
7060                                 continue;
7061                 }
7062
7063                 err = add_fx_switch(codec, ca0132_effects[i].nid,
7064                                     ca0132_effects[i].name,
7065                                     ca0132_effects[i].direct);
7066                 if (err < 0)
7067                         return err;
7068         }
7069         /*
7070          * If codec has use_alt_controls set to true, add effect level sliders,
7071          * EQ presets, and Smart Volume presets. Also, change names to add FX
7072          * prefix, and change PlayEnhancement and CrystalVoice to match.
7073          */
7074         if (ca0132_use_alt_controls(spec)) {
7075                 err = ca0132_alt_add_svm_enum(codec);
7076                 if (err < 0)
7077                         return err;
7078
7079                 err = add_ca0132_alt_eq_presets(codec);
7080                 if (err < 0)
7081                         return err;
7082
7083                 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
7084                                         "Enable OutFX", 0);
7085                 if (err < 0)
7086                         return err;
7087
7088                 err = add_fx_switch(codec, CRYSTAL_VOICE,
7089                                         "Enable InFX", 1);
7090                 if (err < 0)
7091                         return err;
7092
7093                 num_sliders = OUT_EFFECTS_COUNT - 1;
7094                 for (i = 0; i < num_sliders; i++) {
7095                         err = ca0132_alt_add_effect_slider(codec,
7096                                             ca0132_effects[i].nid,
7097                                             ca0132_effects[i].name,
7098                                             ca0132_effects[i].direct);
7099                         if (err < 0)
7100                                 return err;
7101                 }
7102
7103                 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
7104                                         "X-Bass Crossover", EFX_DIR_OUT);
7105
7106                 if (err < 0)
7107                         return err;
7108         } else {
7109                 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
7110                                         "PlayEnhancement", 0);
7111                 if (err < 0)
7112                         return err;
7113
7114                 err = add_fx_switch(codec, CRYSTAL_VOICE,
7115                                         "CrystalVoice", 1);
7116                 if (err < 0)
7117                         return err;
7118         }
7119         err = add_voicefx(codec);
7120         if (err < 0)
7121                 return err;
7122
7123         /*
7124          * If the codec uses alt_functions, you need the enumerated controls
7125          * to select the new outputs and inputs, plus add the new mic boost
7126          * setting control.
7127          */
7128         if (ca0132_use_alt_functions(spec)) {
7129                 err = ca0132_alt_add_output_enum(codec);
7130                 if (err < 0)
7131                         return err;
7132                 err = ca0132_alt_add_speaker_channel_cfg_enum(codec);
7133                 if (err < 0)
7134                         return err;
7135                 err = ca0132_alt_add_front_full_range_switch(codec);
7136                 if (err < 0)
7137                         return err;
7138                 err = ca0132_alt_add_rear_full_range_switch(codec);
7139                 if (err < 0)
7140                         return err;
7141                 err = ca0132_alt_add_bass_redirection_crossover(codec);
7142                 if (err < 0)
7143                         return err;
7144                 err = ca0132_alt_add_bass_redirection_switch(codec);
7145                 if (err < 0)
7146                         return err;
7147                 err = ca0132_alt_add_mic_boost_enum(codec);
7148                 if (err < 0)
7149                         return err;
7150                 /*
7151                  * ZxR only has microphone input, there is no front panel
7152                  * header on the card, and aux-in is handled by the DBPro board.
7153                  */
7154                 if (ca0132_quirk(spec) != QUIRK_ZXR) {
7155                         err = ca0132_alt_add_input_enum(codec);
7156                         if (err < 0)
7157                                 return err;
7158                 }
7159         }
7160
7161         switch (ca0132_quirk(spec)) {
7162         case QUIRK_AE5:
7163         case QUIRK_AE7:
7164                 err = ae5_add_headphone_gain_enum(codec);
7165                 if (err < 0)
7166                         return err;
7167                 err = ae5_add_sound_filter_enum(codec);
7168                 if (err < 0)
7169                         return err;
7170                 break;
7171         case QUIRK_ZXR:
7172                 err = zxr_add_headphone_gain_switch(codec);
7173                 if (err < 0)
7174                         return err;
7175                 break;
7176         default:
7177                 break;
7178         }
7179
7180 #ifdef ENABLE_TUNING_CONTROLS
7181         add_tuning_ctls(codec);
7182 #endif
7183
7184         err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
7185         if (err < 0)
7186                 return err;
7187
7188         if (spec->dig_out) {
7189                 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7190                                                     spec->dig_out);
7191                 if (err < 0)
7192                         return err;
7193                 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
7194                 if (err < 0)
7195                         return err;
7196                 /* spec->multiout.share_spdif = 1; */
7197         }
7198
7199         if (spec->dig_in) {
7200                 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7201                 if (err < 0)
7202                         return err;
7203         }
7204
7205         if (ca0132_use_alt_functions(spec))
7206                 ca0132_alt_add_chmap_ctls(codec);
7207
7208         return 0;
7209 }
7210
7211 static int dbpro_build_controls(struct hda_codec *codec)
7212 {
7213         struct ca0132_spec *spec = codec->spec;
7214         int err = 0;
7215
7216         if (spec->dig_out) {
7217                 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7218                                 spec->dig_out);
7219                 if (err < 0)
7220                         return err;
7221         }
7222
7223         if (spec->dig_in) {
7224                 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7225                 if (err < 0)
7226                         return err;
7227         }
7228
7229         return 0;
7230 }
7231
7232 /*
7233  * PCM
7234  */
7235 static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
7236         .substreams = 1,
7237         .channels_min = 2,
7238         .channels_max = 6,
7239         .ops = {
7240                 .prepare = ca0132_playback_pcm_prepare,
7241                 .cleanup = ca0132_playback_pcm_cleanup,
7242                 .get_delay = ca0132_playback_pcm_delay,
7243         },
7244 };
7245
7246 static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
7247         .substreams = 1,
7248         .channels_min = 2,
7249         .channels_max = 2,
7250         .ops = {
7251                 .prepare = ca0132_capture_pcm_prepare,
7252                 .cleanup = ca0132_capture_pcm_cleanup,
7253                 .get_delay = ca0132_capture_pcm_delay,
7254         },
7255 };
7256
7257 static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
7258         .substreams = 1,
7259         .channels_min = 2,
7260         .channels_max = 2,
7261         .ops = {
7262                 .open = ca0132_dig_playback_pcm_open,
7263                 .close = ca0132_dig_playback_pcm_close,
7264                 .prepare = ca0132_dig_playback_pcm_prepare,
7265                 .cleanup = ca0132_dig_playback_pcm_cleanup
7266         },
7267 };
7268
7269 static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
7270         .substreams = 1,
7271         .channels_min = 2,
7272         .channels_max = 2,
7273 };
7274
7275 static int ca0132_build_pcms(struct hda_codec *codec)
7276 {
7277         struct ca0132_spec *spec = codec->spec;
7278         struct hda_pcm *info;
7279
7280         info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
7281         if (!info)
7282                 return -ENOMEM;
7283         if (ca0132_use_alt_functions(spec)) {
7284                 info->own_chmap = true;
7285                 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
7286                         = ca0132_alt_chmaps;
7287         }
7288         info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
7289         info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
7290         info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
7291                 spec->multiout.max_channels;
7292         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7293         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7294         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7295
7296         /* With the DSP enabled, desktops don't use this ADC. */
7297         if (!ca0132_use_alt_functions(spec)) {
7298                 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
7299                 if (!info)
7300                         return -ENOMEM;
7301                 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7302                         ca0132_pcm_analog_capture;
7303                 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7304                 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
7305         }
7306
7307         info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
7308         if (!info)
7309                 return -ENOMEM;
7310         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7311         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7312         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
7313
7314         if (!spec->dig_out && !spec->dig_in)
7315                 return 0;
7316
7317         info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7318         if (!info)
7319                 return -ENOMEM;
7320         info->pcm_type = HDA_PCM_TYPE_SPDIF;
7321         if (spec->dig_out) {
7322                 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7323                         ca0132_pcm_digital_playback;
7324                 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7325         }
7326         if (spec->dig_in) {
7327                 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7328                         ca0132_pcm_digital_capture;
7329                 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7330         }
7331
7332         return 0;
7333 }
7334
7335 static int dbpro_build_pcms(struct hda_codec *codec)
7336 {
7337         struct ca0132_spec *spec = codec->spec;
7338         struct hda_pcm *info;
7339
7340         info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog");
7341         if (!info)
7342                 return -ENOMEM;
7343         info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7344         info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7345         info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7346
7347
7348         if (!spec->dig_out && !spec->dig_in)
7349                 return 0;
7350
7351         info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7352         if (!info)
7353                 return -ENOMEM;
7354         info->pcm_type = HDA_PCM_TYPE_SPDIF;
7355         if (spec->dig_out) {
7356                 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7357                         ca0132_pcm_digital_playback;
7358                 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7359         }
7360         if (spec->dig_in) {
7361                 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7362                         ca0132_pcm_digital_capture;
7363                 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7364         }
7365
7366         return 0;
7367 }
7368
7369 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
7370 {
7371         if (pin) {
7372                 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
7373                 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
7374                         snd_hda_codec_write(codec, pin, 0,
7375                                             AC_VERB_SET_AMP_GAIN_MUTE,
7376                                             AMP_OUT_UNMUTE);
7377         }
7378         if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
7379                 snd_hda_codec_write(codec, dac, 0,
7380                                     AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
7381 }
7382
7383 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
7384 {
7385         if (pin) {
7386                 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
7387                 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
7388                         snd_hda_codec_write(codec, pin, 0,
7389                                             AC_VERB_SET_AMP_GAIN_MUTE,
7390                                             AMP_IN_UNMUTE(0));
7391         }
7392         if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
7393                 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
7394                                     AMP_IN_UNMUTE(0));
7395
7396                 /* init to 0 dB and unmute. */
7397                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7398                                          HDA_AMP_VOLMASK, 0x5a);
7399                 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7400                                          HDA_AMP_MUTE, 0);
7401         }
7402 }
7403
7404 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
7405 {
7406         unsigned int caps;
7407
7408         caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
7409                                   AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
7410         snd_hda_override_amp_caps(codec, nid, dir, caps);
7411 }
7412
7413 /*
7414  * Switch between Digital built-in mic and analog mic.
7415  */
7416 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
7417 {
7418         struct ca0132_spec *spec = codec->spec;
7419         unsigned int tmp;
7420         u8 val;
7421         unsigned int oldval;
7422
7423         codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
7424
7425         oldval = stop_mic1(codec);
7426         ca0132_set_vipsource(codec, 0);
7427         if (enable) {
7428                 /* set DMic input as 2-ch */
7429                 tmp = FLOAT_TWO;
7430                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7431
7432                 val = spec->dmic_ctl;
7433                 val |= 0x80;
7434                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7435                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
7436
7437                 if (!(spec->dmic_ctl & 0x20))
7438                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
7439         } else {
7440                 /* set AMic input as mono */
7441                 tmp = FLOAT_ONE;
7442                 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7443
7444                 val = spec->dmic_ctl;
7445                 /* clear bit7 and bit5 to disable dmic */
7446                 val &= 0x5f;
7447                 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7448                                     VENDOR_CHIPIO_DMIC_CTL_SET, val);
7449
7450                 if (!(spec->dmic_ctl & 0x20))
7451                         chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
7452         }
7453         ca0132_set_vipsource(codec, 1);
7454         resume_mic1(codec, oldval);
7455 }
7456
7457 /*
7458  * Initialization for Digital Mic.
7459  */
7460 static void ca0132_init_dmic(struct hda_codec *codec)
7461 {
7462         struct ca0132_spec *spec = codec->spec;
7463         u8 val;
7464
7465         /* Setup Digital Mic here, but don't enable.
7466          * Enable based on jack detect.
7467          */
7468
7469         /* MCLK uses MPIO1, set to enable.
7470          * Bit 2-0: MPIO select
7471          * Bit   3: set to disable
7472          * Bit 7-4: reserved
7473          */
7474         val = 0x01;
7475         snd_hda_codec_write(codec, spec->input_pins[0], 0,
7476                             VENDOR_CHIPIO_DMIC_MCLK_SET, val);
7477
7478         /* Data1 uses MPIO3. Data2 not use
7479          * Bit 2-0: Data1 MPIO select
7480          * Bit   3: set disable Data1
7481          * Bit 6-4: Data2 MPIO select
7482          * Bit   7: set disable Data2
7483          */
7484         val = 0x83;
7485         snd_hda_codec_write(codec, spec->input_pins[0], 0,
7486                             VENDOR_CHIPIO_DMIC_PIN_SET, val);
7487
7488         /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
7489          * Bit 3-0: Channel mask
7490          * Bit   4: set for 48KHz, clear for 32KHz
7491          * Bit   5: mode
7492          * Bit   6: set to select Data2, clear for Data1
7493          * Bit   7: set to enable DMic, clear for AMic
7494          */
7495         if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4)
7496                 val = 0x33;
7497         else
7498                 val = 0x23;
7499         /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
7500         spec->dmic_ctl = val;
7501         snd_hda_codec_write(codec, spec->input_pins[0], 0,
7502                             VENDOR_CHIPIO_DMIC_CTL_SET, val);
7503 }
7504
7505 /*
7506  * Initialization for Analog Mic 2
7507  */
7508 static void ca0132_init_analog_mic2(struct hda_codec *codec)
7509 {
7510         struct ca0132_spec *spec = codec->spec;
7511
7512         mutex_lock(&spec->chipio_mutex);
7513
7514         chipio_8051_write_exram_no_mutex(codec, 0x1920, 0x00);
7515         chipio_8051_write_exram_no_mutex(codec, 0x192d, 0x00);
7516
7517         mutex_unlock(&spec->chipio_mutex);
7518 }
7519
7520 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
7521 {
7522         struct ca0132_spec *spec = codec->spec;
7523         int i;
7524
7525         codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7526         snd_hda_codec_update_widgets(codec);
7527
7528         for (i = 0; i < spec->multiout.num_dacs; i++)
7529                 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
7530
7531         for (i = 0; i < spec->num_outputs; i++)
7532                 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
7533
7534         for (i = 0; i < spec->num_inputs; i++) {
7535                 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
7536                 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
7537         }
7538 }
7539
7540
7541 /* If there is an active channel for some reason, find it and free it. */
7542 static void ca0132_alt_free_active_dma_channels(struct hda_codec *codec)
7543 {
7544         unsigned int i, tmp;
7545         int status;
7546
7547         /* Read active DSPDMAC channel register. */
7548         status = chipio_read(codec, DSPDMAC_CHNLSTART_MODULE_OFFSET, &tmp);
7549         if (status >= 0) {
7550                 /* AND against 0xfff to get the active channel bits. */
7551                 tmp = tmp & 0xfff;
7552
7553                 /* If there are no active channels, nothing to free. */
7554                 if (!tmp)
7555                         return;
7556         } else {
7557                 codec_dbg(codec, "%s: Failed to read active DSP DMA channel register.\n",
7558                                 __func__);
7559                 return;
7560         }
7561
7562         /*
7563          * Check each DSP DMA channel for activity, and if the channel is
7564          * active, free it.
7565          */
7566         for (i = 0; i < DSPDMAC_DMA_CFG_CHANNEL_COUNT; i++) {
7567                 if (dsp_is_dma_active(codec, i)) {
7568                         status = dspio_free_dma_chan(codec, i);
7569                         if (status < 0)
7570                                 codec_dbg(codec, "%s: Failed to free active DSP DMA channel %d.\n",
7571                                                 __func__, i);
7572                 }
7573         }
7574 }
7575
7576 /*
7577  * In the case of CT_EXTENSIONS_ENABLE being set to 1, and the DSP being in
7578  * use, audio is no longer routed directly to the DAC/ADC from the HDA stream.
7579  * Instead, audio is now routed through the DSP's DMA controllers, which
7580  * the DSP is tasked with setting up itself. Through debugging, it seems the
7581  * cause of most of the no-audio on startup issues were due to improperly
7582  * configured DSP DMA channels.
7583  *
7584  * Normally, the DSP configures these the first time an HDA audio stream is
7585  * started post DSP firmware download. That is why creating a 'dummy' stream
7586  * worked in fixing the audio in some cases. This works most of the time, but
7587  * sometimes if a stream is started/stopped before the DSP can setup the DMA
7588  * configuration registers, it ends up in a broken state. Issues can also
7589  * arise if streams are started in an unusual order, i.e the audio output dma
7590  * channel being sandwiched between the mic1 and mic2 dma channels.
7591  *
7592  * The solution to this is to make sure that the DSP has no DMA channels
7593  * in use post DSP firmware download, and then to manually start each default
7594  * DSP stream that uses the DMA channels. These are 0x0c, the audio output
7595  * stream, 0x03, analog mic 1, and 0x04, analog mic 2.
7596  */
7597 static void ca0132_alt_start_dsp_audio_streams(struct hda_codec *codec)
7598 {
7599         static const unsigned int dsp_dma_stream_ids[] = { 0x0c, 0x03, 0x04 };
7600         struct ca0132_spec *spec = codec->spec;
7601         unsigned int i, tmp;
7602
7603         /*
7604          * Check if any of the default streams are active, and if they are,
7605          * stop them.
7606          */
7607         mutex_lock(&spec->chipio_mutex);
7608
7609         for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) {
7610                 chipio_get_stream_control(codec, dsp_dma_stream_ids[i], &tmp);
7611
7612                 if (tmp) {
7613                         chipio_set_stream_control(codec,
7614                                         dsp_dma_stream_ids[i], 0);
7615                 }
7616         }
7617
7618         mutex_unlock(&spec->chipio_mutex);
7619
7620         /*
7621          * If all DSP streams are inactive, there should be no active DSP DMA
7622          * channels. Check and make sure this is the case, and if it isn't,
7623          * free any active channels.
7624          */
7625         ca0132_alt_free_active_dma_channels(codec);
7626
7627         mutex_lock(&spec->chipio_mutex);
7628
7629         /* Make sure stream 0x0c is six channels. */
7630         chipio_set_stream_channels(codec, 0x0c, 6);
7631
7632         for (i = 0; i < ARRAY_SIZE(dsp_dma_stream_ids); i++) {
7633                 chipio_set_stream_control(codec,
7634                                 dsp_dma_stream_ids[i], 1);
7635
7636                 /* Give the DSP some time to setup the DMA channel. */
7637                 msleep(75);
7638         }
7639
7640         mutex_unlock(&spec->chipio_mutex);
7641 }
7642
7643 /*
7644  * The region of ChipIO memory from 0x190000-0x1903fc is a sort of 'audio
7645  * router', where each entry represents a 48khz audio channel, with a format
7646  * of an 8-bit destination, an 8-bit source, and an unknown 2-bit number
7647  * value. The 2-bit number value is seemingly 0 if inactive, 1 if active,
7648  * and 3 if it's using Sample Rate Converter ports.
7649  * An example is:
7650  * 0x0001f8c0
7651  * In this case, f8 is the destination, and c0 is the source. The number value
7652  * is 1.
7653  * This region of memory is normally managed internally by the 8051, where
7654  * the region of exram memory from 0x1477-0x1575 has each byte represent an
7655  * entry within the 0x190000 range, and when a range of entries is in use, the
7656  * ending value is overwritten with 0xff.
7657  * 0x1578 in exram is a table of 0x25 entries, corresponding to the ChipIO
7658  * streamID's, where each entry is a starting 0x190000 port offset.
7659  * 0x159d in exram is the same as 0x1578, except it contains the ending port
7660  * offset for the corresponding streamID.
7661  *
7662  * On certain cards, such as the SBZ/ZxR/AE7, these are originally setup by
7663  * the 8051, then manually overwritten to remap the ports to work with the
7664  * new DACs.
7665  *
7666  * Currently known portID's:
7667  * 0x00-0x1f: HDA audio stream input/output ports.
7668  * 0x80-0xbf: Sample rate converter input/outputs. Only valid ports seem to
7669  *            have the lower-nibble set to 0x1, 0x2, and 0x9.
7670  * 0xc0-0xdf: DSP DMA input/output ports. Dynamically assigned.
7671  * 0xe0-0xff: DAC/ADC audio input/output ports.
7672  *
7673  * Currently known streamID's:
7674  * 0x03: Mic1 ADC to DSP.
7675  * 0x04: Mic2 ADC to DSP.
7676  * 0x05: HDA node 0x02 audio stream to DSP.
7677  * 0x0f: DSP Mic exit to HDA node 0x07.
7678  * 0x0c: DSP processed audio to DACs.
7679  * 0x14: DAC0, front L/R.
7680  *
7681  * It is possible to route the HDA audio streams directly to the DAC and
7682  * bypass the DSP entirely, with the only downside being that since the DSP
7683  * does volume control, the only volume control you'll get is through PCM on
7684  * the PC side, in the same way volume is handled for optical out. This may be
7685  * useful for debugging.
7686  */
7687 static void chipio_remap_stream(struct hda_codec *codec,
7688                 const struct chipio_stream_remap_data *remap_data)
7689 {
7690         unsigned int i, stream_offset;
7691
7692         /* Get the starting port for the stream to be remapped. */
7693         chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id,
7694                         &stream_offset);
7695
7696         /*
7697          * Check if the stream's port value is 0xff, because the 8051 may not
7698          * have gotten around to setting up the stream yet. Wait until it's
7699          * setup to remap it's ports.
7700          */
7701         if (stream_offset == 0xff) {
7702                 for (i = 0; i < 5; i++) {
7703                         msleep(25);
7704
7705                         chipio_8051_read_exram(codec, 0x1578 + remap_data->stream_id,
7706                                         &stream_offset);
7707
7708                         if (stream_offset != 0xff)
7709                                 break;
7710                 }
7711         }
7712
7713         if (stream_offset == 0xff) {
7714                 codec_info(codec, "%s: Stream 0x%02x ports aren't allocated, remap failed!\n",
7715                                 __func__, remap_data->stream_id);
7716                 return;
7717         }
7718
7719         /* Offset isn't in bytes, its in 32-bit words, so multiply it by 4. */
7720         stream_offset *= 0x04;
7721         stream_offset += 0x190000;
7722
7723         for (i = 0; i < remap_data->count; i++) {
7724                 chipio_write_no_mutex(codec,
7725                                 stream_offset + remap_data->offset[i],
7726                                 remap_data->value[i]);
7727         }
7728
7729         /* Update stream map configuration. */
7730         chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7731 }
7732
7733 /*
7734  * Default speaker tuning values setup for alternative codecs.
7735  */
7736 static const unsigned int sbz_default_delay_values[] = {
7737         /* Non-zero values are floating point 0.000198. */
7738         0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000
7739 };
7740
7741 static const unsigned int zxr_default_delay_values[] = {
7742         /* Non-zero values are floating point 0.000220. */
7743         0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd
7744 };
7745
7746 static const unsigned int ae5_default_delay_values[] = {
7747         /* Non-zero values are floating point 0.000100. */
7748         0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717
7749 };
7750
7751 /*
7752  * If we never change these, probably only need them on initialization.
7753  */
7754 static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec)
7755 {
7756         struct ca0132_spec *spec = codec->spec;
7757         unsigned int i, tmp, start_req, end_req;
7758         const unsigned int *values;
7759
7760         switch (ca0132_quirk(spec)) {
7761         case QUIRK_SBZ:
7762                 values = sbz_default_delay_values;
7763                 break;
7764         case QUIRK_ZXR:
7765                 values = zxr_default_delay_values;
7766                 break;
7767         case QUIRK_AE5:
7768         case QUIRK_AE7:
7769                 values = ae5_default_delay_values;
7770                 break;
7771         default:
7772                 values = sbz_default_delay_values;
7773                 break;
7774         }
7775
7776         tmp = FLOAT_ZERO;
7777         dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp);
7778
7779         start_req = SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL;
7780         end_req = SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL;
7781         for (i = start_req; i < end_req + 1; i++)
7782                 dspio_set_uint_param(codec, 0x96, i, tmp);
7783
7784         start_req = SPEAKER_TUNING_FRONT_LEFT_INVERT;
7785         end_req = SPEAKER_TUNING_REAR_RIGHT_INVERT;
7786         for (i = start_req; i < end_req + 1; i++)
7787                 dspio_set_uint_param(codec, 0x96, i, tmp);
7788
7789
7790         for (i = 0; i < 6; i++)
7791                 dspio_set_uint_param(codec, 0x96,
7792                                 SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]);
7793 }
7794
7795 /*
7796  * Initialize mic for non-chromebook ca0132 implementations.
7797  */
7798 static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
7799 {
7800         struct ca0132_spec *spec = codec->spec;
7801         unsigned int tmp;
7802
7803         /* Mic 1 Setup */
7804         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7805         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7806         if (ca0132_quirk(spec) == QUIRK_R3DI) {
7807                 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7808                 tmp = FLOAT_ONE;
7809         } else
7810                 tmp = FLOAT_THREE;
7811         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7812
7813         /* Mic 2 setup (not present on desktop cards) */
7814         chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
7815         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
7816         if (ca0132_quirk(spec) == QUIRK_R3DI)
7817                 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7818         tmp = FLOAT_ZERO;
7819         dspio_set_uint_param(codec, 0x80, 0x01, tmp);
7820 }
7821
7822 /*
7823  * Sets the source of stream 0x14 to connpointID 0x48, and the destination
7824  * connpointID to 0x91. If this isn't done, the destination is 0x71, and
7825  * you get no sound. I'm guessing this has to do with the Sound Blaster Z
7826  * having an updated DAC, which changes the destination to that DAC.
7827  */
7828 static void sbz_connect_streams(struct hda_codec *codec)
7829 {
7830         struct ca0132_spec *spec = codec->spec;
7831
7832         mutex_lock(&spec->chipio_mutex);
7833
7834         codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
7835
7836         /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
7837         chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
7838
7839         /* Setup stream 0x14 with it's source and destination points */
7840         chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
7841         chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
7842         chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
7843         chipio_set_stream_channels(codec, 0x14, 2);
7844         chipio_set_stream_control(codec, 0x14, 1);
7845
7846         codec_dbg(codec, "Connect Streams exited, mutex released.\n");
7847
7848         mutex_unlock(&spec->chipio_mutex);
7849 }
7850
7851 /*
7852  * Write data through ChipIO to setup proper stream destinations.
7853  * Not sure how it exactly works, but it seems to direct data
7854  * to different destinations. Example is f8 to c0, e0 to c0.
7855  * All I know is, if you don't set these, you get no sound.
7856  */
7857 static void sbz_chipio_startup_data(struct hda_codec *codec)
7858 {
7859         const struct chipio_stream_remap_data *dsp_out_remap_data;
7860         struct ca0132_spec *spec = codec->spec;
7861
7862         mutex_lock(&spec->chipio_mutex);
7863         codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
7864
7865         /* Remap DAC0's output ports. */
7866         chipio_remap_stream(codec, &stream_remap_data[0]);
7867
7868         /* Remap DSP audio output stream ports. */
7869         switch (ca0132_quirk(spec)) {
7870         case QUIRK_SBZ:
7871                 dsp_out_remap_data = &stream_remap_data[1];
7872                 break;
7873
7874         case QUIRK_ZXR:
7875                 dsp_out_remap_data = &stream_remap_data[2];
7876                 break;
7877
7878         default:
7879                 dsp_out_remap_data = NULL;
7880                 break;
7881         }
7882
7883         if (dsp_out_remap_data)
7884                 chipio_remap_stream(codec, dsp_out_remap_data);
7885
7886         codec_dbg(codec, "Startup Data exited, mutex released.\n");
7887         mutex_unlock(&spec->chipio_mutex);
7888 }
7889
7890 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
7891 {
7892         struct ca0132_spec *spec = codec->spec;
7893         unsigned int tmp;
7894
7895         chipio_set_stream_control(codec, 0x03, 0);
7896         chipio_set_stream_control(codec, 0x04, 0);
7897
7898         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7899         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7900
7901         tmp = FLOAT_THREE;
7902         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7903
7904         chipio_set_stream_control(codec, 0x03, 1);
7905         chipio_set_stream_control(codec, 0x04, 1);
7906
7907         switch (ca0132_quirk(spec)) {
7908         case QUIRK_SBZ:
7909                 chipio_write(codec, 0x18b098, 0x0000000c);
7910                 chipio_write(codec, 0x18b09C, 0x0000000c);
7911                 break;
7912         case QUIRK_AE5:
7913                 chipio_write(codec, 0x18b098, 0x0000000c);
7914                 chipio_write(codec, 0x18b09c, 0x0000004c);
7915                 break;
7916         default:
7917                 break;
7918         }
7919 }
7920
7921 static void ae5_post_dsp_register_set(struct hda_codec *codec)
7922 {
7923         struct ca0132_spec *spec = codec->spec;
7924
7925         chipio_8051_write_direct(codec, 0x93, 0x10);
7926         chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
7927
7928         writeb(0xff, spec->mem_base + 0x304);
7929         writeb(0xff, spec->mem_base + 0x304);
7930         writeb(0xff, spec->mem_base + 0x304);
7931         writeb(0xff, spec->mem_base + 0x304);
7932         writeb(0x00, spec->mem_base + 0x100);
7933         writeb(0xff, spec->mem_base + 0x304);
7934         writeb(0x00, spec->mem_base + 0x100);
7935         writeb(0xff, spec->mem_base + 0x304);
7936         writeb(0x00, spec->mem_base + 0x100);
7937         writeb(0xff, spec->mem_base + 0x304);
7938         writeb(0x00, spec->mem_base + 0x100);
7939         writeb(0xff, spec->mem_base + 0x304);
7940
7941         ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
7942         ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7943         ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7944 }
7945
7946 static void ae5_post_dsp_param_setup(struct hda_codec *codec)
7947 {
7948         /*
7949          * Param3 in the 8051's memory is represented by the ascii string 'mch'
7950          * which seems to be 'multichannel'. This is also mentioned in the
7951          * AE-5's registry values in Windows.
7952          */
7953         chipio_set_control_param(codec, 3, 0);
7954         /*
7955          * I believe ASI is 'audio serial interface' and that it's used to
7956          * change colors on the external LED strip connected to the AE-5.
7957          */
7958         chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
7959
7960         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
7961         chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7962
7963         chipio_8051_write_exram(codec, 0xfa92, 0x22);
7964 }
7965
7966 static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
7967 {
7968         chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
7969         chipio_8051_write_pll_pmu(codec, 0x45, 0xcc);
7970         chipio_8051_write_pll_pmu(codec, 0x40, 0xcb);
7971         chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
7972         chipio_8051_write_pll_pmu(codec, 0x51, 0x8d);
7973 }
7974
7975 static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
7976 {
7977         struct ca0132_spec *spec = codec->spec;
7978
7979         mutex_lock(&spec->chipio_mutex);
7980
7981         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7982
7983         chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
7984
7985         chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
7986
7987         chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
7988         chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7989         chipio_set_stream_channels(codec, 0x18, 6);
7990         chipio_set_stream_control(codec, 0x18, 1);
7991
7992         chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
7993
7994         chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
7995
7996         ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
7997
7998         mutex_unlock(&spec->chipio_mutex);
7999 }
8000
8001 static void ae5_post_dsp_startup_data(struct hda_codec *codec)
8002 {
8003         struct ca0132_spec *spec = codec->spec;
8004
8005         mutex_lock(&spec->chipio_mutex);
8006
8007         chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
8008         chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
8009         chipio_write_no_mutex(codec, 0x189024, 0x00014004);
8010         chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
8011
8012         ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
8013         chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8014         ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
8015         ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
8016         ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
8017         ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
8018         ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8019         ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8020         ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8021         ca0113_mmio_gpio_set(codec, 0, true);
8022         ca0113_mmio_gpio_set(codec, 1, true);
8023         ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
8024
8025         chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
8026
8027         ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8028         ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8029
8030         mutex_unlock(&spec->chipio_mutex);
8031 }
8032
8033 static void ae7_post_dsp_setup_ports(struct hda_codec *codec)
8034 {
8035         struct ca0132_spec *spec = codec->spec;
8036
8037         mutex_lock(&spec->chipio_mutex);
8038
8039         /* Seems to share the same port remapping as the SBZ. */
8040         chipio_remap_stream(codec, &stream_remap_data[1]);
8041
8042         ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8043         ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40);
8044         ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00);
8045         ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00);
8046         ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff);
8047         ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff);
8048         ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff);
8049         ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f);
8050
8051         mutex_unlock(&spec->chipio_mutex);
8052 }
8053
8054 static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec)
8055 {
8056         struct ca0132_spec *spec = codec->spec;
8057
8058         mutex_lock(&spec->chipio_mutex);
8059
8060         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
8061         ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8062
8063         chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
8064
8065         chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
8066         chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
8067
8068         chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8069         chipio_set_stream_channels(codec, 0x18, 6);
8070         chipio_set_stream_control(codec, 0x18, 1);
8071
8072         chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
8073
8074         mutex_unlock(&spec->chipio_mutex);
8075 }
8076
8077 static void ae7_post_dsp_pll_setup(struct hda_codec *codec)
8078 {
8079         static const unsigned int addr[] = {
8080                 0x41, 0x45, 0x40, 0x43, 0x51
8081         };
8082         static const unsigned int data[] = {
8083                 0xc8, 0xcc, 0xcb, 0xc7, 0x8d
8084         };
8085         unsigned int i;
8086
8087         for (i = 0; i < ARRAY_SIZE(addr); i++)
8088                 chipio_8051_write_pll_pmu_no_mutex(codec, addr[i], data[i]);
8089 }
8090
8091 static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec)
8092 {
8093         struct ca0132_spec *spec = codec->spec;
8094         static const unsigned int target[] = {
8095                 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14
8096         };
8097         static const unsigned int data[] = {
8098                 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f
8099         };
8100         unsigned int i;
8101
8102         mutex_lock(&spec->chipio_mutex);
8103
8104         chipio_8051_write_pll_pmu_no_mutex(codec, 0x43, 0xc7);
8105
8106         chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
8107         chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
8108         chipio_write_no_mutex(codec, 0x189024, 0x00014004);
8109         chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
8110
8111         ae7_post_dsp_pll_setup(codec);
8112         chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8113
8114         for (i = 0; i < ARRAY_SIZE(target); i++)
8115                 ca0113_mmio_command_set(codec, 0x48, target[i], data[i]);
8116
8117         ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8118         ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8119         ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8120
8121         chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56);
8122         chipio_set_stream_channels(codec, 0x21, 2);
8123         chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000);
8124
8125         chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09);
8126         /*
8127          * In the 8051's memory, this param is referred to as 'n2sid', which I
8128          * believe is 'node to streamID'. It seems to be a way to assign a
8129          * stream to a given HDA node.
8130          */
8131         chipio_set_control_param_no_mutex(codec, 0x20, 0x21);
8132
8133         chipio_write_no_mutex(codec, 0x18b038, 0x00000088);
8134
8135         /*
8136          * Now, at this point on Windows, an actual stream is setup and
8137          * seemingly sends data to the HDA node 0x09, which is the digital
8138          * audio input node. This is left out here, because obviously I don't
8139          * know what data is being sent. Interestingly, the AE-5 seems to go
8140          * through the motions of getting here and never actually takes this
8141          * step, but the AE-7 does.
8142          */
8143
8144         ca0113_mmio_gpio_set(codec, 0, 1);
8145         ca0113_mmio_gpio_set(codec, 1, 1);
8146
8147         ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8148         chipio_write_no_mutex(codec, 0x18b03c, 0x00000000);
8149         ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
8150         ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
8151
8152         chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
8153         chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
8154
8155         chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
8156         chipio_set_stream_channels(codec, 0x18, 6);
8157
8158         /*
8159          * Runs again, this has been repeated a few times, but I'm just
8160          * following what the Windows driver does.
8161          */
8162         ae7_post_dsp_pll_setup(codec);
8163         chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8164
8165         mutex_unlock(&spec->chipio_mutex);
8166 }
8167
8168 /*
8169  * The Windows driver has commands that seem to setup ASI, which I believe to
8170  * be some sort of audio serial interface. My current speculation is that it's
8171  * related to communicating with the new DAC.
8172  */
8173 static void ae7_post_dsp_asi_setup(struct hda_codec *codec)
8174 {
8175         chipio_8051_write_direct(codec, 0x93, 0x10);
8176
8177         chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
8178
8179         ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8180         ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8181
8182         chipio_set_control_param(codec, 3, 3);
8183         chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
8184
8185         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
8186         chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8187         snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00);
8188
8189         chipio_8051_write_exram(codec, 0xfa92, 0x22);
8190
8191         ae7_post_dsp_pll_setup(codec);
8192         ae7_post_dsp_asi_stream_setup(codec);
8193
8194         chipio_8051_write_pll_pmu(codec, 0x43, 0xc7);
8195
8196         ae7_post_dsp_asi_setup_ports(codec);
8197 }
8198
8199 /*
8200  * Setup default parameters for DSP
8201  */
8202 static void ca0132_setup_defaults(struct hda_codec *codec)
8203 {
8204         struct ca0132_spec *spec = codec->spec;
8205         unsigned int tmp;
8206         int num_fx;
8207         int idx, i;
8208
8209         if (spec->dsp_state != DSP_DOWNLOADED)
8210                 return;
8211
8212         /* out, in effects + voicefx */
8213         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8214         for (idx = 0; idx < num_fx; idx++) {
8215                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8216                         dspio_set_uint_param(codec, ca0132_effects[idx].mid,
8217                                              ca0132_effects[idx].reqs[i],
8218                                              ca0132_effects[idx].def_vals[i]);
8219                 }
8220         }
8221
8222         /*remove DSP headroom*/
8223         tmp = FLOAT_ZERO;
8224         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8225
8226         /*set speaker EQ bypass attenuation*/
8227         dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
8228
8229         /* set AMic1 and AMic2 as mono mic */
8230         tmp = FLOAT_ONE;
8231         dspio_set_uint_param(codec, 0x80, 0x00, tmp);
8232         dspio_set_uint_param(codec, 0x80, 0x01, tmp);
8233
8234         /* set AMic1 as CrystalVoice input */
8235         tmp = FLOAT_ONE;
8236         dspio_set_uint_param(codec, 0x80, 0x05, tmp);
8237
8238         /* set WUH source */
8239         tmp = FLOAT_TWO;
8240         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8241 }
8242
8243 /*
8244  * Setup default parameters for Recon3D/Recon3Di DSP.
8245  */
8246
8247 static void r3d_setup_defaults(struct hda_codec *codec)
8248 {
8249         struct ca0132_spec *spec = codec->spec;
8250         unsigned int tmp;
8251         int num_fx;
8252         int idx, i;
8253
8254         if (spec->dsp_state != DSP_DOWNLOADED)
8255                 return;
8256
8257         ca0132_alt_init_analog_mics(codec);
8258         ca0132_alt_start_dsp_audio_streams(codec);
8259
8260         /*remove DSP headroom*/
8261         tmp = FLOAT_ZERO;
8262         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8263
8264         /* set WUH source */
8265         tmp = FLOAT_TWO;
8266         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8267         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8268
8269         /* Set speaker source? */
8270         dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8271
8272         if (ca0132_quirk(spec) == QUIRK_R3DI)
8273                 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
8274
8275         /* Disable mute on Center/LFE. */
8276         if (ca0132_quirk(spec) == QUIRK_R3D) {
8277                 ca0113_mmio_gpio_set(codec, 2, false);
8278                 ca0113_mmio_gpio_set(codec, 4, true);
8279         }
8280
8281         /* Setup effect defaults */
8282         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8283         for (idx = 0; idx < num_fx; idx++) {
8284                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8285                         dspio_set_uint_param(codec,
8286                                         ca0132_effects[idx].mid,
8287                                         ca0132_effects[idx].reqs[i],
8288                                         ca0132_effects[idx].def_vals[i]);
8289                 }
8290         }
8291 }
8292
8293 /*
8294  * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
8295  * than the Chromebook setup.
8296  */
8297 static void sbz_setup_defaults(struct hda_codec *codec)
8298 {
8299         struct ca0132_spec *spec = codec->spec;
8300         unsigned int tmp;
8301         int num_fx;
8302         int idx, i;
8303
8304         if (spec->dsp_state != DSP_DOWNLOADED)
8305                 return;
8306
8307         ca0132_alt_init_analog_mics(codec);
8308         ca0132_alt_start_dsp_audio_streams(codec);
8309         sbz_connect_streams(codec);
8310         sbz_chipio_startup_data(codec);
8311
8312         /*
8313          * Sets internal input loopback to off, used to have a switch to
8314          * enable input loopback, but turned out to be way too buggy.
8315          */
8316         tmp = FLOAT_ONE;
8317         dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8318         dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8319
8320         /*remove DSP headroom*/
8321         tmp = FLOAT_ZERO;
8322         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8323
8324         /* set WUH source */
8325         tmp = FLOAT_TWO;
8326         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8327         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8328
8329         /* Set speaker source? */
8330         dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8331
8332         ca0132_alt_dsp_initial_mic_setup(codec);
8333
8334         /* out, in effects + voicefx */
8335         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8336         for (idx = 0; idx < num_fx; idx++) {
8337                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8338                         dspio_set_uint_param(codec,
8339                                         ca0132_effects[idx].mid,
8340                                         ca0132_effects[idx].reqs[i],
8341                                         ca0132_effects[idx].def_vals[i]);
8342                 }
8343         }
8344
8345         ca0132_alt_init_speaker_tuning(codec);
8346 }
8347
8348 /*
8349  * Setup default parameters for the Sound BlasterX AE-5 DSP.
8350  */
8351 static void ae5_setup_defaults(struct hda_codec *codec)
8352 {
8353         struct ca0132_spec *spec = codec->spec;
8354         unsigned int tmp;
8355         int num_fx;
8356         int idx, i;
8357
8358         if (spec->dsp_state != DSP_DOWNLOADED)
8359                 return;
8360
8361         ca0132_alt_init_analog_mics(codec);
8362         ca0132_alt_start_dsp_audio_streams(codec);
8363
8364         /* New, unknown SCP req's */
8365         tmp = FLOAT_ZERO;
8366         dspio_set_uint_param(codec, 0x96, 0x29, tmp);
8367         dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
8368         dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8369         dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8370
8371         ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8372         ca0113_mmio_gpio_set(codec, 0, false);
8373         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8374
8375         /* Internal loopback off */
8376         tmp = FLOAT_ONE;
8377         dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8378         dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8379
8380         /*remove DSP headroom*/
8381         tmp = FLOAT_ZERO;
8382         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8383
8384         /* set WUH source */
8385         tmp = FLOAT_TWO;
8386         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8387         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8388
8389         /* Set speaker source? */
8390         dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8391
8392         ca0132_alt_dsp_initial_mic_setup(codec);
8393         ae5_post_dsp_register_set(codec);
8394         ae5_post_dsp_param_setup(codec);
8395         ae5_post_dsp_pll_setup(codec);
8396         ae5_post_dsp_stream_setup(codec);
8397         ae5_post_dsp_startup_data(codec);
8398
8399         /* out, in effects + voicefx */
8400         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8401         for (idx = 0; idx < num_fx; idx++) {
8402                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8403                         dspio_set_uint_param(codec,
8404                                         ca0132_effects[idx].mid,
8405                                         ca0132_effects[idx].reqs[i],
8406                                         ca0132_effects[idx].def_vals[i]);
8407                 }
8408         }
8409
8410         ca0132_alt_init_speaker_tuning(codec);
8411 }
8412
8413 /*
8414  * Setup default parameters for the Sound Blaster AE-7 DSP.
8415  */
8416 static void ae7_setup_defaults(struct hda_codec *codec)
8417 {
8418         struct ca0132_spec *spec = codec->spec;
8419         unsigned int tmp;
8420         int num_fx;
8421         int idx, i;
8422
8423         if (spec->dsp_state != DSP_DOWNLOADED)
8424                 return;
8425
8426         ca0132_alt_init_analog_mics(codec);
8427         ca0132_alt_start_dsp_audio_streams(codec);
8428         ae7_post_dsp_setup_ports(codec);
8429
8430         tmp = FLOAT_ZERO;
8431         dspio_set_uint_param(codec, 0x96,
8432                         SPEAKER_TUNING_FRONT_LEFT_INVERT, tmp);
8433         dspio_set_uint_param(codec, 0x96,
8434                         SPEAKER_TUNING_FRONT_RIGHT_INVERT, tmp);
8435
8436         ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8437
8438         /* New, unknown SCP req's */
8439         dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8440         dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8441
8442         ca0113_mmio_gpio_set(codec, 0, false);
8443
8444         /* Internal loopback off */
8445         tmp = FLOAT_ONE;
8446         dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8447         dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8448
8449         /*remove DSP headroom*/
8450         tmp = FLOAT_ZERO;
8451         dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8452
8453         /* set WUH source */
8454         tmp = FLOAT_TWO;
8455         dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8456         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8457
8458         /* Set speaker source? */
8459         dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8460         ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8461
8462         /*
8463          * This is the second time we've called this, but this is seemingly
8464          * what Windows does.
8465          */
8466         ca0132_alt_init_analog_mics(codec);
8467
8468         ae7_post_dsp_asi_setup(codec);
8469
8470         /*
8471          * Not sure why, but these are both set to 1. They're only set to 0
8472          * upon shutdown.
8473          */
8474         ca0113_mmio_gpio_set(codec, 0, true);
8475         ca0113_mmio_gpio_set(codec, 1, true);
8476
8477         /* Volume control related. */
8478         ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04);
8479         ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04);
8480         ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80);
8481
8482         /* out, in effects + voicefx */
8483         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8484         for (idx = 0; idx < num_fx; idx++) {
8485                 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8486                         dspio_set_uint_param(codec,
8487                                         ca0132_effects[idx].mid,
8488                                         ca0132_effects[idx].reqs[i],
8489                                         ca0132_effects[idx].def_vals[i]);
8490                 }
8491         }
8492
8493         ca0132_alt_init_speaker_tuning(codec);
8494 }
8495
8496 /*
8497  * Initialization of flags in chip
8498  */
8499 static void ca0132_init_flags(struct hda_codec *codec)
8500 {
8501         struct ca0132_spec *spec = codec->spec;
8502
8503         if (ca0132_use_alt_functions(spec)) {
8504                 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
8505                 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
8506                 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
8507                 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
8508                 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
8509                 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8510                 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
8511                 chipio_set_control_flag(codec,
8512                                 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8513                 chipio_set_control_flag(codec,
8514                                 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
8515         } else {
8516                 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8517                 chipio_set_control_flag(codec,
8518                                 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
8519                 chipio_set_control_flag(codec,
8520                                 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
8521                 chipio_set_control_flag(codec,
8522                                 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
8523                 chipio_set_control_flag(codec,
8524                                 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8525                 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
8526         }
8527 }
8528
8529 /*
8530  * Initialization of parameters in chip
8531  */
8532 static void ca0132_init_params(struct hda_codec *codec)
8533 {
8534         struct ca0132_spec *spec = codec->spec;
8535
8536         if (ca0132_use_alt_functions(spec)) {
8537                 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8538                 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
8539                 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
8540                 chipio_set_control_param(codec, 0, 0);
8541                 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
8542         }
8543
8544         chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
8545         chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
8546 }
8547
8548 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
8549 {
8550         chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
8551         chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
8552         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
8553         chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
8554         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
8555         chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
8556
8557         chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
8558         chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
8559         chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8560 }
8561
8562 static bool ca0132_download_dsp_images(struct hda_codec *codec)
8563 {
8564         bool dsp_loaded = false;
8565         struct ca0132_spec *spec = codec->spec;
8566         const struct dsp_image_seg *dsp_os_image;
8567         const struct firmware *fw_entry = NULL;
8568         /*
8569          * Alternate firmwares for different variants. The Recon3Di apparently
8570          * can use the default firmware, but I'll leave the option in case
8571          * it needs it again.
8572          */
8573         switch (ca0132_quirk(spec)) {
8574         case QUIRK_SBZ:
8575         case QUIRK_R3D:
8576         case QUIRK_AE5:
8577                 if (reject_firmware(&fw_entry, DESKTOP_EFX_FILE,
8578                                         codec->card->dev) != 0)
8579                         codec_dbg(codec, "Desktop firmware not found.");
8580                 else
8581                         codec_dbg(codec, "Desktop firmware selected.");
8582                 break;
8583         case QUIRK_R3DI:
8584                 if (reject_firmware(&fw_entry, R3DI_EFX_FILE,
8585                                         codec->card->dev) != 0)
8586                         codec_dbg(codec, "Recon3Di alt firmware not detected.");
8587                 else
8588                         codec_dbg(codec, "Recon3Di firmware selected.");
8589                 break;
8590         default:
8591                 break;
8592         }
8593 /*(DEBLOBBED)*/
8594         if (!fw_entry) {
8595                 codec_dbg(codec, "Default firmware selected.");
8596                 if (reject_firmware(&fw_entry, EFX_FILE,
8597                                         codec->card->dev) != 0)
8598                         return false;
8599         }
8600
8601         dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
8602         if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
8603                 codec_err(codec, "ca0132 DSP load image failed\n");
8604                 goto exit_download;
8605         }
8606
8607         dsp_loaded = dspload_wait_loaded(codec);
8608
8609 exit_download:
8610         release_firmware(fw_entry);
8611
8612         return dsp_loaded;
8613 }
8614
8615 static void ca0132_download_dsp(struct hda_codec *codec)
8616 {
8617         struct ca0132_spec *spec = codec->spec;
8618
8619 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
8620         return; /* NOP */
8621 #endif
8622
8623         if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
8624                 return; /* don't retry failures */
8625
8626         chipio_enable_clocks(codec);
8627         if (spec->dsp_state != DSP_DOWNLOADED) {
8628                 spec->dsp_state = DSP_DOWNLOADING;
8629
8630                 if (!ca0132_download_dsp_images(codec))
8631                         spec->dsp_state = DSP_DOWNLOAD_FAILED;
8632                 else
8633                         spec->dsp_state = DSP_DOWNLOADED;
8634         }
8635
8636         /* For codecs using alt functions, this is already done earlier */
8637         if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec))
8638                 ca0132_set_dsp_msr(codec, true);
8639 }
8640
8641 static void ca0132_process_dsp_response(struct hda_codec *codec,
8642                                         struct hda_jack_callback *callback)
8643 {
8644         struct ca0132_spec *spec = codec->spec;
8645
8646         codec_dbg(codec, "ca0132_process_dsp_response\n");
8647         snd_hda_power_up_pm(codec);
8648         if (spec->wait_scp) {
8649                 if (dspio_get_response_data(codec) >= 0)
8650                         spec->wait_scp = 0;
8651         }
8652
8653         dspio_clear_response_queue(codec);
8654         snd_hda_power_down_pm(codec);
8655 }
8656
8657 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8658 {
8659         struct ca0132_spec *spec = codec->spec;
8660         struct hda_jack_tbl *tbl;
8661
8662         /* Delay enabling the HP amp, to let the mic-detection
8663          * state machine run.
8664          */
8665         tbl = snd_hda_jack_tbl_get(codec, cb->nid);
8666         if (tbl)
8667                 tbl->block_report = 1;
8668         schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
8669 }
8670
8671 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8672 {
8673         struct ca0132_spec *spec = codec->spec;
8674
8675         if (ca0132_use_alt_functions(spec))
8676                 ca0132_alt_select_in(codec);
8677         else
8678                 ca0132_select_mic(codec);
8679 }
8680
8681 static void ca0132_setup_unsol(struct hda_codec *codec)
8682 {
8683         struct ca0132_spec *spec = codec->spec;
8684         snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
8685         snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
8686                                             amic_callback);
8687         snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
8688                                             ca0132_process_dsp_response);
8689         /* Front headphone jack detection */
8690         if (ca0132_use_alt_functions(spec))
8691                 snd_hda_jack_detect_enable_callback(codec,
8692                         spec->unsol_tag_front_hp, hp_callback);
8693 }
8694
8695 /*
8696  * Verbs tables.
8697  */
8698
8699 /* Sends before DSP download. */
8700 static const struct hda_verb ca0132_base_init_verbs[] = {
8701         /*enable ct extension*/
8702         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
8703         {}
8704 };
8705
8706 /* Send at exit. */
8707 static const struct hda_verb ca0132_base_exit_verbs[] = {
8708         /*set afg to D3*/
8709         {0x01, AC_VERB_SET_POWER_STATE, 0x03},
8710         /*disable ct extension*/
8711         {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
8712         {}
8713 };
8714
8715 /* Other verbs tables. Sends after DSP download. */
8716
8717 static const struct hda_verb ca0132_init_verbs0[] = {
8718         /* chip init verbs */
8719         {0x15, 0x70D, 0xF0},
8720         {0x15, 0x70E, 0xFE},
8721         {0x15, 0x707, 0x75},
8722         {0x15, 0x707, 0xD3},
8723         {0x15, 0x707, 0x09},
8724         {0x15, 0x707, 0x53},
8725         {0x15, 0x707, 0xD4},
8726         {0x15, 0x707, 0xEF},
8727         {0x15, 0x707, 0x75},
8728         {0x15, 0x707, 0xD3},
8729         {0x15, 0x707, 0x09},
8730         {0x15, 0x707, 0x02},
8731         {0x15, 0x707, 0x37},
8732         {0x15, 0x707, 0x78},
8733         {0x15, 0x53C, 0xCE},
8734         {0x15, 0x575, 0xC9},
8735         {0x15, 0x53D, 0xCE},
8736         {0x15, 0x5B7, 0xC9},
8737         {0x15, 0x70D, 0xE8},
8738         {0x15, 0x70E, 0xFE},
8739         {0x15, 0x707, 0x02},
8740         {0x15, 0x707, 0x68},
8741         {0x15, 0x707, 0x62},
8742         {0x15, 0x53A, 0xCE},
8743         {0x15, 0x546, 0xC9},
8744         {0x15, 0x53B, 0xCE},
8745         {0x15, 0x5E8, 0xC9},
8746         {}
8747 };
8748
8749 /* Extra init verbs for desktop cards. */
8750 static const struct hda_verb ca0132_init_verbs1[] = {
8751         {0x15, 0x70D, 0x20},
8752         {0x15, 0x70E, 0x19},
8753         {0x15, 0x707, 0x00},
8754         {0x15, 0x539, 0xCE},
8755         {0x15, 0x546, 0xC9},
8756         {0x15, 0x70D, 0xB7},
8757         {0x15, 0x70E, 0x09},
8758         {0x15, 0x707, 0x10},
8759         {0x15, 0x70D, 0xAF},
8760         {0x15, 0x70E, 0x09},
8761         {0x15, 0x707, 0x01},
8762         {0x15, 0x707, 0x05},
8763         {0x15, 0x70D, 0x73},
8764         {0x15, 0x70E, 0x09},
8765         {0x15, 0x707, 0x14},
8766         {0x15, 0x6FF, 0xC4},
8767         {}
8768 };
8769
8770 static void ca0132_init_chip(struct hda_codec *codec)
8771 {
8772         struct ca0132_spec *spec = codec->spec;
8773         int num_fx;
8774         int i;
8775         unsigned int on;
8776
8777         mutex_init(&spec->chipio_mutex);
8778
8779         /*
8780          * The Windows driver always does this upon startup, which seems to
8781          * clear out any previous configuration. This should help issues where
8782          * a boot into Windows prior to a boot into Linux breaks things. Also,
8783          * Windows always sends the reset twice.
8784          */
8785         if (ca0132_use_alt_functions(spec)) {
8786                 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8787                 chipio_write_no_mutex(codec, 0x18b0a4, 0x000000c2);
8788
8789                 snd_hda_codec_write(codec, codec->core.afg, 0,
8790                             AC_VERB_SET_CODEC_RESET, 0);
8791                 snd_hda_codec_write(codec, codec->core.afg, 0,
8792                             AC_VERB_SET_CODEC_RESET, 0);
8793         }
8794
8795         spec->cur_out_type = SPEAKER_OUT;
8796         if (!ca0132_use_alt_functions(spec))
8797                 spec->cur_mic_type = DIGITAL_MIC;
8798         else
8799                 spec->cur_mic_type = REAR_MIC;
8800
8801         spec->cur_mic_boost = 0;
8802
8803         for (i = 0; i < VNODES_COUNT; i++) {
8804                 spec->vnode_lvol[i] = 0x5a;
8805                 spec->vnode_rvol[i] = 0x5a;
8806                 spec->vnode_lswitch[i] = 0;
8807                 spec->vnode_rswitch[i] = 0;
8808         }
8809
8810         /*
8811          * Default states for effects are in ca0132_effects[].
8812          */
8813         num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
8814         for (i = 0; i < num_fx; i++) {
8815                 on = (unsigned int)ca0132_effects[i].reqs[0];
8816                 spec->effects_switch[i] = on ? 1 : 0;
8817         }
8818         /*
8819          * Sets defaults for the effect slider controls, only for alternative
8820          * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
8821          */
8822         if (ca0132_use_alt_controls(spec)) {
8823                 /* Set speakers to default to full range. */
8824                 spec->speaker_range_val[0] = 1;
8825                 spec->speaker_range_val[1] = 1;
8826
8827                 spec->xbass_xover_freq = 8;
8828                 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
8829                         spec->fx_ctl_val[i] = effect_slider_defaults[i];
8830
8831                 spec->bass_redirect_xover_freq = 8;
8832         }
8833
8834         spec->voicefx_val = 0;
8835         spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
8836         spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
8837
8838         /*
8839          * The ZxR doesn't have a front panel header, and it's line-in is on
8840          * the daughter board. So, there is no input enum control, and we need
8841          * to make sure that spec->in_enum_val is set properly.
8842          */
8843         if (ca0132_quirk(spec) == QUIRK_ZXR)
8844                 spec->in_enum_val = REAR_MIC;
8845
8846 #ifdef ENABLE_TUNING_CONTROLS
8847         ca0132_init_tuning_defaults(codec);
8848 #endif
8849 }
8850
8851 /*
8852  * Recon3Di exit specific commands.
8853  */
8854 /* prevents popping noise on shutdown */
8855 static void r3di_gpio_shutdown(struct hda_codec *codec)
8856 {
8857         snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
8858 }
8859
8860 /*
8861  * Sound Blaster Z exit specific commands.
8862  */
8863 static void sbz_region2_exit(struct hda_codec *codec)
8864 {
8865         struct ca0132_spec *spec = codec->spec;
8866         unsigned int i;
8867
8868         for (i = 0; i < 4; i++)
8869                 writeb(0x0, spec->mem_base + 0x100);
8870         for (i = 0; i < 8; i++)
8871                 writeb(0xb3, spec->mem_base + 0x304);
8872
8873         ca0113_mmio_gpio_set(codec, 0, false);
8874         ca0113_mmio_gpio_set(codec, 1, false);
8875         ca0113_mmio_gpio_set(codec, 4, true);
8876         ca0113_mmio_gpio_set(codec, 5, false);
8877         ca0113_mmio_gpio_set(codec, 7, false);
8878 }
8879
8880 static void sbz_set_pin_ctl_default(struct hda_codec *codec)
8881 {
8882         static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
8883         unsigned int i;
8884
8885         snd_hda_codec_write(codec, 0x11, 0,
8886                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
8887
8888         for (i = 0; i < ARRAY_SIZE(pins); i++)
8889                 snd_hda_codec_write(codec, pins[i], 0,
8890                                 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
8891 }
8892
8893 static void ca0132_clear_unsolicited(struct hda_codec *codec)
8894 {
8895         static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
8896         unsigned int i;
8897
8898         for (i = 0; i < ARRAY_SIZE(pins); i++) {
8899                 snd_hda_codec_write(codec, pins[i], 0,
8900                                 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
8901         }
8902 }
8903
8904 /* On shutdown, sends commands in sets of three */
8905 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
8906                                                         int mask, int data)
8907 {
8908         if (dir >= 0)
8909                 snd_hda_codec_write(codec, 0x01, 0,
8910                                 AC_VERB_SET_GPIO_DIRECTION, dir);
8911         if (mask >= 0)
8912                 snd_hda_codec_write(codec, 0x01, 0,
8913                                 AC_VERB_SET_GPIO_MASK, mask);
8914
8915         if (data >= 0)
8916                 snd_hda_codec_write(codec, 0x01, 0,
8917                                 AC_VERB_SET_GPIO_DATA, data);
8918 }
8919
8920 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec)
8921 {
8922         static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01};
8923         unsigned int i;
8924
8925         for (i = 0; i < ARRAY_SIZE(pins); i++)
8926                 snd_hda_codec_write(codec, pins[i], 0,
8927                                 AC_VERB_SET_POWER_STATE, 0x03);
8928 }
8929
8930 static void sbz_exit_chip(struct hda_codec *codec)
8931 {
8932         chipio_set_stream_control(codec, 0x03, 0);
8933         chipio_set_stream_control(codec, 0x04, 0);
8934
8935         /* Mess with GPIO */
8936         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
8937         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
8938         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
8939
8940         chipio_set_stream_control(codec, 0x14, 0);
8941         chipio_set_stream_control(codec, 0x0C, 0);
8942
8943         chipio_set_conn_rate(codec, 0x41, SR_192_000);
8944         chipio_set_conn_rate(codec, 0x91, SR_192_000);
8945
8946         chipio_write(codec, 0x18a020, 0x00000083);
8947
8948         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
8949         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
8950         sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
8951
8952         chipio_set_stream_control(codec, 0x0C, 0);
8953
8954         chipio_set_control_param(codec, 0x0D, 0x24);
8955
8956         ca0132_clear_unsolicited(codec);
8957         sbz_set_pin_ctl_default(codec);
8958
8959         snd_hda_codec_write(codec, 0x0B, 0,
8960                 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
8961
8962         sbz_region2_exit(codec);
8963 }
8964
8965 static void r3d_exit_chip(struct hda_codec *codec)
8966 {
8967         ca0132_clear_unsolicited(codec);
8968         snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8969         snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
8970 }
8971
8972 static void ae5_exit_chip(struct hda_codec *codec)
8973 {
8974         chipio_set_stream_control(codec, 0x03, 0);
8975         chipio_set_stream_control(codec, 0x04, 0);
8976
8977         ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8978         ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8979         ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8980         ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8981         ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8982         ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00);
8983         ca0113_mmio_gpio_set(codec, 0, false);
8984         ca0113_mmio_gpio_set(codec, 1, false);
8985
8986         snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8987         snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8988
8989         chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8990
8991         chipio_set_stream_control(codec, 0x18, 0);
8992         chipio_set_stream_control(codec, 0x0c, 0);
8993
8994         snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83);
8995 }
8996
8997 static void ae7_exit_chip(struct hda_codec *codec)
8998 {
8999         chipio_set_stream_control(codec, 0x18, 0);
9000         chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8);
9001         chipio_set_stream_channels(codec, 0x21, 0);
9002         chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09);
9003         chipio_set_control_param(codec, 0x20, 0x01);
9004
9005         chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
9006
9007         chipio_set_stream_control(codec, 0x18, 0);
9008         chipio_set_stream_control(codec, 0x0c, 0);
9009
9010         ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
9011         snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83);
9012         ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
9013         ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
9014         ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00);
9015         ca0113_mmio_gpio_set(codec, 0, false);
9016         ca0113_mmio_gpio_set(codec, 1, false);
9017         ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9018
9019         snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
9020         snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
9021 }
9022
9023 static void zxr_exit_chip(struct hda_codec *codec)
9024 {
9025         chipio_set_stream_control(codec, 0x03, 0);
9026         chipio_set_stream_control(codec, 0x04, 0);
9027         chipio_set_stream_control(codec, 0x14, 0);
9028         chipio_set_stream_control(codec, 0x0C, 0);
9029
9030         chipio_set_conn_rate(codec, 0x41, SR_192_000);
9031         chipio_set_conn_rate(codec, 0x91, SR_192_000);
9032
9033         chipio_write(codec, 0x18a020, 0x00000083);
9034
9035         snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
9036         snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
9037
9038         ca0132_clear_unsolicited(codec);
9039         sbz_set_pin_ctl_default(codec);
9040         snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00);
9041
9042         ca0113_mmio_gpio_set(codec, 5, false);
9043         ca0113_mmio_gpio_set(codec, 2, false);
9044         ca0113_mmio_gpio_set(codec, 3, false);
9045         ca0113_mmio_gpio_set(codec, 0, false);
9046         ca0113_mmio_gpio_set(codec, 4, true);
9047         ca0113_mmio_gpio_set(codec, 0, true);
9048         ca0113_mmio_gpio_set(codec, 5, true);
9049         ca0113_mmio_gpio_set(codec, 2, false);
9050         ca0113_mmio_gpio_set(codec, 3, false);
9051 }
9052
9053 static void ca0132_exit_chip(struct hda_codec *codec)
9054 {
9055         /* put any chip cleanup stuffs here. */
9056
9057         if (dspload_is_loaded(codec))
9058                 dsp_reset(codec);
9059 }
9060
9061 /*
9062  * This fixes a problem that was hard to reproduce. Very rarely, I would
9063  * boot up, and there would be no sound, but the DSP indicated it had loaded
9064  * properly. I did a few memory dumps to see if anything was different, and
9065  * there were a few areas of memory uninitialized with a1a2a3a4. This function
9066  * checks if those areas are uninitialized, and if they are, it'll attempt to
9067  * reload the card 3 times. Usually it fixes by the second.
9068  */
9069 static void sbz_dsp_startup_check(struct hda_codec *codec)
9070 {
9071         struct ca0132_spec *spec = codec->spec;
9072         unsigned int dsp_data_check[4];
9073         unsigned int cur_address = 0x390;
9074         unsigned int i;
9075         unsigned int failure = 0;
9076         unsigned int reload = 3;
9077
9078         if (spec->startup_check_entered)
9079                 return;
9080
9081         spec->startup_check_entered = true;
9082
9083         for (i = 0; i < 4; i++) {
9084                 chipio_read(codec, cur_address, &dsp_data_check[i]);
9085                 cur_address += 0x4;
9086         }
9087         for (i = 0; i < 4; i++) {
9088                 if (dsp_data_check[i] == 0xa1a2a3a4)
9089                         failure = 1;
9090         }
9091
9092         codec_dbg(codec, "Startup Check: %d ", failure);
9093         if (failure)
9094                 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
9095         /*
9096          * While the failure condition is true, and we haven't reached our
9097          * three reload limit, continue trying to reload the driver and
9098          * fix the issue.
9099          */
9100         while (failure && (reload != 0)) {
9101                 codec_info(codec, "Reloading... Tries left: %d", reload);
9102                 sbz_exit_chip(codec);
9103                 spec->dsp_state = DSP_DOWNLOAD_INIT;
9104                 codec->patch_ops.init(codec);
9105                 failure = 0;
9106                 for (i = 0; i < 4; i++) {
9107                         chipio_read(codec, cur_address, &dsp_data_check[i]);
9108                         cur_address += 0x4;
9109                 }
9110                 for (i = 0; i < 4; i++) {
9111                         if (dsp_data_check[i] == 0xa1a2a3a4)
9112                                 failure = 1;
9113                 }
9114                 reload--;
9115         }
9116
9117         if (!failure && reload < 3)
9118                 codec_info(codec, "DSP fixed.");
9119
9120         if (!failure)
9121                 return;
9122
9123         codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
9124 }
9125
9126 /*
9127  * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
9128  * extra precision for decibel values. If you had the dB value in floating point
9129  * you would take the value after the decimal point, multiply by 64, and divide
9130  * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
9131  * implement fixed point or floating point dB volumes. For now, I'll set them
9132  * to 0 just incase a value has lingered from a boot into Windows.
9133  */
9134 static void ca0132_alt_vol_setup(struct hda_codec *codec)
9135 {
9136         snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
9137         snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
9138         snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
9139         snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
9140         snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
9141         snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
9142         snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
9143         snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
9144 }
9145
9146 /*
9147  * Extra commands that don't really fit anywhere else.
9148  */
9149 static void sbz_pre_dsp_setup(struct hda_codec *codec)
9150 {
9151         struct ca0132_spec *spec = codec->spec;
9152
9153         writel(0x00820680, spec->mem_base + 0x01C);
9154         writel(0x00820680, spec->mem_base + 0x01C);
9155
9156         chipio_write(codec, 0x18b0a4, 0x000000c2);
9157
9158         snd_hda_codec_write(codec, 0x11, 0,
9159                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9160 }
9161
9162 static void r3d_pre_dsp_setup(struct hda_codec *codec)
9163 {
9164         chipio_write(codec, 0x18b0a4, 0x000000c2);
9165
9166         chipio_8051_write_exram(codec, 0x1c1e, 0x5b);
9167
9168         snd_hda_codec_write(codec, 0x11, 0,
9169                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9170 }
9171
9172 static void r3di_pre_dsp_setup(struct hda_codec *codec)
9173 {
9174         chipio_write(codec, 0x18b0a4, 0x000000c2);
9175
9176         chipio_8051_write_exram(codec, 0x1c1e, 0x5b);
9177         chipio_8051_write_exram(codec, 0x1920, 0x00);
9178         chipio_8051_write_exram(codec, 0x1921, 0x40);
9179
9180         snd_hda_codec_write(codec, 0x11, 0,
9181                         AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
9182 }
9183
9184 /*
9185  * The ZxR seems to use alternative DAC's for the surround channels, which
9186  * require PLL PMU setup for the clock rate, I'm guessing. Without setting
9187  * this up, we get no audio out of the surround jacks.
9188  */
9189 static void zxr_pre_dsp_setup(struct hda_codec *codec)
9190 {
9191         static const unsigned int addr[] = { 0x43, 0x40, 0x41, 0x42, 0x45 };
9192         static const unsigned int data[] = { 0x08, 0x0c, 0x0b, 0x07, 0x0d };
9193         unsigned int i;
9194
9195         chipio_write(codec, 0x189000, 0x0001f100);
9196         msleep(50);
9197         chipio_write(codec, 0x18900c, 0x0001f100);
9198         msleep(50);
9199
9200         /*
9201          * This writes a RET instruction at the entry point of the function at
9202          * 0xfa92 in exram. This function seems to have something to do with
9203          * ASI. Might be some way to prevent the card from reconfiguring the
9204          * ASI stuff itself.
9205          */
9206         chipio_8051_write_exram(codec, 0xfa92, 0x22);
9207
9208         chipio_8051_write_pll_pmu(codec, 0x51, 0x98);
9209
9210         snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x82);
9211         chipio_set_control_param(codec, CONTROL_PARAM_ASI, 3);
9212
9213         chipio_write(codec, 0x18902c, 0x00000000);
9214         msleep(50);
9215         chipio_write(codec, 0x18902c, 0x00000003);
9216         msleep(50);
9217
9218         for (i = 0; i < ARRAY_SIZE(addr); i++)
9219                 chipio_8051_write_pll_pmu(codec, addr[i], data[i]);
9220 }
9221
9222 /*
9223  * These are sent before the DSP is downloaded. Not sure
9224  * what they do, or if they're necessary. Could possibly
9225  * be removed. Figure they're better to leave in.
9226  */
9227 static const unsigned int ca0113_mmio_init_address_sbz[] = {
9228         0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c,
9229         0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04
9230 };
9231
9232 static const unsigned int ca0113_mmio_init_data_sbz[] = {
9233         0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9234         0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7,
9235         0x000000c1, 0x00000080
9236 };
9237
9238 static const unsigned int ca0113_mmio_init_data_zxr[] = {
9239         0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003,
9240         0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7,
9241         0x000000c1, 0x00000080
9242 };
9243
9244 static const unsigned int ca0113_mmio_init_address_ae5[] = {
9245         0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408,
9246         0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800,
9247         0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c,
9248         0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c
9249 };
9250
9251 static const unsigned int ca0113_mmio_init_data_ae5[] = {
9252         0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9253         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001,
9254         0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f,
9255         0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b,
9256         0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030,
9257         0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9258         0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1,
9259         0x00000080, 0x00880680
9260 };
9261
9262 static void ca0132_mmio_init_sbz(struct hda_codec *codec)
9263 {
9264         struct ca0132_spec *spec = codec->spec;
9265         unsigned int tmp[2], i, count, cur_addr;
9266         const unsigned int *addr, *data;
9267
9268         addr = ca0113_mmio_init_address_sbz;
9269         for (i = 0; i < 3; i++)
9270                 writel(0x00000000, spec->mem_base + addr[i]);
9271
9272         cur_addr = i;
9273         switch (ca0132_quirk(spec)) {
9274         case QUIRK_ZXR:
9275                 tmp[0] = 0x00880480;
9276                 tmp[1] = 0x00000080;
9277                 break;
9278         case QUIRK_SBZ:
9279                 tmp[0] = 0x00820680;
9280                 tmp[1] = 0x00000083;
9281                 break;
9282         case QUIRK_R3D:
9283                 tmp[0] = 0x00880680;
9284                 tmp[1] = 0x00000083;
9285                 break;
9286         default:
9287                 tmp[0] = 0x00000000;
9288                 tmp[1] = 0x00000000;
9289                 break;
9290         }
9291
9292         for (i = 0; i < 2; i++)
9293                 writel(tmp[i], spec->mem_base + addr[cur_addr + i]);
9294
9295         cur_addr += i;
9296
9297         switch (ca0132_quirk(spec)) {
9298         case QUIRK_ZXR:
9299                 count = ARRAY_SIZE(ca0113_mmio_init_data_zxr);
9300                 data = ca0113_mmio_init_data_zxr;
9301                 break;
9302         default:
9303                 count = ARRAY_SIZE(ca0113_mmio_init_data_sbz);
9304                 data = ca0113_mmio_init_data_sbz;
9305                 break;
9306         }
9307
9308         for (i = 0; i < count; i++)
9309                 writel(data[i], spec->mem_base + addr[cur_addr + i]);
9310 }
9311
9312 static void ca0132_mmio_init_ae5(struct hda_codec *codec)
9313 {
9314         struct ca0132_spec *spec = codec->spec;
9315         const unsigned int *addr, *data;
9316         unsigned int i, count;
9317
9318         addr = ca0113_mmio_init_address_ae5;
9319         data = ca0113_mmio_init_data_ae5;
9320         count = ARRAY_SIZE(ca0113_mmio_init_data_ae5);
9321
9322         if (ca0132_quirk(spec) == QUIRK_AE7) {
9323                 writel(0x00000680, spec->mem_base + 0x1c);
9324                 writel(0x00880680, spec->mem_base + 0x1c);
9325         }
9326
9327         for (i = 0; i < count; i++) {
9328                 /*
9329                  * AE-7 shares all writes with the AE-5, except that it writes
9330                  * a different value to 0x20c.
9331                  */
9332                 if (i == 21 && ca0132_quirk(spec) == QUIRK_AE7) {
9333                         writel(0x00800001, spec->mem_base + addr[i]);
9334                         continue;
9335                 }
9336
9337                 writel(data[i], spec->mem_base + addr[i]);
9338         }
9339
9340         if (ca0132_quirk(spec) == QUIRK_AE5)
9341                 writel(0x00880680, spec->mem_base + 0x1c);
9342 }
9343
9344 static void ca0132_mmio_init(struct hda_codec *codec)
9345 {
9346         struct ca0132_spec *spec = codec->spec;
9347
9348         switch (ca0132_quirk(spec)) {
9349         case QUIRK_R3D:
9350         case QUIRK_SBZ:
9351         case QUIRK_ZXR:
9352                 ca0132_mmio_init_sbz(codec);
9353                 break;
9354         case QUIRK_AE5:
9355                 ca0132_mmio_init_ae5(codec);
9356                 break;
9357         default:
9358                 break;
9359         }
9360 }
9361
9362 static const unsigned int ca0132_ae5_register_set_addresses[] = {
9363         0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304,
9364         0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804
9365 };
9366
9367 static const unsigned char ca0132_ae5_register_set_data[] = {
9368         0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b,
9369         0x01, 0x6b, 0x57
9370 };
9371
9372 /*
9373  * This function writes to some SFR's, does some region2 writes, and then
9374  * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
9375  * what it does.
9376  */
9377 static void ae5_register_set(struct hda_codec *codec)
9378 {
9379         struct ca0132_spec *spec = codec->spec;
9380         unsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses);
9381         const unsigned int *addr = ca0132_ae5_register_set_addresses;
9382         const unsigned char *data = ca0132_ae5_register_set_data;
9383         unsigned int i, cur_addr;
9384         unsigned char tmp[3];
9385
9386         if (ca0132_quirk(spec) == QUIRK_AE7)
9387                 chipio_8051_write_pll_pmu(codec, 0x41, 0xc8);
9388
9389         chipio_8051_write_direct(codec, 0x93, 0x10);
9390         chipio_8051_write_pll_pmu(codec, 0x44, 0xc2);
9391
9392         if (ca0132_quirk(spec) == QUIRK_AE7) {
9393                 tmp[0] = 0x03;
9394                 tmp[1] = 0x03;
9395                 tmp[2] = 0x07;
9396         } else {
9397                 tmp[0] = 0x0f;
9398                 tmp[1] = 0x0f;
9399                 tmp[2] = 0x0f;
9400         }
9401
9402         for (i = cur_addr = 0; i < 3; i++, cur_addr++)
9403                 writeb(tmp[i], spec->mem_base + addr[cur_addr]);
9404
9405         /*
9406          * First writes are in single bytes, final are in 4 bytes. So, we use
9407          * writeb, then writel.
9408          */
9409         for (i = 0; cur_addr < 12; i++, cur_addr++)
9410                 writeb(data[i], spec->mem_base + addr[cur_addr]);
9411
9412         for (; cur_addr < count; i++, cur_addr++)
9413                 writel(data[i], spec->mem_base + addr[cur_addr]);
9414
9415         writel(0x00800001, spec->mem_base + 0x20c);
9416
9417         if (ca0132_quirk(spec) == QUIRK_AE7) {
9418                 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
9419                 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
9420         } else {
9421                 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
9422         }
9423
9424         chipio_8051_write_direct(codec, 0x90, 0x00);
9425         chipio_8051_write_direct(codec, 0x90, 0x10);
9426
9427         if (ca0132_quirk(spec) == QUIRK_AE5)
9428                 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
9429 }
9430
9431 /*
9432  * Extra init functions for alternative ca0132 codecs. Done
9433  * here so they don't clutter up the main ca0132_init function
9434  * anymore than they have to.
9435  */
9436 static void ca0132_alt_init(struct hda_codec *codec)
9437 {
9438         struct ca0132_spec *spec = codec->spec;
9439
9440         ca0132_alt_vol_setup(codec);
9441
9442         switch (ca0132_quirk(spec)) {
9443         case QUIRK_SBZ:
9444                 codec_dbg(codec, "SBZ alt_init");
9445                 ca0132_gpio_init(codec);
9446                 sbz_pre_dsp_setup(codec);
9447                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9448                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9449                 break;
9450         case QUIRK_R3DI:
9451                 codec_dbg(codec, "R3DI alt_init");
9452                 ca0132_gpio_init(codec);
9453                 ca0132_gpio_setup(codec);
9454                 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
9455                 r3di_pre_dsp_setup(codec);
9456                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9457                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
9458                 break;
9459         case QUIRK_R3D:
9460                 r3d_pre_dsp_setup(codec);
9461                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9462                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9463                 break;
9464         case QUIRK_AE5:
9465                 ca0132_gpio_init(codec);
9466                 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9467                 chipio_write(codec, 0x18b030, 0x00000020);
9468                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9469                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9470                 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9471                 break;
9472         case QUIRK_AE7:
9473                 ca0132_gpio_init(codec);
9474                 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9475                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9476                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9477                 chipio_write(codec, 0x18b008, 0x000000f8);
9478                 chipio_write(codec, 0x18b008, 0x000000f0);
9479                 chipio_write(codec, 0x18b030, 0x00000020);
9480                 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9481                 break;
9482         case QUIRK_ZXR:
9483                 chipio_8051_write_pll_pmu(codec, 0x49, 0x88);
9484                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9485                 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9486                 zxr_pre_dsp_setup(codec);
9487                 break;
9488         default:
9489                 break;
9490         }
9491 }
9492
9493 static int ca0132_init(struct hda_codec *codec)
9494 {
9495         struct ca0132_spec *spec = codec->spec;
9496         struct auto_pin_cfg *cfg = &spec->autocfg;
9497         int i;
9498         bool dsp_loaded;
9499
9500         /*
9501          * If the DSP is already downloaded, and init has been entered again,
9502          * there's only two reasons for it. One, the codec has awaken from a
9503          * suspended state, and in that case dspload_is_loaded will return
9504          * false, and the init will be ran again. The other reason it gets
9505          * re entered is on startup for some reason it triggers a suspend and
9506          * resume state. In this case, it will check if the DSP is downloaded,
9507          * and not run the init function again. For codecs using alt_functions,
9508          * it will check if the DSP is loaded properly.
9509          */
9510         if (spec->dsp_state == DSP_DOWNLOADED) {
9511                 dsp_loaded = dspload_is_loaded(codec);
9512                 if (!dsp_loaded) {
9513                         spec->dsp_reload = true;
9514                         spec->dsp_state = DSP_DOWNLOAD_INIT;
9515                 } else {
9516                         if (ca0132_quirk(spec) == QUIRK_SBZ)
9517                                 sbz_dsp_startup_check(codec);
9518                         return 0;
9519                 }
9520         }
9521
9522         if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
9523                 spec->dsp_state = DSP_DOWNLOAD_INIT;
9524         spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
9525
9526         if (ca0132_use_pci_mmio(spec))
9527                 ca0132_mmio_init(codec);
9528
9529         snd_hda_power_up_pm(codec);
9530
9531         if (ca0132_quirk(spec) == QUIRK_AE5 || ca0132_quirk(spec) == QUIRK_AE7)
9532                 ae5_register_set(codec);
9533
9534         ca0132_init_params(codec);
9535         ca0132_init_flags(codec);
9536
9537         snd_hda_sequence_write(codec, spec->base_init_verbs);
9538
9539         if (ca0132_use_alt_functions(spec))
9540                 ca0132_alt_init(codec);
9541
9542         ca0132_download_dsp(codec);
9543
9544         ca0132_refresh_widget_caps(codec);
9545
9546         switch (ca0132_quirk(spec)) {
9547         case QUIRK_R3DI:
9548         case QUIRK_R3D:
9549                 r3d_setup_defaults(codec);
9550                 break;
9551         case QUIRK_SBZ:
9552         case QUIRK_ZXR:
9553                 sbz_setup_defaults(codec);
9554                 break;
9555         case QUIRK_AE5:
9556                 ae5_setup_defaults(codec);
9557                 break;
9558         case QUIRK_AE7:
9559                 ae7_setup_defaults(codec);
9560                 break;
9561         default:
9562                 ca0132_setup_defaults(codec);
9563                 ca0132_init_analog_mic2(codec);
9564                 ca0132_init_dmic(codec);
9565                 break;
9566         }
9567
9568         for (i = 0; i < spec->num_outputs; i++)
9569                 init_output(codec, spec->out_pins[i], spec->dacs[0]);
9570
9571         init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9572
9573         for (i = 0; i < spec->num_inputs; i++)
9574                 init_input(codec, spec->input_pins[i], spec->adcs[i]);
9575
9576         init_input(codec, cfg->dig_in_pin, spec->dig_in);
9577
9578         if (!ca0132_use_alt_functions(spec)) {
9579                 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9580                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9581                             VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
9582                 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9583                             VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
9584         }
9585
9586         if (ca0132_quirk(spec) == QUIRK_SBZ)
9587                 ca0132_gpio_setup(codec);
9588
9589         snd_hda_sequence_write(codec, spec->spec_init_verbs);
9590         if (ca0132_use_alt_functions(spec)) {
9591                 ca0132_alt_select_out(codec);
9592                 ca0132_alt_select_in(codec);
9593         } else {
9594                 ca0132_select_out(codec);
9595                 ca0132_select_mic(codec);
9596         }
9597
9598         snd_hda_jack_report_sync(codec);
9599
9600         /*
9601          * Re set the PlayEnhancement switch on a resume event, because the
9602          * controls will not be reloaded.
9603          */
9604         if (spec->dsp_reload) {
9605                 spec->dsp_reload = false;
9606                 ca0132_pe_switch_set(codec);
9607         }
9608
9609         snd_hda_power_down_pm(codec);
9610
9611         return 0;
9612 }
9613
9614 static int dbpro_init(struct hda_codec *codec)
9615 {
9616         struct ca0132_spec *spec = codec->spec;
9617         struct auto_pin_cfg *cfg = &spec->autocfg;
9618         unsigned int i;
9619
9620         init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9621         init_input(codec, cfg->dig_in_pin, spec->dig_in);
9622
9623         for (i = 0; i < spec->num_inputs; i++)
9624                 init_input(codec, spec->input_pins[i], spec->adcs[i]);
9625
9626         return 0;
9627 }
9628
9629 static void ca0132_free(struct hda_codec *codec)
9630 {
9631         struct ca0132_spec *spec = codec->spec;
9632
9633         cancel_delayed_work_sync(&spec->unsol_hp_work);
9634         snd_hda_power_up(codec);
9635         switch (ca0132_quirk(spec)) {
9636         case QUIRK_SBZ:
9637                 sbz_exit_chip(codec);
9638                 break;
9639         case QUIRK_ZXR:
9640                 zxr_exit_chip(codec);
9641                 break;
9642         case QUIRK_R3D:
9643                 r3d_exit_chip(codec);
9644                 break;
9645         case QUIRK_AE5:
9646                 ae5_exit_chip(codec);
9647                 break;
9648         case QUIRK_AE7:
9649                 ae7_exit_chip(codec);
9650                 break;
9651         case QUIRK_R3DI:
9652                 r3di_gpio_shutdown(codec);
9653                 break;
9654         default:
9655                 break;
9656         }
9657
9658         snd_hda_sequence_write(codec, spec->base_exit_verbs);
9659         ca0132_exit_chip(codec);
9660
9661         snd_hda_power_down(codec);
9662 #ifdef CONFIG_PCI
9663         if (spec->mem_base)
9664                 pci_iounmap(codec->bus->pci, spec->mem_base);
9665 #endif
9666         kfree(spec->spec_init_verbs);
9667         kfree(codec->spec);
9668 }
9669
9670 static void dbpro_free(struct hda_codec *codec)
9671 {
9672         struct ca0132_spec *spec = codec->spec;
9673
9674         zxr_dbpro_power_state_shutdown(codec);
9675
9676         kfree(spec->spec_init_verbs);
9677         kfree(codec->spec);
9678 }
9679
9680 #ifdef CONFIG_PM
9681 static int ca0132_suspend(struct hda_codec *codec)
9682 {
9683         struct ca0132_spec *spec = codec->spec;
9684
9685         cancel_delayed_work_sync(&spec->unsol_hp_work);
9686         return 0;
9687 }
9688 #endif
9689
9690 static const struct hda_codec_ops ca0132_patch_ops = {
9691         .build_controls = ca0132_build_controls,
9692         .build_pcms = ca0132_build_pcms,
9693         .init = ca0132_init,
9694         .free = ca0132_free,
9695         .unsol_event = snd_hda_jack_unsol_event,
9696 #ifdef CONFIG_PM
9697         .suspend = ca0132_suspend,
9698 #endif
9699 };
9700
9701 static const struct hda_codec_ops dbpro_patch_ops = {
9702         .build_controls = dbpro_build_controls,
9703         .build_pcms = dbpro_build_pcms,
9704         .init = dbpro_init,
9705         .free = dbpro_free,
9706 };
9707
9708 static void ca0132_config(struct hda_codec *codec)
9709 {
9710         struct ca0132_spec *spec = codec->spec;
9711
9712         spec->dacs[0] = 0x2;
9713         spec->dacs[1] = 0x3;
9714         spec->dacs[2] = 0x4;
9715
9716         spec->multiout.dac_nids = spec->dacs;
9717         spec->multiout.num_dacs = 3;
9718
9719         if (!ca0132_use_alt_functions(spec))
9720                 spec->multiout.max_channels = 2;
9721         else
9722                 spec->multiout.max_channels = 6;
9723
9724         switch (ca0132_quirk(spec)) {
9725         case QUIRK_ALIENWARE:
9726                 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
9727                 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
9728                 break;
9729         case QUIRK_SBZ:
9730                 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
9731                 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
9732                 break;
9733         case QUIRK_ZXR:
9734                 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__);
9735                 snd_hda_apply_pincfgs(codec, zxr_pincfgs);
9736                 break;
9737         case QUIRK_R3D:
9738                 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
9739                 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
9740                 break;
9741         case QUIRK_R3DI:
9742                 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
9743                 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
9744                 break;
9745         case QUIRK_AE5:
9746                 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
9747                 snd_hda_apply_pincfgs(codec, ae5_pincfgs);
9748                 break;
9749         case QUIRK_AE7:
9750                 codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__);
9751                 snd_hda_apply_pincfgs(codec, ae7_pincfgs);
9752                 break;
9753         default:
9754                 break;
9755         }
9756
9757         switch (ca0132_quirk(spec)) {
9758         case QUIRK_ALIENWARE:
9759                 spec->num_outputs = 2;
9760                 spec->out_pins[0] = 0x0b; /* speaker out */
9761                 spec->out_pins[1] = 0x0f;
9762                 spec->shared_out_nid = 0x2;
9763                 spec->unsol_tag_hp = 0x0f;
9764
9765                 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9766                 spec->adcs[1] = 0x8; /* analog mic2 */
9767                 spec->adcs[2] = 0xa; /* what u hear */
9768
9769                 spec->num_inputs = 3;
9770                 spec->input_pins[0] = 0x12;
9771                 spec->input_pins[1] = 0x11;
9772                 spec->input_pins[2] = 0x13;
9773                 spec->shared_mic_nid = 0x7;
9774                 spec->unsol_tag_amic1 = 0x11;
9775                 break;
9776         case QUIRK_SBZ:
9777         case QUIRK_R3D:
9778                 spec->num_outputs = 2;
9779                 spec->out_pins[0] = 0x0B; /* Line out */
9780                 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9781                 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9782                 spec->out_pins[3] = 0x11; /* Rear surround */
9783                 spec->shared_out_nid = 0x2;
9784                 spec->unsol_tag_hp = spec->out_pins[1];
9785                 spec->unsol_tag_front_hp = spec->out_pins[2];
9786
9787                 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9788                 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9789                 spec->adcs[2] = 0xa; /* what u hear */
9790
9791                 spec->num_inputs = 2;
9792                 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9793                 spec->input_pins[1] = 0x13; /* What U Hear */
9794                 spec->shared_mic_nid = 0x7;
9795                 spec->unsol_tag_amic1 = spec->input_pins[0];
9796
9797                 /* SPDIF I/O */
9798                 spec->dig_out = 0x05;
9799                 spec->multiout.dig_out_nid = spec->dig_out;
9800                 spec->dig_in = 0x09;
9801                 break;
9802         case QUIRK_ZXR:
9803                 spec->num_outputs = 2;
9804                 spec->out_pins[0] = 0x0B; /* Line out */
9805                 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9806                 spec->out_pins[2] = 0x10; /* Center/LFE */
9807                 spec->out_pins[3] = 0x11; /* Rear surround */
9808                 spec->shared_out_nid = 0x2;
9809                 spec->unsol_tag_hp = spec->out_pins[1];
9810                 spec->unsol_tag_front_hp = spec->out_pins[2];
9811
9812                 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9813                 spec->adcs[1] = 0x8; /* Not connected, no front mic */
9814                 spec->adcs[2] = 0xa; /* what u hear */
9815
9816                 spec->num_inputs = 2;
9817                 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9818                 spec->input_pins[1] = 0x13; /* What U Hear */
9819                 spec->shared_mic_nid = 0x7;
9820                 spec->unsol_tag_amic1 = spec->input_pins[0];
9821                 break;
9822         case QUIRK_ZXR_DBPRO:
9823                 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */
9824
9825                 spec->num_inputs = 1;
9826                 spec->input_pins[0] = 0x11; /* RCA Line-in */
9827
9828                 spec->dig_out = 0x05;
9829                 spec->multiout.dig_out_nid = spec->dig_out;
9830
9831                 spec->dig_in = 0x09;
9832                 break;
9833         case QUIRK_AE5:
9834         case QUIRK_AE7:
9835                 spec->num_outputs = 2;
9836                 spec->out_pins[0] = 0x0B; /* Line out */
9837                 spec->out_pins[1] = 0x11; /* Rear headphone out */
9838                 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9839                 spec->out_pins[3] = 0x0F; /* Rear surround */
9840                 spec->shared_out_nid = 0x2;
9841                 spec->unsol_tag_hp = spec->out_pins[1];
9842                 spec->unsol_tag_front_hp = spec->out_pins[2];
9843
9844                 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9845                 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9846                 spec->adcs[2] = 0xa; /* what u hear */
9847
9848                 spec->num_inputs = 2;
9849                 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9850                 spec->input_pins[1] = 0x13; /* What U Hear */
9851                 spec->shared_mic_nid = 0x7;
9852                 spec->unsol_tag_amic1 = spec->input_pins[0];
9853
9854                 /* SPDIF I/O */
9855                 spec->dig_out = 0x05;
9856                 spec->multiout.dig_out_nid = spec->dig_out;
9857                 break;
9858         case QUIRK_R3DI:
9859                 spec->num_outputs = 2;
9860                 spec->out_pins[0] = 0x0B; /* Line out */
9861                 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9862                 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9863                 spec->out_pins[3] = 0x11; /* Rear surround */
9864                 spec->shared_out_nid = 0x2;
9865                 spec->unsol_tag_hp = spec->out_pins[1];
9866                 spec->unsol_tag_front_hp = spec->out_pins[2];
9867
9868                 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
9869                 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
9870                 spec->adcs[2] = 0x0a; /* what u hear */
9871
9872                 spec->num_inputs = 2;
9873                 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9874                 spec->input_pins[1] = 0x13; /* What U Hear */
9875                 spec->shared_mic_nid = 0x7;
9876                 spec->unsol_tag_amic1 = spec->input_pins[0];
9877
9878                 /* SPDIF I/O */
9879                 spec->dig_out = 0x05;
9880                 spec->multiout.dig_out_nid = spec->dig_out;
9881                 break;
9882         default:
9883                 spec->num_outputs = 2;
9884                 spec->out_pins[0] = 0x0b; /* speaker out */
9885                 spec->out_pins[1] = 0x10; /* headphone out */
9886                 spec->shared_out_nid = 0x2;
9887                 spec->unsol_tag_hp = spec->out_pins[1];
9888
9889                 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9890                 spec->adcs[1] = 0x8; /* analog mic2 */
9891                 spec->adcs[2] = 0xa; /* what u hear */
9892
9893                 spec->num_inputs = 3;
9894                 spec->input_pins[0] = 0x12;
9895                 spec->input_pins[1] = 0x11;
9896                 spec->input_pins[2] = 0x13;
9897                 spec->shared_mic_nid = 0x7;
9898                 spec->unsol_tag_amic1 = spec->input_pins[0];
9899
9900                 /* SPDIF I/O */
9901                 spec->dig_out = 0x05;
9902                 spec->multiout.dig_out_nid = spec->dig_out;
9903                 spec->dig_in = 0x09;
9904                 break;
9905         }
9906 }
9907
9908 static int ca0132_prepare_verbs(struct hda_codec *codec)
9909 {
9910 /* Verbs + terminator (an empty element) */
9911 #define NUM_SPEC_VERBS 2
9912         struct ca0132_spec *spec = codec->spec;
9913
9914         spec->chip_init_verbs = ca0132_init_verbs0;
9915         /*
9916          * Since desktop cards use pci_mmio, this can be used to determine
9917          * whether or not to use these verbs instead of a separate bool.
9918          */
9919         if (ca0132_use_pci_mmio(spec))
9920                 spec->desktop_init_verbs = ca0132_init_verbs1;
9921         spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
9922                                         sizeof(struct hda_verb),
9923                                         GFP_KERNEL);
9924         if (!spec->spec_init_verbs)
9925                 return -ENOMEM;
9926
9927         /* config EAPD */
9928         spec->spec_init_verbs[0].nid = 0x0b;
9929         spec->spec_init_verbs[0].param = 0x78D;
9930         spec->spec_init_verbs[0].verb = 0x00;
9931
9932         /* Previously commented configuration */
9933         /*
9934         spec->spec_init_verbs[2].nid = 0x0b;
9935         spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
9936         spec->spec_init_verbs[2].verb = 0x02;
9937
9938         spec->spec_init_verbs[3].nid = 0x10;
9939         spec->spec_init_verbs[3].param = 0x78D;
9940         spec->spec_init_verbs[3].verb = 0x02;
9941
9942         spec->spec_init_verbs[4].nid = 0x10;
9943         spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
9944         spec->spec_init_verbs[4].verb = 0x02;
9945         */
9946
9947         /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
9948         return 0;
9949 }
9950
9951 /*
9952  * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular
9953  * Sound Blaster Z cards. However, they have different HDA codec subsystem
9954  * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro
9955  * daughter boards ID.
9956  */
9957 static void sbz_detect_quirk(struct hda_codec *codec)
9958 {
9959         struct ca0132_spec *spec = codec->spec;
9960
9961         switch (codec->core.subsystem_id) {
9962         case 0x11020033:
9963                 spec->quirk = QUIRK_ZXR;
9964                 break;
9965         case 0x1102003f:
9966                 spec->quirk = QUIRK_ZXR_DBPRO;
9967                 break;
9968         default:
9969                 spec->quirk = QUIRK_SBZ;
9970                 break;
9971         }
9972 }
9973
9974 static int patch_ca0132(struct hda_codec *codec)
9975 {
9976         struct ca0132_spec *spec;
9977         int err;
9978         const struct snd_pci_quirk *quirk;
9979
9980         codec_dbg(codec, "patch_ca0132\n");
9981
9982         spec = kzalloc(sizeof(*spec), GFP_KERNEL);
9983         if (!spec)
9984                 return -ENOMEM;
9985         codec->spec = spec;
9986         spec->codec = codec;
9987
9988         /* Detect codec quirk */
9989         quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
9990         if (quirk)
9991                 spec->quirk = quirk->value;
9992         else
9993                 spec->quirk = QUIRK_NONE;
9994         if (ca0132_quirk(spec) == QUIRK_SBZ)
9995                 sbz_detect_quirk(codec);
9996
9997         if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO)
9998                 codec->patch_ops = dbpro_patch_ops;
9999         else
10000                 codec->patch_ops = ca0132_patch_ops;
10001
10002         codec->pcm_format_first = 1;
10003         codec->no_sticky_stream = 1;
10004
10005
10006         spec->dsp_state = DSP_DOWNLOAD_INIT;
10007         spec->num_mixers = 1;
10008
10009         /* Set which mixers each quirk uses. */
10010         switch (ca0132_quirk(spec)) {
10011         case QUIRK_SBZ:
10012                 spec->mixers[0] = desktop_mixer;
10013                 snd_hda_codec_set_name(codec, "Sound Blaster Z");
10014                 break;
10015         case QUIRK_ZXR:
10016                 spec->mixers[0] = desktop_mixer;
10017                 snd_hda_codec_set_name(codec, "Sound Blaster ZxR");
10018                 break;
10019         case QUIRK_ZXR_DBPRO:
10020                 break;
10021         case QUIRK_R3D:
10022                 spec->mixers[0] = desktop_mixer;
10023                 snd_hda_codec_set_name(codec, "Recon3D");
10024                 break;
10025         case QUIRK_R3DI:
10026                 spec->mixers[0] = r3di_mixer;
10027                 snd_hda_codec_set_name(codec, "Recon3Di");
10028                 break;
10029         case QUIRK_AE5:
10030                 spec->mixers[0] = desktop_mixer;
10031                 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
10032                 break;
10033         case QUIRK_AE7:
10034                 spec->mixers[0] = desktop_mixer;
10035                 snd_hda_codec_set_name(codec, "Sound Blaster AE-7");
10036                 break;
10037         default:
10038                 spec->mixers[0] = ca0132_mixer;
10039                 break;
10040         }
10041
10042         /* Setup whether or not to use alt functions/controls/pci_mmio */
10043         switch (ca0132_quirk(spec)) {
10044         case QUIRK_SBZ:
10045         case QUIRK_R3D:
10046         case QUIRK_AE5:
10047         case QUIRK_AE7:
10048         case QUIRK_ZXR:
10049                 spec->use_alt_controls = true;
10050                 spec->use_alt_functions = true;
10051                 spec->use_pci_mmio = true;
10052                 break;
10053         case QUIRK_R3DI:
10054                 spec->use_alt_controls = true;
10055                 spec->use_alt_functions = true;
10056                 spec->use_pci_mmio = false;
10057                 break;
10058         default:
10059                 spec->use_alt_controls = false;
10060                 spec->use_alt_functions = false;
10061                 spec->use_pci_mmio = false;
10062                 break;
10063         }
10064
10065 #ifdef CONFIG_PCI
10066         if (spec->use_pci_mmio) {
10067                 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
10068                 if (spec->mem_base == NULL) {
10069                         codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
10070                         spec->quirk = QUIRK_NONE;
10071                 }
10072         }
10073 #endif
10074
10075         spec->base_init_verbs = ca0132_base_init_verbs;
10076         spec->base_exit_verbs = ca0132_base_exit_verbs;
10077
10078         INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
10079
10080         ca0132_init_chip(codec);
10081
10082         ca0132_config(codec);
10083
10084         err = ca0132_prepare_verbs(codec);
10085         if (err < 0)
10086                 goto error;
10087
10088         err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
10089         if (err < 0)
10090                 goto error;
10091
10092         ca0132_setup_unsol(codec);
10093
10094         return 0;
10095
10096  error:
10097         ca0132_free(codec);
10098         return err;
10099 }
10100
10101 /*
10102  * patch entries
10103  */
10104 static const struct hda_device_id snd_hda_id_ca0132[] = {
10105         HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
10106         {} /* terminator */
10107 };
10108 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
10109
10110 MODULE_LICENSE("GPL");
10111 MODULE_DESCRIPTION("Creative Sound Core3D codec");
10112
10113 static struct hda_codec_driver ca0132_driver = {
10114         .id = snd_hda_id_ca0132,
10115 };
10116
10117 module_hda_codec_driver(ca0132_driver);