1 // SPDX-License-Identifier: GPL-2.0-only
4 * Implementation of primary ALSA driver code base for NVIDIA Tegra HDA.
8 #include <linux/clocksource.h>
9 #include <linux/completion.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/mutex.h>
19 #include <linux/of_device.h>
20 #include <linux/reset.h>
21 #include <linux/slab.h>
22 #include <linux/time.h>
23 #include <linux/string.h>
24 #include <linux/pm_runtime.h>
26 #include <sound/core.h>
27 #include <sound/initval.h>
29 #include <sound/hda_codec.h>
30 #include "hda_controller.h"
32 /* Defines for Nvidia Tegra HDA support */
33 #define HDA_BAR0 0x8000
35 #define HDA_CFG_CMD 0x1004
36 #define HDA_CFG_BAR0 0x1010
38 #define HDA_ENABLE_IO_SPACE (1 << 0)
39 #define HDA_ENABLE_MEM_SPACE (1 << 1)
40 #define HDA_ENABLE_BUS_MASTER (1 << 2)
41 #define HDA_ENABLE_SERR (1 << 8)
42 #define HDA_DISABLE_INTR (1 << 10)
43 #define HDA_BAR0_INIT_PROGRAM 0xFFFFFFFF
44 #define HDA_BAR0_FINAL_PROGRAM (1 << 14)
47 #define HDA_IPFS_CONFIG 0x180
48 #define HDA_IPFS_EN_FPCI 0x1
50 #define HDA_IPFS_FPCI_BAR0 0x80
51 #define HDA_FPCI_BAR0_START 0x40
53 #define HDA_IPFS_INTR_MASK 0x188
54 #define HDA_IPFS_EN_INTR (1 << 16)
57 #define FPCI_DBG_CFG_2 0x10F4
58 #define FPCI_GCAP_NSDO_SHIFT 18
59 #define FPCI_GCAP_NSDO_MASK (0x3 << FPCI_GCAP_NSDO_SHIFT)
61 /* max number of SDs */
62 #define NUM_CAPTURE_SD 1
63 #define NUM_PLAYBACK_SD 1
66 * Tegra194 does not reflect correct number of SDO lines. Below macro
67 * is used to update the GCAP register to workaround the issue.
69 #define TEGRA194_NUM_SDO_LINES 4
71 struct hda_tegra_soc {
72 bool has_hda2codec_2x_reset;
79 struct reset_control_bulk_data resets[3];
80 struct clk_bulk_data clocks[3];
84 struct work_struct probe_work;
85 const struct hda_tegra_soc *soc;
89 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
90 module_param(power_save, bint, 0644);
91 MODULE_PARM_DESC(power_save,
92 "Automatic power-saving timeout (in seconds, 0 = disable).");
97 static const struct hda_controller_ops hda_tegra_ops; /* nothing special */
99 static void hda_tegra_init(struct hda_tegra *hda)
103 /* Enable PCI access */
104 v = readl(hda->regs + HDA_IPFS_CONFIG);
105 v |= HDA_IPFS_EN_FPCI;
106 writel(v, hda->regs + HDA_IPFS_CONFIG);
108 /* Enable MEM/IO space and bus master */
109 v = readl(hda->regs + HDA_CFG_CMD);
110 v &= ~HDA_DISABLE_INTR;
111 v |= HDA_ENABLE_MEM_SPACE | HDA_ENABLE_IO_SPACE |
112 HDA_ENABLE_BUS_MASTER | HDA_ENABLE_SERR;
113 writel(v, hda->regs + HDA_CFG_CMD);
115 writel(HDA_BAR0_INIT_PROGRAM, hda->regs + HDA_CFG_BAR0);
116 writel(HDA_BAR0_FINAL_PROGRAM, hda->regs + HDA_CFG_BAR0);
117 writel(HDA_FPCI_BAR0_START, hda->regs + HDA_IPFS_FPCI_BAR0);
119 v = readl(hda->regs + HDA_IPFS_INTR_MASK);
120 v |= HDA_IPFS_EN_INTR;
121 writel(v, hda->regs + HDA_IPFS_INTR_MASK);
127 static int __maybe_unused hda_tegra_suspend(struct device *dev)
129 struct snd_card *card = dev_get_drvdata(dev);
132 rc = pm_runtime_force_suspend(dev);
135 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
140 static int __maybe_unused hda_tegra_resume(struct device *dev)
142 struct snd_card *card = dev_get_drvdata(dev);
145 rc = pm_runtime_force_resume(dev);
148 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
153 static int __maybe_unused hda_tegra_runtime_suspend(struct device *dev)
155 struct snd_card *card = dev_get_drvdata(dev);
156 struct azx *chip = card->private_data;
157 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
159 if (chip && chip->running) {
160 /* enable controller wake up event */
161 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
165 azx_enter_link_reset(chip);
167 clk_bulk_disable_unprepare(hda->nclocks, hda->clocks);
172 static int __maybe_unused hda_tegra_runtime_resume(struct device *dev)
174 struct snd_card *card = dev_get_drvdata(dev);
175 struct azx *chip = card->private_data;
176 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
179 if (!chip->running) {
180 rc = reset_control_bulk_assert(hda->nresets, hda->resets);
185 rc = clk_bulk_prepare_enable(hda->nclocks, hda->clocks);
190 azx_init_chip(chip, 1);
191 /* disable controller wake up event*/
192 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
195 usleep_range(10, 100);
197 rc = reset_control_bulk_deassert(hda->nresets, hda->resets);
205 static const struct dev_pm_ops hda_tegra_pm = {
206 SET_SYSTEM_SLEEP_PM_OPS(hda_tegra_suspend, hda_tegra_resume)
207 SET_RUNTIME_PM_OPS(hda_tegra_runtime_suspend,
208 hda_tegra_runtime_resume,
212 static int hda_tegra_dev_disconnect(struct snd_device *device)
214 struct azx *chip = device->device_data;
216 chip->bus.shutdown = 1;
223 static int hda_tegra_dev_free(struct snd_device *device)
225 struct azx *chip = device->device_data;
226 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
228 cancel_work_sync(&hda->probe_work);
229 if (azx_bus(chip)->chip_init) {
230 azx_stop_all_streams(chip);
234 azx_free_stream_pages(chip);
235 azx_free_streams(chip);
236 snd_hdac_bus_exit(azx_bus(chip));
241 static int hda_tegra_init_chip(struct azx *chip, struct platform_device *pdev)
243 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
244 struct hdac_bus *bus = azx_bus(chip);
245 struct resource *res;
247 hda->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
248 if (IS_ERR(hda->regs))
249 return PTR_ERR(hda->regs);
251 bus->remap_addr = hda->regs + HDA_BAR0;
252 bus->addr = res->start + HDA_BAR0;
259 static int hda_tegra_first_init(struct azx *chip, struct platform_device *pdev)
261 struct hda_tegra *hda = container_of(chip, struct hda_tegra, chip);
262 struct hdac_bus *bus = azx_bus(chip);
263 struct snd_card *card = chip->card;
266 int irq_id = platform_get_irq(pdev, 0);
267 const char *sname, *drv_name = "tegra-hda";
268 struct device_node *np = pdev->dev.of_node;
273 err = hda_tegra_init_chip(chip, pdev);
277 err = devm_request_irq(chip->card->dev, irq_id, azx_interrupt,
278 IRQF_SHARED, KBUILD_MODNAME, chip);
280 dev_err(chip->card->dev,
281 "unable to request IRQ %d, disabling device\n",
286 bus->dma_stop_delay = 100;
287 card->sync_irq = bus->irq;
290 * Tegra194 has 4 SDO lines and the STRIPE can be used to
291 * indicate how many of the SDO lines the stream should be
292 * striped. But GCAP register does not reflect the true
293 * capability of HW. Below workaround helps to fix this.
295 * GCAP_NSDO is bits 19:18 in T_AZA_DBG_CFG_2,
296 * 0 for 1 SDO, 1 for 2 SDO, 2 for 4 SDO lines.
298 if (of_device_is_compatible(np, "nvidia,tegra194-hda")) {
301 dev_info(card->dev, "Override SDO lines to %u\n",
302 TEGRA194_NUM_SDO_LINES);
304 val = readl(hda->regs + FPCI_DBG_CFG_2) & ~FPCI_GCAP_NSDO_MASK;
305 val |= (TEGRA194_NUM_SDO_LINES >> 1) << FPCI_GCAP_NSDO_SHIFT;
306 writel(val, hda->regs + FPCI_DBG_CFG_2);
309 gcap = azx_readw(chip, GCAP);
310 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
312 chip->align_buffer_size = 1;
314 /* read number of streams from GCAP register instead of using
317 chip->capture_streams = (gcap >> 8) & 0x0f;
319 /* The GCAP register on Tegra234 implies no Input Streams(ISS) support,
320 * but the HW output stream descriptor programming should start with
321 * offset 0x20*4 from base stream descriptor address. This will be a
322 * problem while calculating the offset for output stream descriptor
323 * which will be considering input stream also. So here output stream
324 * starts with offset 0 which is wrong as HW register for output stream
325 * offset starts with 4.
327 if (of_device_is_compatible(np, "nvidia,tegra234-hda"))
328 chip->capture_streams = 4;
330 chip->playback_streams = (gcap >> 12) & 0x0f;
331 if (!chip->playback_streams && !chip->capture_streams) {
332 /* gcap didn't give any info, switching to old method */
333 chip->playback_streams = NUM_PLAYBACK_SD;
334 chip->capture_streams = NUM_CAPTURE_SD;
336 chip->capture_index_offset = 0;
337 chip->playback_index_offset = chip->capture_streams;
338 chip->num_streams = chip->playback_streams + chip->capture_streams;
340 /* initialize streams */
341 err = azx_init_streams(chip);
343 dev_err(card->dev, "failed to initialize streams: %d\n", err);
347 err = azx_alloc_stream_pages(chip);
349 dev_err(card->dev, "failed to allocate stream pages: %d\n",
354 /* initialize chip */
355 azx_init_chip(chip, 1);
358 * Playback (for 44.1K/48K, 2-channel, 16-bps) fails with
359 * 4 SDO lines due to legacy design limitation. Following
360 * is, from HD Audio Specification (Revision 1.0a), used to
361 * control striping of the stream across multiple SDO lines
362 * for sample rates <= 48K.
364 * { ((num_channels * bits_per_sample) / number of SDOs) >= 8 }
366 * Due to legacy design issue it is recommended that above
367 * ratio must be greater than 8. Since number of SDO lines is
368 * in powers of 2, next available ratio is 16 which can be
369 * used as a limiting factor here.
371 if (of_device_is_compatible(np, "nvidia,tegra30-hda"))
372 chip->bus.core.sdo_limit = 16;
374 /* codec detection */
375 if (!bus->codec_mask) {
376 dev_err(card->dev, "no codecs found!\n");
381 strncpy(card->driver, drv_name, sizeof(card->driver));
382 /* shortname for card */
383 sname = of_get_property(np, "nvidia,model", NULL);
386 if (strlen(sname) > sizeof(card->shortname))
387 dev_info(card->dev, "truncating shortname for card\n");
388 strncpy(card->shortname, sname, sizeof(card->shortname));
390 /* longname for card */
391 snprintf(card->longname, sizeof(card->longname),
392 "%s at 0x%lx irq %i",
393 card->shortname, bus->addr, bus->irq);
402 static void hda_tegra_probe_work(struct work_struct *work);
404 static int hda_tegra_create(struct snd_card *card,
405 unsigned int driver_caps,
406 struct hda_tegra *hda)
408 static const struct snd_device_ops ops = {
409 .dev_disconnect = hda_tegra_dev_disconnect,
410 .dev_free = hda_tegra_dev_free,
417 mutex_init(&chip->open_mutex);
419 chip->ops = &hda_tegra_ops;
420 chip->driver_caps = driver_caps;
421 chip->driver_type = driver_caps & 0xff;
423 chip->jackpoll_interval = msecs_to_jiffies(5000);
424 INIT_LIST_HEAD(&chip->pcm_list);
426 chip->codec_probe_mask = -1;
428 chip->single_cmd = false;
431 INIT_WORK(&hda->probe_work, hda_tegra_probe_work);
433 err = azx_bus_init(chip, NULL);
437 chip->bus.core.sync_write = 0;
438 chip->bus.core.needs_damn_long_delay = 1;
439 chip->bus.core.aligned_mmio = 1;
440 chip->bus.jackpoll_in_suspend = 1;
442 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
444 dev_err(card->dev, "Error creating device\n");
451 static const struct hda_tegra_soc tegra30_data = {
452 .has_hda2codec_2x_reset = true,
453 .has_hda2hdmi = true,
456 static const struct hda_tegra_soc tegra194_data = {
457 .has_hda2codec_2x_reset = false,
458 .has_hda2hdmi = true,
461 static const struct hda_tegra_soc tegra234_data = {
462 .has_hda2codec_2x_reset = true,
463 .has_hda2hdmi = false,
466 static const struct of_device_id hda_tegra_match[] = {
467 { .compatible = "nvidia,tegra30-hda", .data = &tegra30_data },
468 { .compatible = "nvidia,tegra194-hda", .data = &tegra194_data },
469 { .compatible = "nvidia,tegra234-hda", .data = &tegra234_data },
472 MODULE_DEVICE_TABLE(of, hda_tegra_match);
474 static int hda_tegra_probe(struct platform_device *pdev)
476 const unsigned int driver_flags = AZX_DCAPS_CORBRP_SELF_CLEAR |
477 AZX_DCAPS_PM_RUNTIME;
478 struct snd_card *card;
480 struct hda_tegra *hda;
483 hda = devm_kzalloc(&pdev->dev, sizeof(*hda), GFP_KERNEL);
486 hda->dev = &pdev->dev;
489 hda->soc = of_device_get_match_data(&pdev->dev);
491 err = snd_card_new(&pdev->dev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
492 THIS_MODULE, 0, &card);
494 dev_err(&pdev->dev, "Error creating card!\n");
498 hda->resets[hda->nresets++].id = "hda";
501 * "hda2hdmi" is not applicable for Tegra234. This is because the
502 * codec is separate IP and not under display SOR partition now.
504 if (hda->soc->has_hda2hdmi)
505 hda->resets[hda->nresets++].id = "hda2hdmi";
508 * "hda2codec_2x" reset is not present on Tegra194. Though DT would
509 * be updated to reflect this, but to have backward compatibility
510 * below is necessary.
512 if (hda->soc->has_hda2codec_2x_reset)
513 hda->resets[hda->nresets++].id = "hda2codec_2x";
515 err = devm_reset_control_bulk_get_exclusive(&pdev->dev, hda->nresets,
520 hda->clocks[hda->nclocks++].id = "hda";
521 if (hda->soc->has_hda2hdmi)
522 hda->clocks[hda->nclocks++].id = "hda2hdmi";
523 hda->clocks[hda->nclocks++].id = "hda2codec_2x";
525 err = devm_clk_bulk_get(&pdev->dev, hda->nclocks, hda->clocks);
529 err = hda_tegra_create(card, driver_flags, hda);
532 card->private_data = chip;
534 dev_set_drvdata(&pdev->dev, card);
536 pm_runtime_enable(hda->dev);
537 if (!azx_has_pm_runtime(chip))
538 pm_runtime_forbid(hda->dev);
540 schedule_work(&hda->probe_work);
549 static void hda_tegra_probe_work(struct work_struct *work)
551 struct hda_tegra *hda = container_of(work, struct hda_tegra, probe_work);
552 struct azx *chip = &hda->chip;
553 struct platform_device *pdev = to_platform_device(hda->dev);
556 pm_runtime_get_sync(hda->dev);
557 err = hda_tegra_first_init(chip, pdev);
561 /* create codec instances */
562 err = azx_probe_codecs(chip, 8);
566 err = azx_codec_configure(chip);
570 err = snd_card_register(chip->card);
575 snd_hda_set_power_save(&chip->bus, power_save * 1000);
578 pm_runtime_put(hda->dev);
579 return; /* no error return from async probe */
582 static int hda_tegra_remove(struct platform_device *pdev)
586 ret = snd_card_free(dev_get_drvdata(&pdev->dev));
587 pm_runtime_disable(&pdev->dev);
592 static void hda_tegra_shutdown(struct platform_device *pdev)
594 struct snd_card *card = dev_get_drvdata(&pdev->dev);
599 chip = card->private_data;
600 if (chip && chip->running)
604 static struct platform_driver tegra_platform_hda = {
608 .of_match_table = hda_tegra_match,
610 .probe = hda_tegra_probe,
611 .remove = hda_tegra_remove,
612 .shutdown = hda_tegra_shutdown,
614 module_platform_driver(tegra_platform_hda);
616 MODULE_DESCRIPTION("Tegra HDA bus driver");
617 MODULE_LICENSE("GPL v2");